1/* 2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8/dts-v1/; 9 10#include "dra74x.dtsi" 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/clk/ti-dra7-atl.h> 13#include <dt-bindings/input/input.h> 14 15/ { 16 model = "TI DRA742"; 17 compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7"; 18 19 chosen { 20 stdout-path = &uart1; 21 tick-timer = &timer2; 22 }; 23 24 memory@0 { 25 device_type = "memory"; 26 reg = <0x0 0x80000000 0x0 0x60000000>; /* 1536 MB */ 27 }; 28 29 evm_3v3_sd: fixedregulator-sd { 30 compatible = "regulator-fixed"; 31 regulator-name = "evm_3v3_sd"; 32 regulator-min-microvolt = <3300000>; 33 regulator-max-microvolt = <3300000>; 34 enable-active-high; 35 gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>; 36 }; 37 38 evm_3v3_sw: fixedregulator-evm_3v3_sw { 39 compatible = "regulator-fixed"; 40 regulator-name = "evm_3v3_sw"; 41 vin-supply = <&sysen1>; 42 regulator-min-microvolt = <3300000>; 43 regulator-max-microvolt = <3300000>; 44 }; 45 46 aic_dvdd: fixedregulator-aic_dvdd { 47 /* TPS77018DBVT */ 48 compatible = "regulator-fixed"; 49 regulator-name = "aic_dvdd"; 50 vin-supply = <&evm_3v3_sw>; 51 regulator-min-microvolt = <1800000>; 52 regulator-max-microvolt = <1800000>; 53 }; 54 55 extcon_usb1: extcon_usb1 { 56 compatible = "linux,extcon-usb-gpio"; 57 id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>; 58 }; 59 60 extcon_usb2: extcon_usb2 { 61 compatible = "linux,extcon-usb-gpio"; 62 id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>; 63 }; 64 65 vtt_fixed: fixedregulator-vtt { 66 compatible = "regulator-fixed"; 67 regulator-name = "vtt_fixed"; 68 regulator-min-microvolt = <1350000>; 69 regulator-max-microvolt = <1350000>; 70 regulator-always-on; 71 regulator-boot-on; 72 enable-active-high; 73 vin-supply = <&sysen2>; 74 gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>; 75 }; 76 77 sound0: sound0 { 78 compatible = "simple-audio-card"; 79 simple-audio-card,name = "DRA7xx-EVM"; 80 simple-audio-card,widgets = 81 "Headphone", "Headphone Jack", 82 "Line", "Line Out", 83 "Microphone", "Mic Jack", 84 "Line", "Line In"; 85 simple-audio-card,routing = 86 "Headphone Jack", "HPLOUT", 87 "Headphone Jack", "HPROUT", 88 "Line Out", "LLOUT", 89 "Line Out", "RLOUT", 90 "MIC3L", "Mic Jack", 91 "MIC3R", "Mic Jack", 92 "Mic Jack", "Mic Bias", 93 "LINE1L", "Line In", 94 "LINE1R", "Line In"; 95 simple-audio-card,format = "dsp_b"; 96 simple-audio-card,bitclock-master = <&sound0_master>; 97 simple-audio-card,frame-master = <&sound0_master>; 98 simple-audio-card,bitclock-inversion; 99 100 sound0_master: simple-audio-card,cpu { 101 sound-dai = <&mcasp3>; 102 system-clock-frequency = <5644800>; 103 }; 104 105 simple-audio-card,codec { 106 sound-dai = <&tlv320aic3106>; 107 clocks = <&atl_clkin2_ck>; 108 }; 109 }; 110 111 leds { 112 compatible = "gpio-leds"; 113 led0 { 114 label = "dra7:usr1"; 115 gpios = <&pcf_lcd 4 GPIO_ACTIVE_LOW>; 116 default-state = "off"; 117 }; 118 119 led1 { 120 label = "dra7:usr2"; 121 gpios = <&pcf_lcd 5 GPIO_ACTIVE_LOW>; 122 default-state = "off"; 123 }; 124 125 led2 { 126 label = "dra7:usr3"; 127 gpios = <&pcf_lcd 6 GPIO_ACTIVE_LOW>; 128 default-state = "off"; 129 }; 130 131 led3 { 132 label = "dra7:usr4"; 133 gpios = <&pcf_lcd 7 GPIO_ACTIVE_LOW>; 134 default-state = "off"; 135 }; 136 }; 137 138 gpio_keys { 139 compatible = "gpio-keys"; 140 #address-cells = <1>; 141 #size-cells = <0>; 142 autorepeat; 143 144 USER1 { 145 label = "btnUser1"; 146 linux,code = <BTN_0>; 147 gpios = <&pcf_lcd 2 GPIO_ACTIVE_LOW>; 148 }; 149 150 USER2 { 151 label = "btnUser2"; 152 linux,code = <BTN_1>; 153 gpios = <&pcf_lcd 3 GPIO_ACTIVE_LOW>; 154 }; 155 }; 156}; 157 158&dra7_pmx_core { 159 pinctrl-names = "default"; 160 pinctrl-0 = <&vtt_pin>; 161 162 vtt_pin: pinmux_vtt_pin { 163 pinctrl-single,pins = < 164 DRA7XX_CORE_IOPAD(0x37b4, PIN_OUTPUT | MUX_MODE14) /* spi1_cs1.gpio7_11 */ 165 >; 166 }; 167 168 i2c1_pins: pinmux_i2c1_pins { 169 pinctrl-single,pins = < 170 DRA7XX_CORE_IOPAD(0x3800, PIN_INPUT | MUX_MODE0) /* i2c1_sda */ 171 DRA7XX_CORE_IOPAD(0x3804, PIN_INPUT | MUX_MODE0) /* i2c1_scl */ 172 >; 173 }; 174 175 i2c2_pins: pinmux_i2c2_pins { 176 pinctrl-single,pins = < 177 DRA7XX_CORE_IOPAD(0x3808, PIN_INPUT | MUX_MODE0) /* i2c2_sda */ 178 DRA7XX_CORE_IOPAD(0x380c, PIN_INPUT | MUX_MODE0) /* i2c2_scl */ 179 >; 180 }; 181 182 i2c3_pins: pinmux_i2c3_pins { 183 pinctrl-single,pins = < 184 DRA7XX_CORE_IOPAD(0x3688, PIN_INPUT | MUX_MODE9) /* gpio6_14.i2c3_sda */ 185 DRA7XX_CORE_IOPAD(0x368c, PIN_INPUT | MUX_MODE9) /* gpio6_15.i2c3_scl */ 186 >; 187 }; 188 189 mcspi1_pins: pinmux_mcspi1_pins { 190 pinctrl-single,pins = < 191 DRA7XX_CORE_IOPAD(0x37a4, PIN_INPUT | MUX_MODE0) /* spi1_sclk */ 192 DRA7XX_CORE_IOPAD(0x37a8, PIN_INPUT | MUX_MODE0) /* spi1_d1 */ 193 DRA7XX_CORE_IOPAD(0x37ac, PIN_INPUT | MUX_MODE0) /* spi1_d0 */ 194 DRA7XX_CORE_IOPAD(0x37b0, PIN_INPUT_SLEW | MUX_MODE0) /* spi1_cs0 */ 195 DRA7XX_CORE_IOPAD(0x37b8, PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs2.hdmi1_hpd */ 196 DRA7XX_CORE_IOPAD(0x37bc, PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs3.hdmi1_cec */ 197 >; 198 }; 199 200 mcspi2_pins: pinmux_mcspi2_pins { 201 pinctrl-single,pins = < 202 DRA7XX_CORE_IOPAD(0x37c0, PIN_INPUT | MUX_MODE0) /* spi2_sclk */ 203 DRA7XX_CORE_IOPAD(0x37c4, PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */ 204 DRA7XX_CORE_IOPAD(0x37c8, PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */ 205 DRA7XX_CORE_IOPAD(0x37cc, PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs0 */ 206 >; 207 }; 208 209 uart1_pins: pinmux_uart1_pins { 210 pinctrl-single,pins = < 211 DRA7XX_CORE_IOPAD(0x37e0, PIN_INPUT_SLEW | MUX_MODE0) /* uart1_rxd */ 212 DRA7XX_CORE_IOPAD(0x37e4, PIN_INPUT_SLEW | MUX_MODE0) /* uart1_txd */ 213 DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT | MUX_MODE3) /* uart1_ctsn */ 214 DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT | MUX_MODE3) /* uart1_rtsn */ 215 >; 216 }; 217 218 uart2_pins: pinmux_uart2_pins { 219 pinctrl-single,pins = < 220 DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT | MUX_MODE0) /* uart2_rxd */ 221 DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT | MUX_MODE0) /* uart2_txd */ 222 DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT | MUX_MODE0) /* uart2_ctsn */ 223 DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT | MUX_MODE0) /* uart2_rtsn */ 224 >; 225 }; 226 227 uart3_pins: pinmux_uart3_pins { 228 pinctrl-single,pins = < 229 DRA7XX_CORE_IOPAD(0x3648, PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd */ 230 DRA7XX_CORE_IOPAD(0x364c, PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */ 231 >; 232 }; 233 234 usb1_pins: pinmux_usb1_pins { 235 pinctrl-single,pins = < 236 DRA7XX_CORE_IOPAD(0x3680, PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */ 237 >; 238 }; 239 240 usb2_pins: pinmux_usb2_pins { 241 pinctrl-single,pins = < 242 DRA7XX_CORE_IOPAD(0x3684, PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */ 243 >; 244 }; 245 246 nand_flash_x16: nand_flash_x16 { 247 /* On DRA7 EVM, GPMC_WPN and NAND_BOOTn comes from DIP switch 248 * So NAND flash requires following switch settings: 249 * SW5.1 (NAND_BOOTn) = ON (LOW) 250 * SW5.9 (GPMC_WPN) = OFF (HIGH) 251 */ 252 pinctrl-single,pins = < 253 DRA7XX_CORE_IOPAD(0x3400, PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */ 254 DRA7XX_CORE_IOPAD(0x3404, PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */ 255 DRA7XX_CORE_IOPAD(0x3408, PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */ 256 DRA7XX_CORE_IOPAD(0x340c, PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */ 257 DRA7XX_CORE_IOPAD(0x3410, PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */ 258 DRA7XX_CORE_IOPAD(0x3414, PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */ 259 DRA7XX_CORE_IOPAD(0x3418, PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */ 260 DRA7XX_CORE_IOPAD(0x341c, PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */ 261 DRA7XX_CORE_IOPAD(0x3420, PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */ 262 DRA7XX_CORE_IOPAD(0x3424, PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */ 263 DRA7XX_CORE_IOPAD(0x3428, PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */ 264 DRA7XX_CORE_IOPAD(0x342c, PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */ 265 DRA7XX_CORE_IOPAD(0x3430, PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */ 266 DRA7XX_CORE_IOPAD(0x3434, PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */ 267 DRA7XX_CORE_IOPAD(0x3438, PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */ 268 DRA7XX_CORE_IOPAD(0x343c, PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */ 269 DRA7XX_CORE_IOPAD(0x34d8, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0 */ 270 DRA7XX_CORE_IOPAD(0x34cc, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */ 271 DRA7XX_CORE_IOPAD(0x34b4, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn0 */ 272 DRA7XX_CORE_IOPAD(0x34c4, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */ 273 DRA7XX_CORE_IOPAD(0x34c8, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */ 274 DRA7XX_CORE_IOPAD(0x34d0, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle */ 275 >; 276 }; 277 278 cpsw_default: cpsw_default { 279 pinctrl-single,pins = < 280 /* Slave 1 */ 281 DRA7XX_CORE_IOPAD(0x3650, PIN_OUTPUT | MUX_MODE0) /* rgmii0_txc.rgmii0_txc */ 282 DRA7XX_CORE_IOPAD(0x3654, PIN_OUTPUT | MUX_MODE0) /* rgmii0_txctl.rgmii0_txctl */ 283 DRA7XX_CORE_IOPAD(0x3658, PIN_OUTPUT | MUX_MODE0) /* rgmii0_td3.rgmii0_txd3 */ 284 DRA7XX_CORE_IOPAD(0x365c, PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd2.rgmii0_txd2 */ 285 DRA7XX_CORE_IOPAD(0x3660, PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd1.rgmii0_txd1 */ 286 DRA7XX_CORE_IOPAD(0x3664, PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd0.rgmii0_txd0 */ 287 DRA7XX_CORE_IOPAD(0x3668, PIN_INPUT | MUX_MODE0) /* rgmii0_rxc.rgmii0_rxc */ 288 DRA7XX_CORE_IOPAD(0x366c, PIN_INPUT | MUX_MODE0) /* rgmii0_rxctl.rgmii0_rxctl */ 289 DRA7XX_CORE_IOPAD(0x3670, PIN_INPUT | MUX_MODE0) /* rgmii0_rxd3.rgmii0_rxd3 */ 290 DRA7XX_CORE_IOPAD(0x3674, PIN_INPUT | MUX_MODE0) /* rgmii0_rxd2.rgmii0_rxd2 */ 291 DRA7XX_CORE_IOPAD(0x3678, PIN_INPUT | MUX_MODE0) /* rgmii0_rxd1.rgmii0_rxd1 */ 292 DRA7XX_CORE_IOPAD(0x367c, PIN_INPUT | MUX_MODE0) /* rgmii0_rxd0.rgmii0_rxd0 */ 293 294 /* Slave 2 */ 295 DRA7XX_CORE_IOPAD(0x3598, PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_txc */ 296 DRA7XX_CORE_IOPAD(0x359c, PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */ 297 DRA7XX_CORE_IOPAD(0x35a0, PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */ 298 DRA7XX_CORE_IOPAD(0x35a4, PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */ 299 DRA7XX_CORE_IOPAD(0x35a8, PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */ 300 DRA7XX_CORE_IOPAD(0x35ac, PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */ 301 DRA7XX_CORE_IOPAD(0x35b0, PIN_INPUT | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */ 302 DRA7XX_CORE_IOPAD(0x35b4, PIN_INPUT | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */ 303 DRA7XX_CORE_IOPAD(0x35b8, PIN_INPUT | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */ 304 DRA7XX_CORE_IOPAD(0x35bc, PIN_INPUT | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */ 305 DRA7XX_CORE_IOPAD(0x35c0, PIN_INPUT | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */ 306 DRA7XX_CORE_IOPAD(0x35c4, PIN_INPUT | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */ 307 >; 308 309 }; 310 311 cpsw_sleep: cpsw_sleep { 312 pinctrl-single,pins = < 313 /* Slave 1 */ 314 DRA7XX_CORE_IOPAD(0x3650, MUX_MODE15) 315 DRA7XX_CORE_IOPAD(0x3654, MUX_MODE15) 316 DRA7XX_CORE_IOPAD(0x3658, MUX_MODE15) 317 DRA7XX_CORE_IOPAD(0x365c, MUX_MODE15) 318 DRA7XX_CORE_IOPAD(0x3660, MUX_MODE15) 319 DRA7XX_CORE_IOPAD(0x3664, MUX_MODE15) 320 DRA7XX_CORE_IOPAD(0x3668, MUX_MODE15) 321 DRA7XX_CORE_IOPAD(0x366c, MUX_MODE15) 322 DRA7XX_CORE_IOPAD(0x3670, MUX_MODE15) 323 DRA7XX_CORE_IOPAD(0x3674, MUX_MODE15) 324 DRA7XX_CORE_IOPAD(0x3678, MUX_MODE15) 325 DRA7XX_CORE_IOPAD(0x367c, MUX_MODE15) 326 327 /* Slave 2 */ 328 DRA7XX_CORE_IOPAD(0x3598, MUX_MODE15) 329 DRA7XX_CORE_IOPAD(0x359c, MUX_MODE15) 330 DRA7XX_CORE_IOPAD(0x35a0, MUX_MODE15) 331 DRA7XX_CORE_IOPAD(0x35a4, MUX_MODE15) 332 DRA7XX_CORE_IOPAD(0x35a8, MUX_MODE15) 333 DRA7XX_CORE_IOPAD(0x35ac, MUX_MODE15) 334 DRA7XX_CORE_IOPAD(0x35b0, MUX_MODE15) 335 DRA7XX_CORE_IOPAD(0x35b4, MUX_MODE15) 336 DRA7XX_CORE_IOPAD(0x35b8, MUX_MODE15) 337 DRA7XX_CORE_IOPAD(0x35bc, MUX_MODE15) 338 DRA7XX_CORE_IOPAD(0x35c0, MUX_MODE15) 339 DRA7XX_CORE_IOPAD(0x35c4, MUX_MODE15) 340 >; 341 }; 342 343 davinci_mdio_default: davinci_mdio_default { 344 pinctrl-single,pins = < 345 DRA7XX_CORE_IOPAD(0x363c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_d.mdio_d */ 346 DRA7XX_CORE_IOPAD(0x3640, PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ 347 >; 348 }; 349 350 davinci_mdio_sleep: davinci_mdio_sleep { 351 pinctrl-single,pins = < 352 DRA7XX_CORE_IOPAD(0x363c, MUX_MODE15) 353 DRA7XX_CORE_IOPAD(0x3640, MUX_MODE15) 354 >; 355 }; 356 357 dcan1_pins_default: dcan1_pins_default { 358 pinctrl-single,pins = < 359 DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */ 360 DRA7XX_CORE_IOPAD(0x3818, PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */ 361 >; 362 }; 363 364 dcan1_pins_sleep: dcan1_pins_sleep { 365 pinctrl-single,pins = < 366 DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP) /* dcan1_tx.off */ 367 DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 | PULL_UP) /* wakeup0.off */ 368 >; 369 }; 370 371 atl_pins: pinmux_atl_pins { 372 pinctrl-single,pins = < 373 DRA7XX_CORE_IOPAD(0x3698, PIN_OUTPUT | MUX_MODE5) /* xref_clk1.atl_clk1 */ 374 DRA7XX_CORE_IOPAD(0x369c, PIN_OUTPUT | MUX_MODE5) /* xref_clk2.atl_clk2 */ 375 >; 376 }; 377 378 mcasp3_pins: pinmux_mcasp3_pins { 379 pinctrl-single,pins = < 380 DRA7XX_CORE_IOPAD(0x3724, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_aclkx */ 381 DRA7XX_CORE_IOPAD(0x3728, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_fsx */ 382 DRA7XX_CORE_IOPAD(0x372c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr0 */ 383 DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr1 */ 384 >; 385 }; 386 387 mcasp3_sleep_pins: pinmux_mcasp3_sleep_pins { 388 pinctrl-single,pins = < 389 DRA7XX_CORE_IOPAD(0x3724, MUX_MODE15) 390 DRA7XX_CORE_IOPAD(0x3728, MUX_MODE15) 391 DRA7XX_CORE_IOPAD(0x372c, MUX_MODE15) 392 DRA7XX_CORE_IOPAD(0x3730, MUX_MODE15) 393 >; 394 }; 395}; 396 397&i2c1 { 398 status = "okay"; 399 pinctrl-names = "default"; 400 pinctrl-0 = <&i2c1_pins>; 401 clock-frequency = <400000>; 402 403 tps659038: tps659038@58 { 404 compatible = "ti,tps659038"; 405 reg = <0x58>; 406 407 tps659038_pmic { 408 compatible = "ti,tps659038-pmic"; 409 410 regulators { 411 smps123_reg: smps123 { 412 /* VDD_MPU */ 413 regulator-name = "smps123"; 414 regulator-min-microvolt = < 850000>; 415 regulator-max-microvolt = <1250000>; 416 regulator-always-on; 417 regulator-boot-on; 418 }; 419 420 smps45_reg: smps45 { 421 /* VDD_DSPEVE */ 422 regulator-name = "smps45"; 423 regulator-min-microvolt = < 850000>; 424 regulator-max-microvolt = <1250000>; 425 regulator-always-on; 426 regulator-boot-on; 427 }; 428 429 smps6_reg: smps6 { 430 /* VDD_GPU - over VDD_SMPS6 */ 431 regulator-name = "smps6"; 432 regulator-min-microvolt = <850000>; 433 regulator-max-microvolt = <1250000>; 434 regulator-always-on; 435 regulator-boot-on; 436 }; 437 438 smps7_reg: smps7 { 439 /* CORE_VDD */ 440 regulator-name = "smps7"; 441 regulator-min-microvolt = <850000>; 442 regulator-max-microvolt = <1150000>; 443 regulator-always-on; 444 regulator-boot-on; 445 }; 446 447 smps8_reg: smps8 { 448 /* VDD_IVAHD */ 449 regulator-name = "smps8"; 450 regulator-min-microvolt = < 850000>; 451 regulator-max-microvolt = <1250000>; 452 regulator-always-on; 453 regulator-boot-on; 454 }; 455 456 smps9_reg: smps9 { 457 /* VDDS1V8 */ 458 regulator-name = "smps9"; 459 regulator-min-microvolt = <1800000>; 460 regulator-max-microvolt = <1800000>; 461 regulator-always-on; 462 regulator-boot-on; 463 }; 464 465 ldo1_reg: ldo1 { 466 /* LDO1_OUT --> SDIO */ 467 regulator-name = "ldo1"; 468 regulator-min-microvolt = <1800000>; 469 regulator-max-microvolt = <3300000>; 470 regulator-always-on; 471 regulator-boot-on; 472 }; 473 474 ldo2_reg: ldo2 { 475 /* VDD_RTCIO */ 476 /* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */ 477 regulator-name = "ldo2"; 478 regulator-min-microvolt = <3300000>; 479 regulator-max-microvolt = <3300000>; 480 regulator-always-on; 481 regulator-boot-on; 482 }; 483 484 ldo3_reg: ldo3 { 485 /* VDDA_1V8_PHY */ 486 regulator-name = "ldo3"; 487 regulator-min-microvolt = <1800000>; 488 regulator-max-microvolt = <1800000>; 489 regulator-always-on; 490 regulator-boot-on; 491 }; 492 493 ldo9_reg: ldo9 { 494 /* VDD_RTC */ 495 regulator-name = "ldo9"; 496 regulator-min-microvolt = <1050000>; 497 regulator-max-microvolt = <1050000>; 498 regulator-always-on; 499 regulator-boot-on; 500 regulator-allow-bypass; 501 }; 502 503 ldoln_reg: ldoln { 504 /* VDDA_1V8_PLL */ 505 regulator-name = "ldoln"; 506 regulator-min-microvolt = <1800000>; 507 regulator-max-microvolt = <1800000>; 508 regulator-always-on; 509 regulator-boot-on; 510 }; 511 512 ldousb_reg: ldousb { 513 /* VDDA_3V_USB: VDDA_USBHS33 */ 514 regulator-name = "ldousb"; 515 regulator-min-microvolt = <3300000>; 516 regulator-max-microvolt = <3300000>; 517 regulator-boot-on; 518 }; 519 520 /* REGEN1 is unused */ 521 522 regen2: regen2 { 523 /* Needed for PMIC internal resources */ 524 regulator-name = "regen2"; 525 regulator-boot-on; 526 regulator-always-on; 527 }; 528 529 /* REGEN3 is unused */ 530 531 sysen1: sysen1 { 532 /* PMIC_REGEN_3V3 */ 533 regulator-name = "sysen1"; 534 regulator-boot-on; 535 regulator-always-on; 536 }; 537 538 sysen2: sysen2 { 539 /* PMIC_REGEN_DDR */ 540 regulator-name = "sysen2"; 541 regulator-boot-on; 542 regulator-always-on; 543 }; 544 }; 545 }; 546 }; 547 548 pcf_lcd: gpio@20 { 549 compatible = "ti,pcf8575", "nxp,pcf8575"; 550 reg = <0x20>; 551 gpio-controller; 552 #gpio-cells = <2>; 553 interrupt-parent = <&gpio6>; 554 interrupts = <11 IRQ_TYPE_EDGE_FALLING>; 555 interrupt-controller; 556 #interrupt-cells = <2>; 557 }; 558 559 pcf_gpio_21: gpio@21 { 560 compatible = "ti,pcf8575", "nxp,pcf8575"; 561 reg = <0x21>; 562 lines-initial-states = <0x1408>; 563 gpio-controller; 564 #gpio-cells = <2>; 565 interrupt-parent = <&gpio6>; 566 interrupts = <11 IRQ_TYPE_EDGE_FALLING>; 567 interrupt-controller; 568 #interrupt-cells = <2>; 569 u-boot,i2c-offset-len = <0>; 570 }; 571 572 tlv320aic3106: tlv320aic3106@19 { 573 #sound-dai-cells = <0>; 574 compatible = "ti,tlv320aic3106"; 575 reg = <0x19>; 576 adc-settle-ms = <40>; 577 ai3x-micbias-vg = <1>; /* 2.0V */ 578 status = "okay"; 579 580 /* Regulators */ 581 AVDD-supply = <&evm_3v3_sw>; 582 IOVDD-supply = <&evm_3v3_sw>; 583 DRVDD-supply = <&evm_3v3_sw>; 584 DVDD-supply = <&aic_dvdd>; 585 }; 586}; 587 588&i2c2 { 589 status = "okay"; 590 pinctrl-names = "default"; 591 pinctrl-0 = <&i2c2_pins>; 592 clock-frequency = <400000>; 593 594 pcf_hdmi: gpio@26 { 595 compatible = "ti,pcf8575", "nxp,pcf8575"; 596 reg = <0x26>; 597 gpio-controller; 598 #gpio-cells = <2>; 599 p1 { 600 /* vin6_sel_s0: high: VIN6, low: audio */ 601 gpio-hog; 602 gpios = <1 GPIO_ACTIVE_HIGH>; 603 output-low; 604 line-name = "vin6_sel_s0"; 605 }; 606 }; 607}; 608 609&i2c3 { 610 status = "okay"; 611 pinctrl-names = "default"; 612 pinctrl-0 = <&i2c3_pins>; 613 clock-frequency = <400000>; 614}; 615 616&mcspi1 { 617 status = "okay"; 618 pinctrl-names = "default"; 619 pinctrl-0 = <&mcspi1_pins>; 620}; 621 622&mcspi2 { 623 status = "okay"; 624 pinctrl-names = "default"; 625 pinctrl-0 = <&mcspi2_pins>; 626}; 627 628&uart1 { 629 status = "okay"; 630 pinctrl-names = "default"; 631 pinctrl-0 = <&uart1_pins>; 632 interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 633 <&dra7_pmx_core 0x3e0>; 634}; 635 636&uart2 { 637 status = "okay"; 638 pinctrl-names = "default"; 639 pinctrl-0 = <&uart2_pins>; 640}; 641 642&uart3 { 643 status = "okay"; 644 pinctrl-names = "default"; 645 pinctrl-0 = <&uart3_pins>; 646}; 647 648&mmc1 { 649 status = "okay"; 650 vmmc-supply = <&evm_3v3_sd>; 651 vmmc_aux-supply = <&ldo1_reg>; 652 bus-width = <4>; 653 /* 654 * SDCD signal is not being used here - using the fact that GPIO mode 655 * is always hardwired. 656 */ 657 cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; 658}; 659 660&mmc2 { 661 status = "okay"; 662 vmmc-supply = <&evm_3v3_sw>; 663 bus-width = <8>; 664}; 665 666&cpu0 { 667 cpu0-supply = <&smps123_reg>; 668}; 669 670&qspi { 671 status = "okay"; 672 673 spi-max-frequency = <76800000>; 674 m25p80@0 { 675 compatible = "s25fl256s1", "spi-flash"; 676 spi-max-frequency = <76800000>; 677 reg = <0>; 678 spi-tx-bus-width = <1>; 679 spi-rx-bus-width = <4>; 680 #address-cells = <1>; 681 #size-cells = <1>; 682 683 /* MTD partition table. 684 * The ROM checks the first four physical blocks 685 * for a valid file to boot and the flash here is 686 * 64KiB block size. 687 */ 688 partition@0 { 689 label = "QSPI.SPL"; 690 reg = <0x00000000 0x000010000>; 691 }; 692 partition@1 { 693 label = "QSPI.SPL.backup1"; 694 reg = <0x00010000 0x00010000>; 695 }; 696 partition@2 { 697 label = "QSPI.SPL.backup2"; 698 reg = <0x00020000 0x00010000>; 699 }; 700 partition@3 { 701 label = "QSPI.SPL.backup3"; 702 reg = <0x00030000 0x00010000>; 703 }; 704 partition@4 { 705 label = "QSPI.u-boot"; 706 reg = <0x00040000 0x00100000>; 707 }; 708 partition@5 { 709 label = "QSPI.u-boot-spl-os"; 710 reg = <0x00140000 0x00080000>; 711 }; 712 partition@6 { 713 label = "QSPI.u-boot-env"; 714 reg = <0x001c0000 0x00010000>; 715 }; 716 partition@7 { 717 label = "QSPI.u-boot-env.backup1"; 718 reg = <0x001d0000 0x0010000>; 719 }; 720 partition@8 { 721 label = "QSPI.kernel"; 722 reg = <0x001e0000 0x0800000>; 723 }; 724 partition@9 { 725 label = "QSPI.file-system"; 726 reg = <0x009e0000 0x01620000>; 727 }; 728 }; 729}; 730 731&omap_dwc3_1 { 732 extcon = <&extcon_usb1>; 733}; 734 735&omap_dwc3_2 { 736 extcon = <&extcon_usb2>; 737}; 738 739&usb1 { 740 dr_mode = "peripheral"; 741 pinctrl-names = "default"; 742 pinctrl-0 = <&usb1_pins>; 743}; 744 745&usb2 { 746 dr_mode = "host"; 747 pinctrl-names = "default"; 748 pinctrl-0 = <&usb2_pins>; 749}; 750 751&elm { 752 status = "okay"; 753}; 754 755&gpmc { 756 status = "okay"; 757 pinctrl-names = "default"; 758 pinctrl-0 = <&nand_flash_x16>; 759 ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */ 760 nand@0,0 { 761 compatible = "ti,omap2-nand"; 762 reg = <0 0 4>; /* device IO registers */ 763 interrupt-parent = <&gpmc>; 764 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ 765 <1 IRQ_TYPE_NONE>; /* termcount */ 766 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */ 767 ti,nand-ecc-opt = "bch8"; 768 ti,elm-id = <&elm>; 769 nand-bus-width = <16>; 770 gpmc,device-width = <2>; 771 gpmc,sync-clk-ps = <0>; 772 gpmc,cs-on-ns = <0>; 773 gpmc,cs-rd-off-ns = <80>; 774 gpmc,cs-wr-off-ns = <80>; 775 gpmc,adv-on-ns = <0>; 776 gpmc,adv-rd-off-ns = <60>; 777 gpmc,adv-wr-off-ns = <60>; 778 gpmc,we-on-ns = <10>; 779 gpmc,we-off-ns = <50>; 780 gpmc,oe-on-ns = <4>; 781 gpmc,oe-off-ns = <40>; 782 gpmc,access-ns = <40>; 783 gpmc,wr-access-ns = <80>; 784 gpmc,rd-cycle-ns = <80>; 785 gpmc,wr-cycle-ns = <80>; 786 gpmc,bus-turnaround-ns = <0>; 787 gpmc,cycle2cycle-delay-ns = <0>; 788 gpmc,clk-activation-ns = <0>; 789 gpmc,wr-data-mux-bus-ns = <0>; 790 /* MTD partition table */ 791 /* All SPL-* partitions are sized to minimal length 792 * which can be independently programmable. For 793 * NAND flash this is equal to size of erase-block */ 794 #address-cells = <1>; 795 #size-cells = <1>; 796 partition@0 { 797 label = "NAND.SPL"; 798 reg = <0x00000000 0x000020000>; 799 }; 800 partition@1 { 801 label = "NAND.SPL.backup1"; 802 reg = <0x00020000 0x00020000>; 803 }; 804 partition@2 { 805 label = "NAND.SPL.backup2"; 806 reg = <0x00040000 0x00020000>; 807 }; 808 partition@3 { 809 label = "NAND.SPL.backup3"; 810 reg = <0x00060000 0x00020000>; 811 }; 812 partition@4 { 813 label = "NAND.u-boot-spl-os"; 814 reg = <0x00080000 0x00040000>; 815 }; 816 partition@5 { 817 label = "NAND.u-boot"; 818 reg = <0x000c0000 0x00100000>; 819 }; 820 partition@6 { 821 label = "NAND.u-boot-env"; 822 reg = <0x001c0000 0x00020000>; 823 }; 824 partition@7 { 825 label = "NAND.u-boot-env.backup1"; 826 reg = <0x001e0000 0x00020000>; 827 }; 828 partition@8 { 829 label = "NAND.kernel"; 830 reg = <0x00200000 0x00800000>; 831 }; 832 partition@9 { 833 label = "NAND.file-system"; 834 reg = <0x00a00000 0x0f600000>; 835 }; 836 }; 837}; 838 839&usb2_phy1 { 840 phy-supply = <&ldousb_reg>; 841}; 842 843&usb2_phy2 { 844 phy-supply = <&ldousb_reg>; 845}; 846 847&gpio7 { 848 ti,no-reset-on-init; 849 ti,no-idle-on-init; 850}; 851 852&mac { 853 status = "okay"; 854 pinctrl-names = "default", "sleep"; 855 pinctrl-0 = <&cpsw_default>; 856 pinctrl-1 = <&cpsw_sleep>; 857 dual_emac; 858}; 859 860&cpsw_emac0 { 861 phy_id = <&davinci_mdio>, <2>; 862 phy-mode = "rgmii"; 863 dual_emac_res_vlan = <1>; 864}; 865 866&cpsw_emac1 { 867 phy_id = <&davinci_mdio>, <3>; 868 phy-mode = "rgmii"; 869 dual_emac_res_vlan = <2>; 870}; 871 872&davinci_mdio { 873 pinctrl-names = "default", "sleep"; 874 pinctrl-0 = <&davinci_mdio_default>; 875 pinctrl-1 = <&davinci_mdio_sleep>; 876}; 877 878&dcan1 { 879 status = "ok"; 880 pinctrl-names = "default", "sleep", "active"; 881 pinctrl-0 = <&dcan1_pins_sleep>; 882 pinctrl-1 = <&dcan1_pins_sleep>; 883 pinctrl-2 = <&dcan1_pins_default>; 884}; 885 886&atl { 887 pinctrl-names = "default"; 888 pinctrl-0 = <&atl_pins>; 889 890 assigned-clocks = <&abe_dpll_sys_clk_mux>, 891 <&atl_gfclk_mux>, 892 <&dpll_abe_ck>, 893 <&dpll_abe_m2x2_ck>, 894 <&atl_clkin2_ck>; 895 assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>; 896 assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>; 897 898 status = "okay"; 899 900 atl2 { 901 bws = <DRA7_ATL_WS_MCASP2_FSX>; 902 aws = <DRA7_ATL_WS_MCASP3_FSX>; 903 }; 904}; 905 906&mcasp3 { 907 #sound-dai-cells = <0>; 908 pinctrl-names = "default", "sleep"; 909 pinctrl-0 = <&mcasp3_pins>; 910 pinctrl-1 = <&mcasp3_sleep_pins>; 911 912 assigned-clocks = <&mcasp3_ahclkx_mux>; 913 assigned-clock-parents = <&atl_clkin2_ck>; 914 915 status = "okay"; 916 917 op-mode = <0>; /* MCASP_IIS_MODE */ 918 tdm-slots = <2>; 919 /* 4 serializer */ 920 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ 921 1 2 0 0 922 >; 923 tx-num-evt = <32>; 924 rx-num-evt = <32>; 925}; 926 927&mailbox5 { 928 status = "okay"; 929 mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { 930 status = "okay"; 931 }; 932 mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { 933 status = "okay"; 934 }; 935}; 936 937&mailbox6 { 938 status = "okay"; 939 mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { 940 status = "okay"; 941 }; 942 mbox_dsp2_ipc3x: mbox_dsp2_ipc3x { 943 status = "okay"; 944 }; 945}; 946