1/* 2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8/dts-v1/; 9 10#include "dra74x.dtsi" 11#include <dt-bindings/gpio/gpio.h> 12 13/ { 14 model = "TI DRA742"; 15 compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7"; 16 17 chosen { 18 stdout-path = &uart1; 19 }; 20 21 memory { 22 device_type = "memory"; 23 reg = <0x80000000 0x60000000>; /* 1536 MB */ 24 }; 25 26 mmc2_3v3: fixedregulator-mmc2 { 27 compatible = "regulator-fixed"; 28 regulator-name = "mmc2_3v3"; 29 regulator-min-microvolt = <3300000>; 30 regulator-max-microvolt = <3300000>; 31 }; 32 33 extcon_usb1: extcon_usb1 { 34 compatible = "linux,extcon-usb-gpio"; 35 id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>; 36 }; 37 38 extcon_usb2: extcon_usb2 { 39 compatible = "linux,extcon-usb-gpio"; 40 id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>; 41 }; 42 43 vtt_fixed: fixedregulator-vtt { 44 compatible = "regulator-fixed"; 45 regulator-name = "vtt_fixed"; 46 regulator-min-microvolt = <1350000>; 47 regulator-max-microvolt = <1350000>; 48 regulator-always-on; 49 regulator-boot-on; 50 enable-active-high; 51 gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>; 52 }; 53}; 54 55&dra7_pmx_core { 56 pinctrl-names = "default"; 57 pinctrl-0 = <&vtt_pin>; 58 59 vtt_pin: pinmux_vtt_pin { 60 pinctrl-single,pins = < 61 0x3b4 (PIN_OUTPUT | MUX_MODE14) /* spi1_cs1.gpio7_11 */ 62 >; 63 }; 64 65 i2c1_pins: pinmux_i2c1_pins { 66 pinctrl-single,pins = < 67 0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda */ 68 0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl */ 69 >; 70 }; 71 72 i2c2_pins: pinmux_i2c2_pins { 73 pinctrl-single,pins = < 74 0x408 (PIN_INPUT | MUX_MODE0) /* i2c2_sda */ 75 0x40c (PIN_INPUT | MUX_MODE0) /* i2c2_scl */ 76 >; 77 }; 78 79 i2c3_pins: pinmux_i2c3_pins { 80 pinctrl-single,pins = < 81 0x288 (PIN_INPUT | MUX_MODE9) /* gpio6_14.i2c3_sda */ 82 0x28c (PIN_INPUT | MUX_MODE9) /* gpio6_15.i2c3_scl */ 83 >; 84 }; 85 86 mcspi1_pins: pinmux_mcspi1_pins { 87 pinctrl-single,pins = < 88 0x3a4 (PIN_INPUT | MUX_MODE0) /* spi1_sclk */ 89 0x3a8 (PIN_INPUT | MUX_MODE0) /* spi1_d1 */ 90 0x3ac (PIN_INPUT | MUX_MODE0) /* spi1_d0 */ 91 0x3b0 (PIN_INPUT_SLEW | MUX_MODE0) /* spi1_cs0 */ 92 0x3b8 (PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs2.hdmi1_hpd */ 93 0x3bc (PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs3.hdmi1_cec */ 94 >; 95 }; 96 97 mcspi2_pins: pinmux_mcspi2_pins { 98 pinctrl-single,pins = < 99 0x3c0 (PIN_INPUT | MUX_MODE0) /* spi2_sclk */ 100 0x3c4 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */ 101 0x3c8 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */ 102 0x3cc (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs0 */ 103 >; 104 }; 105 106 uart1_pins: pinmux_uart1_pins { 107 pinctrl-single,pins = < 108 0x3e0 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_rxd */ 109 0x3e4 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_txd */ 110 0x3e8 (PIN_INPUT | MUX_MODE3) /* uart1_ctsn */ 111 0x3ec (PIN_INPUT | MUX_MODE3) /* uart1_rtsn */ 112 >; 113 }; 114 115 uart2_pins: pinmux_uart2_pins { 116 pinctrl-single,pins = < 117 0x3f0 (PIN_INPUT | MUX_MODE0) /* uart2_rxd */ 118 0x3f4 (PIN_INPUT | MUX_MODE0) /* uart2_txd */ 119 0x3f8 (PIN_INPUT | MUX_MODE0) /* uart2_ctsn */ 120 0x3fc (PIN_INPUT | MUX_MODE0) /* uart2_rtsn */ 121 >; 122 }; 123 124 uart3_pins: pinmux_uart3_pins { 125 pinctrl-single,pins = < 126 0x248 (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd */ 127 0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */ 128 >; 129 }; 130 131 qspi1_pins: pinmux_qspi1_pins { 132 pinctrl-single,pins = < 133 0x4c (PIN_INPUT | MUX_MODE1) /* gpmc_a3.qspi1_cs2 */ 134 0x50 (PIN_INPUT | MUX_MODE1) /* gpmc_a4.qspi1_cs3 */ 135 0x74 (PIN_INPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */ 136 0x78 (PIN_INPUT | MUX_MODE1) /* gpmc_a14.qspi1_d3 */ 137 0x7c (PIN_INPUT | MUX_MODE1) /* gpmc_a15.qspi1_d2 */ 138 0x80 (PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */ 139 0x84 (PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d0 */ 140 0x88 (PIN_INPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */ 141 0xb8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs2.qspi1_cs0 */ 142 0xbc (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs3.qspi1_cs1 */ 143 >; 144 }; 145 146 usb1_pins: pinmux_usb1_pins { 147 pinctrl-single,pins = < 148 0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */ 149 >; 150 }; 151 152 usb2_pins: pinmux_usb2_pins { 153 pinctrl-single,pins = < 154 0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */ 155 >; 156 }; 157 158 nand_flash_x16: nand_flash_x16 { 159 /* On DRA7 EVM, GPMC_WPN and NAND_BOOTn comes from DIP switch 160 * So NAND flash requires following switch settings: 161 * SW5.9 (GPMC_WPN) = LOW 162 * SW5.1 (NAND_BOOTn) = HIGH */ 163 pinctrl-single,pins = < 164 0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */ 165 0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */ 166 0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */ 167 0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */ 168 0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */ 169 0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */ 170 0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */ 171 0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */ 172 0x20 (PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */ 173 0x24 (PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */ 174 0x28 (PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */ 175 0x2c (PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */ 176 0x30 (PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */ 177 0x34 (PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */ 178 0x38 (PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */ 179 0x3c (PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */ 180 0xd8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0 */ 181 0xcc (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */ 182 0xb4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn0 */ 183 0xc4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */ 184 0xc8 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */ 185 0xd0 (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle */ 186 >; 187 }; 188 189 cpsw_default: cpsw_default { 190 pinctrl-single,pins = < 191 /* Slave 1 */ 192 0x250 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txc.rgmii0_txc */ 193 0x254 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txctl.rgmii0_txctl */ 194 0x258 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_td3.rgmii0_txd3 */ 195 0x25c (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd2.rgmii0_txd2 */ 196 0x260 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd1.rgmii0_txd1 */ 197 0x264 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd0.rgmii0_txd0 */ 198 0x268 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxc.rgmii0_rxc */ 199 0x26c (PIN_INPUT | MUX_MODE0) /* rgmii0_rxctl.rgmii0_rxctl */ 200 0x270 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd3.rgmii0_rxd3 */ 201 0x274 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd2.rgmii0_rxd2 */ 202 0x278 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd1.rgmii0_rxd1 */ 203 0x27c (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd0.rgmii0_rxd0 */ 204 205 /* Slave 2 */ 206 0x198 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_txc */ 207 0x19c (PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */ 208 0x1a0 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */ 209 0x1a4 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */ 210 0x1a8 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */ 211 0x1ac (PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */ 212 0x1b0 (PIN_INPUT | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */ 213 0x1b4 (PIN_INPUT | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */ 214 0x1b8 (PIN_INPUT | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */ 215 0x1bc (PIN_INPUT | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */ 216 0x1c0 (PIN_INPUT | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */ 217 0x1c4 (PIN_INPUT | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */ 218 >; 219 220 }; 221 222 cpsw_sleep: cpsw_sleep { 223 pinctrl-single,pins = < 224 /* Slave 1 */ 225 0x250 (MUX_MODE15) 226 0x254 (MUX_MODE15) 227 0x258 (MUX_MODE15) 228 0x25c (MUX_MODE15) 229 0x260 (MUX_MODE15) 230 0x264 (MUX_MODE15) 231 0x268 (MUX_MODE15) 232 0x26c (MUX_MODE15) 233 0x270 (MUX_MODE15) 234 0x274 (MUX_MODE15) 235 0x278 (MUX_MODE15) 236 0x27c (MUX_MODE15) 237 238 /* Slave 2 */ 239 0x198 (MUX_MODE15) 240 0x19c (MUX_MODE15) 241 0x1a0 (MUX_MODE15) 242 0x1a4 (MUX_MODE15) 243 0x1a8 (MUX_MODE15) 244 0x1ac (MUX_MODE15) 245 0x1b0 (MUX_MODE15) 246 0x1b4 (MUX_MODE15) 247 0x1b8 (MUX_MODE15) 248 0x1bc (MUX_MODE15) 249 0x1c0 (MUX_MODE15) 250 0x1c4 (MUX_MODE15) 251 >; 252 }; 253 254 davinci_mdio_default: davinci_mdio_default { 255 pinctrl-single,pins = < 256 0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_d.mdio_d */ 257 0x240 (PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ 258 >; 259 }; 260 261 davinci_mdio_sleep: davinci_mdio_sleep { 262 pinctrl-single,pins = < 263 0x23c (MUX_MODE15) 264 0x240 (MUX_MODE15) 265 >; 266 }; 267 268 dcan1_pins_default: dcan1_pins_default { 269 pinctrl-single,pins = < 270 0x3d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */ 271 0x418 (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */ 272 >; 273 }; 274 275 dcan1_pins_sleep: dcan1_pins_sleep { 276 pinctrl-single,pins = < 277 0x3d0 (MUX_MODE15 | PULL_UP) /* dcan1_tx.off */ 278 0x418 (MUX_MODE15 | PULL_UP) /* wakeup0.off */ 279 >; 280 }; 281}; 282 283&i2c1 { 284 status = "okay"; 285 pinctrl-names = "default"; 286 pinctrl-0 = <&i2c1_pins>; 287 clock-frequency = <400000>; 288 289 tps659038: tps659038@58 { 290 compatible = "ti,tps659038"; 291 reg = <0x58>; 292 293 tps659038_pmic { 294 compatible = "ti,tps659038-pmic"; 295 296 regulators { 297 smps123_reg: smps123 { 298 /* VDD_MPU */ 299 regulator-name = "smps123"; 300 regulator-min-microvolt = < 850000>; 301 regulator-max-microvolt = <1250000>; 302 regulator-always-on; 303 regulator-boot-on; 304 }; 305 306 smps45_reg: smps45 { 307 /* VDD_DSPEVE */ 308 regulator-name = "smps45"; 309 regulator-min-microvolt = < 850000>; 310 regulator-max-microvolt = <1150000>; 311 regulator-always-on; 312 regulator-boot-on; 313 }; 314 315 smps6_reg: smps6 { 316 /* VDD_GPU - over VDD_SMPS6 */ 317 regulator-name = "smps6"; 318 regulator-min-microvolt = <850000>; 319 regulator-max-microvolt = <1250000>; 320 regulator-always-on; 321 regulator-boot-on; 322 }; 323 324 smps7_reg: smps7 { 325 /* CORE_VDD */ 326 regulator-name = "smps7"; 327 regulator-min-microvolt = <850000>; 328 regulator-max-microvolt = <1060000>; 329 regulator-always-on; 330 regulator-boot-on; 331 }; 332 333 smps8_reg: smps8 { 334 /* VDD_IVAHD */ 335 regulator-name = "smps8"; 336 regulator-min-microvolt = < 850000>; 337 regulator-max-microvolt = <1250000>; 338 regulator-always-on; 339 regulator-boot-on; 340 }; 341 342 smps9_reg: smps9 { 343 /* VDDS1V8 */ 344 regulator-name = "smps9"; 345 regulator-min-microvolt = <1800000>; 346 regulator-max-microvolt = <1800000>; 347 regulator-always-on; 348 regulator-boot-on; 349 }; 350 351 ldo1_reg: ldo1 { 352 /* LDO1_OUT --> SDIO */ 353 regulator-name = "ldo1"; 354 regulator-min-microvolt = <1800000>; 355 regulator-max-microvolt = <3300000>; 356 regulator-boot-on; 357 }; 358 359 ldo2_reg: ldo2 { 360 /* VDD_RTCIO */ 361 /* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */ 362 regulator-name = "ldo2"; 363 regulator-min-microvolt = <3300000>; 364 regulator-max-microvolt = <3300000>; 365 regulator-always-on; 366 regulator-boot-on; 367 }; 368 369 ldo3_reg: ldo3 { 370 /* VDDA_1V8_PHY */ 371 regulator-name = "ldo3"; 372 regulator-min-microvolt = <1800000>; 373 regulator-max-microvolt = <1800000>; 374 regulator-always-on; 375 regulator-boot-on; 376 }; 377 378 ldo9_reg: ldo9 { 379 /* VDD_RTC */ 380 regulator-name = "ldo9"; 381 regulator-min-microvolt = <1050000>; 382 regulator-max-microvolt = <1050000>; 383 regulator-always-on; 384 regulator-boot-on; 385 }; 386 387 ldoln_reg: ldoln { 388 /* VDDA_1V8_PLL */ 389 regulator-name = "ldoln"; 390 regulator-min-microvolt = <1800000>; 391 regulator-max-microvolt = <1800000>; 392 regulator-always-on; 393 regulator-boot-on; 394 }; 395 396 ldousb_reg: ldousb { 397 /* VDDA_3V_USB: VDDA_USBHS33 */ 398 regulator-name = "ldousb"; 399 regulator-min-microvolt = <3300000>; 400 regulator-max-microvolt = <3300000>; 401 regulator-boot-on; 402 }; 403 }; 404 }; 405 }; 406 407 pcf_gpio_21: gpio@21 { 408 compatible = "ti,pcf8575"; 409 reg = <0x21>; 410 lines-initial-states = <0x1408>; 411 gpio-controller; 412 #gpio-cells = <2>; 413 interrupt-parent = <&gpio6>; 414 interrupts = <11 IRQ_TYPE_EDGE_FALLING>; 415 interrupt-controller; 416 #interrupt-cells = <2>; 417 }; 418 419}; 420 421&i2c2 { 422 status = "okay"; 423 pinctrl-names = "default"; 424 pinctrl-0 = <&i2c2_pins>; 425 clock-frequency = <400000>; 426}; 427 428&i2c3 { 429 status = "okay"; 430 pinctrl-names = "default"; 431 pinctrl-0 = <&i2c3_pins>; 432 clock-frequency = <400000>; 433}; 434 435&mcspi1 { 436 status = "okay"; 437 pinctrl-names = "default"; 438 pinctrl-0 = <&mcspi1_pins>; 439}; 440 441&mcspi2 { 442 status = "okay"; 443 pinctrl-names = "default"; 444 pinctrl-0 = <&mcspi2_pins>; 445}; 446 447&uart1 { 448 status = "okay"; 449 pinctrl-names = "default"; 450 pinctrl-0 = <&uart1_pins>; 451 interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 452 <&dra7_pmx_core 0x3e0>; 453}; 454 455&uart2 { 456 status = "okay"; 457 pinctrl-names = "default"; 458 pinctrl-0 = <&uart2_pins>; 459}; 460 461&uart3 { 462 status = "okay"; 463 pinctrl-names = "default"; 464 pinctrl-0 = <&uart3_pins>; 465}; 466 467&mmc1 { 468 status = "okay"; 469 vmmc-supply = <&ldo1_reg>; 470 bus-width = <4>; 471}; 472 473&mmc2 { 474 status = "okay"; 475 vmmc-supply = <&mmc2_3v3>; 476 bus-width = <8>; 477}; 478 479&cpu0 { 480 cpu0-supply = <&smps123_reg>; 481}; 482 483&qspi { 484 status = "okay"; 485 pinctrl-names = "default"; 486 pinctrl-0 = <&qspi1_pins>; 487 488 spi-max-frequency = <48000000>; 489 m25p80@0 { 490 compatible = "s25fl256s1"; 491 spi-max-frequency = <48000000>; 492 reg = <0>; 493 spi-tx-bus-width = <1>; 494 spi-rx-bus-width = <4>; 495 spi-cpol; 496 spi-cpha; 497 #address-cells = <1>; 498 #size-cells = <1>; 499 500 /* MTD partition table. 501 * The ROM checks the first four physical blocks 502 * for a valid file to boot and the flash here is 503 * 64KiB block size. 504 */ 505 partition@0 { 506 label = "QSPI.SPL"; 507 reg = <0x00000000 0x000010000>; 508 }; 509 partition@1 { 510 label = "QSPI.SPL.backup1"; 511 reg = <0x00010000 0x00010000>; 512 }; 513 partition@2 { 514 label = "QSPI.SPL.backup2"; 515 reg = <0x00020000 0x00010000>; 516 }; 517 partition@3 { 518 label = "QSPI.SPL.backup3"; 519 reg = <0x00030000 0x00010000>; 520 }; 521 partition@4 { 522 label = "QSPI.u-boot"; 523 reg = <0x00040000 0x00100000>; 524 }; 525 partition@5 { 526 label = "QSPI.u-boot-spl-os"; 527 reg = <0x00140000 0x00080000>; 528 }; 529 partition@6 { 530 label = "QSPI.u-boot-env"; 531 reg = <0x001c0000 0x00010000>; 532 }; 533 partition@7 { 534 label = "QSPI.u-boot-env.backup1"; 535 reg = <0x001d0000 0x0010000>; 536 }; 537 partition@8 { 538 label = "QSPI.kernel"; 539 reg = <0x001e0000 0x0800000>; 540 }; 541 partition@9 { 542 label = "QSPI.file-system"; 543 reg = <0x009e0000 0x01620000>; 544 }; 545 }; 546}; 547 548&omap_dwc3_1 { 549 extcon = <&extcon_usb1>; 550}; 551 552&omap_dwc3_2 { 553 extcon = <&extcon_usb2>; 554}; 555 556&usb1 { 557 dr_mode = "peripheral"; 558 pinctrl-names = "default"; 559 pinctrl-0 = <&usb1_pins>; 560}; 561 562&usb2 { 563 dr_mode = "host"; 564 pinctrl-names = "default"; 565 pinctrl-0 = <&usb2_pins>; 566}; 567 568&elm { 569 status = "okay"; 570}; 571 572&gpmc { 573 status = "okay"; 574 pinctrl-names = "default"; 575 pinctrl-0 = <&nand_flash_x16>; 576 ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */ 577 nand@0,0 { 578 reg = <0 0 4>; /* device IO registers */ 579 ti,nand-ecc-opt = "bch8"; 580 ti,elm-id = <&elm>; 581 nand-bus-width = <16>; 582 gpmc,device-width = <2>; 583 gpmc,sync-clk-ps = <0>; 584 gpmc,cs-on-ns = <0>; 585 gpmc,cs-rd-off-ns = <80>; 586 gpmc,cs-wr-off-ns = <80>; 587 gpmc,adv-on-ns = <0>; 588 gpmc,adv-rd-off-ns = <60>; 589 gpmc,adv-wr-off-ns = <60>; 590 gpmc,we-on-ns = <10>; 591 gpmc,we-off-ns = <50>; 592 gpmc,oe-on-ns = <4>; 593 gpmc,oe-off-ns = <40>; 594 gpmc,access-ns = <40>; 595 gpmc,wr-access-ns = <80>; 596 gpmc,rd-cycle-ns = <80>; 597 gpmc,wr-cycle-ns = <80>; 598 gpmc,bus-turnaround-ns = <0>; 599 gpmc,cycle2cycle-delay-ns = <0>; 600 gpmc,clk-activation-ns = <0>; 601 gpmc,wait-monitoring-ns = <0>; 602 gpmc,wr-data-mux-bus-ns = <0>; 603 /* MTD partition table */ 604 /* All SPL-* partitions are sized to minimal length 605 * which can be independently programmable. For 606 * NAND flash this is equal to size of erase-block */ 607 #address-cells = <1>; 608 #size-cells = <1>; 609 partition@0 { 610 label = "NAND.SPL"; 611 reg = <0x00000000 0x000020000>; 612 }; 613 partition@1 { 614 label = "NAND.SPL.backup1"; 615 reg = <0x00020000 0x00020000>; 616 }; 617 partition@2 { 618 label = "NAND.SPL.backup2"; 619 reg = <0x00040000 0x00020000>; 620 }; 621 partition@3 { 622 label = "NAND.SPL.backup3"; 623 reg = <0x00060000 0x00020000>; 624 }; 625 partition@4 { 626 label = "NAND.u-boot-spl-os"; 627 reg = <0x00080000 0x00040000>; 628 }; 629 partition@5 { 630 label = "NAND.u-boot"; 631 reg = <0x000c0000 0x00100000>; 632 }; 633 partition@6 { 634 label = "NAND.u-boot-env"; 635 reg = <0x001c0000 0x00020000>; 636 }; 637 partition@7 { 638 label = "NAND.u-boot-env.backup1"; 639 reg = <0x001e0000 0x00020000>; 640 }; 641 partition@8 { 642 label = "NAND.kernel"; 643 reg = <0x00200000 0x00800000>; 644 }; 645 partition@9 { 646 label = "NAND.file-system"; 647 reg = <0x00a00000 0x0f600000>; 648 }; 649 }; 650}; 651 652&usb2_phy1 { 653 phy-supply = <&ldousb_reg>; 654}; 655 656&usb2_phy2 { 657 phy-supply = <&ldousb_reg>; 658}; 659 660&gpio7 { 661 ti,no-reset-on-init; 662 ti,no-idle-on-init; 663}; 664 665&mac { 666 status = "okay"; 667 pinctrl-names = "default", "sleep"; 668 pinctrl-0 = <&cpsw_default>; 669 pinctrl-1 = <&cpsw_sleep>; 670 dual_emac; 671}; 672 673&cpsw_emac0 { 674 phy_id = <&davinci_mdio>, <2>; 675 phy-mode = "rgmii"; 676 dual_emac_res_vlan = <1>; 677}; 678 679&cpsw_emac1 { 680 phy_id = <&davinci_mdio>, <3>; 681 phy-mode = "rgmii"; 682 dual_emac_res_vlan = <2>; 683}; 684 685&davinci_mdio { 686 pinctrl-names = "default", "sleep"; 687 pinctrl-0 = <&davinci_mdio_default>; 688 pinctrl-1 = <&davinci_mdio_sleep>; 689}; 690 691&dcan1 { 692 status = "ok"; 693 pinctrl-names = "default", "sleep", "active"; 694 pinctrl-0 = <&dcan1_pins_sleep>; 695 pinctrl-1 = <&dcan1_pins_sleep>; 696 pinctrl-2 = <&dcan1_pins_default>; 697}; 698