1/* 2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8/dts-v1/; 9 10#include "dra74x.dtsi" 11#include <dt-bindings/gpio/gpio.h> 12 13/ { 14 model = "TI DRA742"; 15 compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7"; 16 17 memory { 18 device_type = "memory"; 19 reg = <0x80000000 0x60000000>; /* 1536 MB */ 20 }; 21 22 mmc2_3v3: fixedregulator-mmc2 { 23 compatible = "regulator-fixed"; 24 regulator-name = "mmc2_3v3"; 25 regulator-min-microvolt = <3300000>; 26 regulator-max-microvolt = <3300000>; 27 }; 28 29 extcon_usb1: extcon_usb1 { 30 compatible = "linux,extcon-usb-gpio"; 31 id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>; 32 }; 33 34 extcon_usb2: extcon_usb2 { 35 compatible = "linux,extcon-usb-gpio"; 36 id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>; 37 }; 38 39 vtt_fixed: fixedregulator-vtt { 40 compatible = "regulator-fixed"; 41 regulator-name = "vtt_fixed"; 42 regulator-min-microvolt = <1350000>; 43 regulator-max-microvolt = <1350000>; 44 regulator-always-on; 45 regulator-boot-on; 46 enable-active-high; 47 gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>; 48 }; 49}; 50 51&dra7_pmx_core { 52 pinctrl-names = "default"; 53 pinctrl-0 = <&vtt_pin>; 54 55 vtt_pin: pinmux_vtt_pin { 56 pinctrl-single,pins = < 57 0x3b4 (PIN_OUTPUT | MUX_MODE14) /* spi1_cs1.gpio7_11 */ 58 >; 59 }; 60 61 i2c1_pins: pinmux_i2c1_pins { 62 pinctrl-single,pins = < 63 0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda */ 64 0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl */ 65 >; 66 }; 67 68 i2c2_pins: pinmux_i2c2_pins { 69 pinctrl-single,pins = < 70 0x408 (PIN_INPUT | MUX_MODE0) /* i2c2_sda */ 71 0x40c (PIN_INPUT | MUX_MODE0) /* i2c2_scl */ 72 >; 73 }; 74 75 i2c3_pins: pinmux_i2c3_pins { 76 pinctrl-single,pins = < 77 0x288 (PIN_INPUT | MUX_MODE9) /* gpio6_14.i2c3_sda */ 78 0x28c (PIN_INPUT | MUX_MODE9) /* gpio6_15.i2c3_scl */ 79 >; 80 }; 81 82 mcspi1_pins: pinmux_mcspi1_pins { 83 pinctrl-single,pins = < 84 0x3a4 (PIN_INPUT | MUX_MODE0) /* spi1_sclk */ 85 0x3a8 (PIN_INPUT | MUX_MODE0) /* spi1_d1 */ 86 0x3ac (PIN_INPUT | MUX_MODE0) /* spi1_d0 */ 87 0x3b0 (PIN_INPUT_SLEW | MUX_MODE0) /* spi1_cs0 */ 88 0x3b8 (PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs2.hdmi1_hpd */ 89 0x3bc (PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs3.hdmi1_cec */ 90 >; 91 }; 92 93 mcspi2_pins: pinmux_mcspi2_pins { 94 pinctrl-single,pins = < 95 0x3c0 (PIN_INPUT | MUX_MODE0) /* spi2_sclk */ 96 0x3c4 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */ 97 0x3c8 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */ 98 0x3cc (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs0 */ 99 >; 100 }; 101 102 uart1_pins: pinmux_uart1_pins { 103 pinctrl-single,pins = < 104 0x3e0 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_rxd */ 105 0x3e4 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_txd */ 106 0x3e8 (PIN_INPUT | MUX_MODE3) /* uart1_ctsn */ 107 0x3ec (PIN_INPUT | MUX_MODE3) /* uart1_rtsn */ 108 >; 109 }; 110 111 uart2_pins: pinmux_uart2_pins { 112 pinctrl-single,pins = < 113 0x3f0 (PIN_INPUT | MUX_MODE0) /* uart2_rxd */ 114 0x3f4 (PIN_INPUT | MUX_MODE0) /* uart2_txd */ 115 0x3f8 (PIN_INPUT | MUX_MODE0) /* uart2_ctsn */ 116 0x3fc (PIN_INPUT | MUX_MODE0) /* uart2_rtsn */ 117 >; 118 }; 119 120 uart3_pins: pinmux_uart3_pins { 121 pinctrl-single,pins = < 122 0x248 (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd */ 123 0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */ 124 >; 125 }; 126 127 qspi1_pins: pinmux_qspi1_pins { 128 pinctrl-single,pins = < 129 0x4c (PIN_INPUT | MUX_MODE1) /* gpmc_a3.qspi1_cs2 */ 130 0x50 (PIN_INPUT | MUX_MODE1) /* gpmc_a4.qspi1_cs3 */ 131 0x74 (PIN_INPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */ 132 0x78 (PIN_INPUT | MUX_MODE1) /* gpmc_a14.qspi1_d3 */ 133 0x7c (PIN_INPUT | MUX_MODE1) /* gpmc_a15.qspi1_d2 */ 134 0x80 (PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */ 135 0x84 (PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d0 */ 136 0x88 (PIN_INPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */ 137 0xb8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs2.qspi1_cs0 */ 138 0xbc (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs3.qspi1_cs1 */ 139 >; 140 }; 141 142 usb1_pins: pinmux_usb1_pins { 143 pinctrl-single,pins = < 144 0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */ 145 >; 146 }; 147 148 usb2_pins: pinmux_usb2_pins { 149 pinctrl-single,pins = < 150 0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */ 151 >; 152 }; 153 154 nand_flash_x16: nand_flash_x16 { 155 /* On DRA7 EVM, GPMC_WPN and NAND_BOOTn comes from DIP switch 156 * So NAND flash requires following switch settings: 157 * SW5.9 (GPMC_WPN) = LOW 158 * SW5.1 (NAND_BOOTn) = HIGH */ 159 pinctrl-single,pins = < 160 0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */ 161 0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */ 162 0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */ 163 0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */ 164 0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */ 165 0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */ 166 0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */ 167 0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */ 168 0x20 (PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */ 169 0x24 (PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */ 170 0x28 (PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */ 171 0x2c (PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */ 172 0x30 (PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */ 173 0x34 (PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */ 174 0x38 (PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */ 175 0x3c (PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */ 176 0xd8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0 */ 177 0xcc (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */ 178 0xb4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn0 */ 179 0xc4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */ 180 0xc8 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */ 181 0xd0 (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle */ 182 >; 183 }; 184 185 cpsw_default: cpsw_default { 186 pinctrl-single,pins = < 187 /* Slave 1 */ 188 0x250 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txc.rgmii0_txc */ 189 0x254 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txctl.rgmii0_txctl */ 190 0x258 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_td3.rgmii0_txd3 */ 191 0x25c (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd2.rgmii0_txd2 */ 192 0x260 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd1.rgmii0_txd1 */ 193 0x264 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd0.rgmii0_txd0 */ 194 0x268 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxc.rgmii0_rxc */ 195 0x26c (PIN_INPUT | MUX_MODE0) /* rgmii0_rxctl.rgmii0_rxctl */ 196 0x270 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd3.rgmii0_rxd3 */ 197 0x274 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd2.rgmii0_rxd2 */ 198 0x278 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd1.rgmii0_rxd1 */ 199 0x27c (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd0.rgmii0_rxd0 */ 200 201 /* Slave 2 */ 202 0x198 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_txc */ 203 0x19c (PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */ 204 0x1a0 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */ 205 0x1a4 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */ 206 0x1a8 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */ 207 0x1ac (PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */ 208 0x1b0 (PIN_INPUT | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */ 209 0x1b4 (PIN_INPUT | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */ 210 0x1b8 (PIN_INPUT | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */ 211 0x1bc (PIN_INPUT | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */ 212 0x1c0 (PIN_INPUT | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */ 213 0x1c4 (PIN_INPUT | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */ 214 >; 215 216 }; 217 218 cpsw_sleep: cpsw_sleep { 219 pinctrl-single,pins = < 220 /* Slave 1 */ 221 0x250 (MUX_MODE15) 222 0x254 (MUX_MODE15) 223 0x258 (MUX_MODE15) 224 0x25c (MUX_MODE15) 225 0x260 (MUX_MODE15) 226 0x264 (MUX_MODE15) 227 0x268 (MUX_MODE15) 228 0x26c (MUX_MODE15) 229 0x270 (MUX_MODE15) 230 0x274 (MUX_MODE15) 231 0x278 (MUX_MODE15) 232 0x27c (MUX_MODE15) 233 234 /* Slave 2 */ 235 0x198 (MUX_MODE15) 236 0x19c (MUX_MODE15) 237 0x1a0 (MUX_MODE15) 238 0x1a4 (MUX_MODE15) 239 0x1a8 (MUX_MODE15) 240 0x1ac (MUX_MODE15) 241 0x1b0 (MUX_MODE15) 242 0x1b4 (MUX_MODE15) 243 0x1b8 (MUX_MODE15) 244 0x1bc (MUX_MODE15) 245 0x1c0 (MUX_MODE15) 246 0x1c4 (MUX_MODE15) 247 >; 248 }; 249 250 davinci_mdio_default: davinci_mdio_default { 251 pinctrl-single,pins = < 252 0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_d.mdio_d */ 253 0x240 (PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ 254 >; 255 }; 256 257 davinci_mdio_sleep: davinci_mdio_sleep { 258 pinctrl-single,pins = < 259 0x23c (MUX_MODE15) 260 0x240 (MUX_MODE15) 261 >; 262 }; 263 264 dcan1_pins_default: dcan1_pins_default { 265 pinctrl-single,pins = < 266 0x3d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */ 267 0x418 (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */ 268 >; 269 }; 270 271 dcan1_pins_sleep: dcan1_pins_sleep { 272 pinctrl-single,pins = < 273 0x3d0 (MUX_MODE15 | PULL_UP) /* dcan1_tx.off */ 274 0x418 (MUX_MODE15 | PULL_UP) /* wakeup0.off */ 275 >; 276 }; 277}; 278 279&i2c1 { 280 status = "okay"; 281 pinctrl-names = "default"; 282 pinctrl-0 = <&i2c1_pins>; 283 clock-frequency = <400000>; 284 285 tps659038: tps659038@58 { 286 compatible = "ti,tps659038"; 287 reg = <0x58>; 288 289 tps659038_pmic { 290 compatible = "ti,tps659038-pmic"; 291 292 regulators { 293 smps123_reg: smps123 { 294 /* VDD_MPU */ 295 regulator-name = "smps123"; 296 regulator-min-microvolt = < 850000>; 297 regulator-max-microvolt = <1250000>; 298 regulator-always-on; 299 regulator-boot-on; 300 }; 301 302 smps45_reg: smps45 { 303 /* VDD_DSPEVE */ 304 regulator-name = "smps45"; 305 regulator-min-microvolt = < 850000>; 306 regulator-max-microvolt = <1150000>; 307 regulator-always-on; 308 regulator-boot-on; 309 }; 310 311 smps6_reg: smps6 { 312 /* VDD_GPU - over VDD_SMPS6 */ 313 regulator-name = "smps6"; 314 regulator-min-microvolt = <850000>; 315 regulator-max-microvolt = <1250000>; 316 regulator-always-on; 317 regulator-boot-on; 318 }; 319 320 smps7_reg: smps7 { 321 /* CORE_VDD */ 322 regulator-name = "smps7"; 323 regulator-min-microvolt = <850000>; 324 regulator-max-microvolt = <1060000>; 325 regulator-always-on; 326 regulator-boot-on; 327 }; 328 329 smps8_reg: smps8 { 330 /* VDD_IVAHD */ 331 regulator-name = "smps8"; 332 regulator-min-microvolt = < 850000>; 333 regulator-max-microvolt = <1250000>; 334 regulator-always-on; 335 regulator-boot-on; 336 }; 337 338 smps9_reg: smps9 { 339 /* VDDS1V8 */ 340 regulator-name = "smps9"; 341 regulator-min-microvolt = <1800000>; 342 regulator-max-microvolt = <1800000>; 343 regulator-always-on; 344 regulator-boot-on; 345 }; 346 347 ldo1_reg: ldo1 { 348 /* LDO1_OUT --> SDIO */ 349 regulator-name = "ldo1"; 350 regulator-min-microvolt = <1800000>; 351 regulator-max-microvolt = <3300000>; 352 regulator-boot-on; 353 }; 354 355 ldo2_reg: ldo2 { 356 /* VDD_RTCIO */ 357 /* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */ 358 regulator-name = "ldo2"; 359 regulator-min-microvolt = <3300000>; 360 regulator-max-microvolt = <3300000>; 361 regulator-always-on; 362 regulator-boot-on; 363 }; 364 365 ldo3_reg: ldo3 { 366 /* VDDA_1V8_PHY */ 367 regulator-name = "ldo3"; 368 regulator-min-microvolt = <1800000>; 369 regulator-max-microvolt = <1800000>; 370 regulator-always-on; 371 regulator-boot-on; 372 }; 373 374 ldo9_reg: ldo9 { 375 /* VDD_RTC */ 376 regulator-name = "ldo9"; 377 regulator-min-microvolt = <1050000>; 378 regulator-max-microvolt = <1050000>; 379 regulator-always-on; 380 regulator-boot-on; 381 }; 382 383 ldoln_reg: ldoln { 384 /* VDDA_1V8_PLL */ 385 regulator-name = "ldoln"; 386 regulator-min-microvolt = <1800000>; 387 regulator-max-microvolt = <1800000>; 388 regulator-always-on; 389 regulator-boot-on; 390 }; 391 392 ldousb_reg: ldousb { 393 /* VDDA_3V_USB: VDDA_USBHS33 */ 394 regulator-name = "ldousb"; 395 regulator-min-microvolt = <3300000>; 396 regulator-max-microvolt = <3300000>; 397 regulator-boot-on; 398 }; 399 }; 400 }; 401 }; 402 403 pcf_gpio_21: gpio@21 { 404 compatible = "ti,pcf8575"; 405 reg = <0x21>; 406 lines-initial-states = <0x1408>; 407 gpio-controller; 408 #gpio-cells = <2>; 409 interrupt-parent = <&gpio6>; 410 interrupts = <11 IRQ_TYPE_EDGE_FALLING>; 411 interrupt-controller; 412 #interrupt-cells = <2>; 413 }; 414 415}; 416 417&i2c2 { 418 status = "okay"; 419 pinctrl-names = "default"; 420 pinctrl-0 = <&i2c2_pins>; 421 clock-frequency = <400000>; 422}; 423 424&i2c3 { 425 status = "okay"; 426 pinctrl-names = "default"; 427 pinctrl-0 = <&i2c3_pins>; 428 clock-frequency = <400000>; 429}; 430 431&mcspi1 { 432 status = "okay"; 433 pinctrl-names = "default"; 434 pinctrl-0 = <&mcspi1_pins>; 435}; 436 437&mcspi2 { 438 status = "okay"; 439 pinctrl-names = "default"; 440 pinctrl-0 = <&mcspi2_pins>; 441}; 442 443&uart1 { 444 status = "okay"; 445 pinctrl-names = "default"; 446 pinctrl-0 = <&uart1_pins>; 447 interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 448 <&dra7_pmx_core 0x3e0>; 449}; 450 451&uart2 { 452 status = "okay"; 453 pinctrl-names = "default"; 454 pinctrl-0 = <&uart2_pins>; 455}; 456 457&uart3 { 458 status = "okay"; 459 pinctrl-names = "default"; 460 pinctrl-0 = <&uart3_pins>; 461}; 462 463&mmc1 { 464 status = "okay"; 465 vmmc-supply = <&ldo1_reg>; 466 bus-width = <4>; 467}; 468 469&mmc2 { 470 status = "okay"; 471 vmmc-supply = <&mmc2_3v3>; 472 bus-width = <8>; 473}; 474 475&cpu0 { 476 cpu0-supply = <&smps123_reg>; 477}; 478 479&qspi { 480 status = "okay"; 481 pinctrl-names = "default"; 482 pinctrl-0 = <&qspi1_pins>; 483 484 spi-max-frequency = <48000000>; 485 m25p80@0 { 486 compatible = "s25fl256s1"; 487 spi-max-frequency = <48000000>; 488 reg = <0>; 489 spi-tx-bus-width = <1>; 490 spi-rx-bus-width = <4>; 491 spi-cpol; 492 spi-cpha; 493 #address-cells = <1>; 494 #size-cells = <1>; 495 496 /* MTD partition table. 497 * The ROM checks the first four physical blocks 498 * for a valid file to boot and the flash here is 499 * 64KiB block size. 500 */ 501 partition@0 { 502 label = "QSPI.SPL"; 503 reg = <0x00000000 0x000010000>; 504 }; 505 partition@1 { 506 label = "QSPI.SPL.backup1"; 507 reg = <0x00010000 0x00010000>; 508 }; 509 partition@2 { 510 label = "QSPI.SPL.backup2"; 511 reg = <0x00020000 0x00010000>; 512 }; 513 partition@3 { 514 label = "QSPI.SPL.backup3"; 515 reg = <0x00030000 0x00010000>; 516 }; 517 partition@4 { 518 label = "QSPI.u-boot"; 519 reg = <0x00040000 0x00100000>; 520 }; 521 partition@5 { 522 label = "QSPI.u-boot-spl-os"; 523 reg = <0x00140000 0x00080000>; 524 }; 525 partition@6 { 526 label = "QSPI.u-boot-env"; 527 reg = <0x001c0000 0x00010000>; 528 }; 529 partition@7 { 530 label = "QSPI.u-boot-env.backup1"; 531 reg = <0x001d0000 0x0010000>; 532 }; 533 partition@8 { 534 label = "QSPI.kernel"; 535 reg = <0x001e0000 0x0800000>; 536 }; 537 partition@9 { 538 label = "QSPI.file-system"; 539 reg = <0x009e0000 0x01620000>; 540 }; 541 }; 542}; 543 544&omap_dwc3_1 { 545 extcon = <&extcon_usb1>; 546}; 547 548&omap_dwc3_2 { 549 extcon = <&extcon_usb2>; 550}; 551 552&usb1 { 553 dr_mode = "peripheral"; 554 pinctrl-names = "default"; 555 pinctrl-0 = <&usb1_pins>; 556}; 557 558&usb2 { 559 dr_mode = "host"; 560 pinctrl-names = "default"; 561 pinctrl-0 = <&usb2_pins>; 562}; 563 564&elm { 565 status = "okay"; 566}; 567 568&gpmc { 569 status = "okay"; 570 pinctrl-names = "default"; 571 pinctrl-0 = <&nand_flash_x16>; 572 ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */ 573 nand@0,0 { 574 reg = <0 0 4>; /* device IO registers */ 575 ti,nand-ecc-opt = "bch8"; 576 ti,elm-id = <&elm>; 577 nand-bus-width = <16>; 578 gpmc,device-width = <2>; 579 gpmc,sync-clk-ps = <0>; 580 gpmc,cs-on-ns = <0>; 581 gpmc,cs-rd-off-ns = <80>; 582 gpmc,cs-wr-off-ns = <80>; 583 gpmc,adv-on-ns = <0>; 584 gpmc,adv-rd-off-ns = <60>; 585 gpmc,adv-wr-off-ns = <60>; 586 gpmc,we-on-ns = <10>; 587 gpmc,we-off-ns = <50>; 588 gpmc,oe-on-ns = <4>; 589 gpmc,oe-off-ns = <40>; 590 gpmc,access-ns = <40>; 591 gpmc,wr-access-ns = <80>; 592 gpmc,rd-cycle-ns = <80>; 593 gpmc,wr-cycle-ns = <80>; 594 gpmc,bus-turnaround-ns = <0>; 595 gpmc,cycle2cycle-delay-ns = <0>; 596 gpmc,clk-activation-ns = <0>; 597 gpmc,wait-monitoring-ns = <0>; 598 gpmc,wr-data-mux-bus-ns = <0>; 599 /* MTD partition table */ 600 /* All SPL-* partitions are sized to minimal length 601 * which can be independently programmable. For 602 * NAND flash this is equal to size of erase-block */ 603 #address-cells = <1>; 604 #size-cells = <1>; 605 partition@0 { 606 label = "NAND.SPL"; 607 reg = <0x00000000 0x000020000>; 608 }; 609 partition@1 { 610 label = "NAND.SPL.backup1"; 611 reg = <0x00020000 0x00020000>; 612 }; 613 partition@2 { 614 label = "NAND.SPL.backup2"; 615 reg = <0x00040000 0x00020000>; 616 }; 617 partition@3 { 618 label = "NAND.SPL.backup3"; 619 reg = <0x00060000 0x00020000>; 620 }; 621 partition@4 { 622 label = "NAND.u-boot-spl-os"; 623 reg = <0x00080000 0x00040000>; 624 }; 625 partition@5 { 626 label = "NAND.u-boot"; 627 reg = <0x000c0000 0x00100000>; 628 }; 629 partition@6 { 630 label = "NAND.u-boot-env"; 631 reg = <0x001c0000 0x00020000>; 632 }; 633 partition@7 { 634 label = "NAND.u-boot-env.backup1"; 635 reg = <0x001e0000 0x00020000>; 636 }; 637 partition@8 { 638 label = "NAND.kernel"; 639 reg = <0x00200000 0x00800000>; 640 }; 641 partition@9 { 642 label = "NAND.file-system"; 643 reg = <0x00a00000 0x0f600000>; 644 }; 645 }; 646}; 647 648&usb2_phy1 { 649 phy-supply = <&ldousb_reg>; 650}; 651 652&usb2_phy2 { 653 phy-supply = <&ldousb_reg>; 654}; 655 656&gpio7 { 657 ti,no-reset-on-init; 658 ti,no-idle-on-init; 659}; 660 661&mac { 662 status = "okay"; 663 pinctrl-names = "default", "sleep"; 664 pinctrl-0 = <&cpsw_default>; 665 pinctrl-1 = <&cpsw_sleep>; 666 dual_emac; 667}; 668 669&cpsw_emac0 { 670 phy_id = <&davinci_mdio>, <2>; 671 phy-mode = "rgmii"; 672 dual_emac_res_vlan = <1>; 673}; 674 675&cpsw_emac1 { 676 phy_id = <&davinci_mdio>, <3>; 677 phy-mode = "rgmii"; 678 dual_emac_res_vlan = <2>; 679}; 680 681&davinci_mdio { 682 pinctrl-names = "default", "sleep"; 683 pinctrl-0 = <&davinci_mdio_default>; 684 pinctrl-1 = <&davinci_mdio_sleep>; 685}; 686 687&dcan1 { 688 status = "ok"; 689 pinctrl-names = "default", "sleep", "active"; 690 pinctrl-0 = <&dcan1_pins_sleep>; 691 pinctrl-1 = <&dcan1_pins_sleep>; 692 pinctrl-2 = <&dcan1_pins_default>; 693}; 694