1*708ca4daSTom Rini/* 2*708ca4daSTom Rini * This program is free software; you can redistribute it and/or modify 3*708ca4daSTom Rini * it under the terms of the GNU General Public License version 2 as 4*708ca4daSTom Rini * published by the Free Software Foundation. 5*708ca4daSTom Rini */ 6*708ca4daSTom Rini 7*708ca4daSTom Rini&scrm { 8*708ca4daSTom Rini main_fapll: main_fapll { 9*708ca4daSTom Rini #clock-cells = <1>; 10*708ca4daSTom Rini compatible = "ti,dm816-fapll-clock"; 11*708ca4daSTom Rini reg = <0x400 0x40>; 12*708ca4daSTom Rini clocks = <&sys_clkin_ck &sys_clkin_ck>; 13*708ca4daSTom Rini clock-indices = <1>, <2>, <3>, <4>, <5>, 14*708ca4daSTom Rini <6>, <7>; 15*708ca4daSTom Rini clock-output-names = "main_pll_clk1", 16*708ca4daSTom Rini "main_pll_clk2", 17*708ca4daSTom Rini "main_pll_clk3", 18*708ca4daSTom Rini "main_pll_clk4", 19*708ca4daSTom Rini "main_pll_clk5", 20*708ca4daSTom Rini "main_pll_clk6", 21*708ca4daSTom Rini "main_pll_clk7"; 22*708ca4daSTom Rini }; 23*708ca4daSTom Rini 24*708ca4daSTom Rini ddr_fapll: ddr_fapll { 25*708ca4daSTom Rini #clock-cells = <1>; 26*708ca4daSTom Rini compatible = "ti,dm816-fapll-clock"; 27*708ca4daSTom Rini reg = <0x440 0x30>; 28*708ca4daSTom Rini clocks = <&sys_clkin_ck &sys_clkin_ck>; 29*708ca4daSTom Rini clock-indices = <1>, <2>, <3>, <4>; 30*708ca4daSTom Rini clock-output-names = "ddr_pll_clk1", 31*708ca4daSTom Rini "ddr_pll_clk2", 32*708ca4daSTom Rini "ddr_pll_clk3", 33*708ca4daSTom Rini "ddr_pll_clk4"; 34*708ca4daSTom Rini }; 35*708ca4daSTom Rini 36*708ca4daSTom Rini video_fapll: video_fapll { 37*708ca4daSTom Rini #clock-cells = <1>; 38*708ca4daSTom Rini compatible = "ti,dm816-fapll-clock"; 39*708ca4daSTom Rini reg = <0x470 0x30>; 40*708ca4daSTom Rini clocks = <&sys_clkin_ck &sys_clkin_ck>; 41*708ca4daSTom Rini clock-indices = <1>, <2>, <3>; 42*708ca4daSTom Rini clock-output-names = "video_pll_clk1", 43*708ca4daSTom Rini "video_pll_clk2", 44*708ca4daSTom Rini "video_pll_clk3"; 45*708ca4daSTom Rini }; 46*708ca4daSTom Rini 47*708ca4daSTom Rini audio_fapll: audio_fapll { 48*708ca4daSTom Rini #clock-cells = <1>; 49*708ca4daSTom Rini compatible = "ti,dm816-fapll-clock"; 50*708ca4daSTom Rini reg = <0x4a0 0x30>; 51*708ca4daSTom Rini clocks = <&main_fapll 7>, < &sys_clkin_ck>; 52*708ca4daSTom Rini clock-indices = <1>, <2>, <3>, <4>, <5>; 53*708ca4daSTom Rini clock-output-names = "audio_pll_clk1", 54*708ca4daSTom Rini "audio_pll_clk2", 55*708ca4daSTom Rini "audio_pll_clk3", 56*708ca4daSTom Rini "audio_pll_clk4", 57*708ca4daSTom Rini "audio_pll_clk5"; 58*708ca4daSTom Rini }; 59*708ca4daSTom Rini}; 60*708ca4daSTom Rini 61*708ca4daSTom Rini&scrm_clocks { 62*708ca4daSTom Rini secure_32k_ck: secure_32k_ck { 63*708ca4daSTom Rini #clock-cells = <0>; 64*708ca4daSTom Rini compatible = "fixed-clock"; 65*708ca4daSTom Rini clock-frequency = <32768>; 66*708ca4daSTom Rini }; 67*708ca4daSTom Rini 68*708ca4daSTom Rini sys_32k_ck: sys_32k_ck { 69*708ca4daSTom Rini #clock-cells = <0>; 70*708ca4daSTom Rini compatible = "fixed-clock"; 71*708ca4daSTom Rini clock-frequency = <32768>; 72*708ca4daSTom Rini }; 73*708ca4daSTom Rini 74*708ca4daSTom Rini tclkin_ck: tclkin_ck { 75*708ca4daSTom Rini #clock-cells = <0>; 76*708ca4daSTom Rini compatible = "fixed-clock"; 77*708ca4daSTom Rini clock-frequency = <32768>; 78*708ca4daSTom Rini }; 79*708ca4daSTom Rini 80*708ca4daSTom Rini sys_clkin_ck: sys_clkin_ck { 81*708ca4daSTom Rini #clock-cells = <0>; 82*708ca4daSTom Rini compatible = "fixed-clock"; 83*708ca4daSTom Rini clock-frequency = <27000000>; 84*708ca4daSTom Rini }; 85*708ca4daSTom Rini}; 86*708ca4daSTom Rini 87*708ca4daSTom Rini/* 0x48180000 */ 88*708ca4daSTom Rini&prcm_clocks { 89*708ca4daSTom Rini clkout_pre_ck: clkout_pre_ck@100 { 90*708ca4daSTom Rini #clock-cells = <0>; 91*708ca4daSTom Rini compatible = "ti,mux-clock"; 92*708ca4daSTom Rini clocks = <&main_fapll 5 &ddr_fapll 1 &video_fapll 1 93*708ca4daSTom Rini &audio_fapll 1>; 94*708ca4daSTom Rini reg = <0x100>; 95*708ca4daSTom Rini }; 96*708ca4daSTom Rini 97*708ca4daSTom Rini clkout_div_ck: clkout_div_ck@100 { 98*708ca4daSTom Rini #clock-cells = <0>; 99*708ca4daSTom Rini compatible = "ti,divider-clock"; 100*708ca4daSTom Rini clocks = <&clkout_pre_ck>; 101*708ca4daSTom Rini ti,bit-shift = <3>; 102*708ca4daSTom Rini ti,max-div = <8>; 103*708ca4daSTom Rini reg = <0x100>; 104*708ca4daSTom Rini }; 105*708ca4daSTom Rini 106*708ca4daSTom Rini clkout_ck: clkout_ck@100 { 107*708ca4daSTom Rini #clock-cells = <0>; 108*708ca4daSTom Rini compatible = "ti,gate-clock"; 109*708ca4daSTom Rini clocks = <&clkout_div_ck>; 110*708ca4daSTom Rini ti,bit-shift = <7>; 111*708ca4daSTom Rini reg = <0x100>; 112*708ca4daSTom Rini }; 113*708ca4daSTom Rini 114*708ca4daSTom Rini /* CM_DPLL clocks p1795 */ 115*708ca4daSTom Rini sysclk1_ck: sysclk1_ck@300 { 116*708ca4daSTom Rini #clock-cells = <0>; 117*708ca4daSTom Rini compatible = "ti,divider-clock"; 118*708ca4daSTom Rini clocks = <&main_fapll 1>; 119*708ca4daSTom Rini ti,max-div = <7>; 120*708ca4daSTom Rini reg = <0x0300>; 121*708ca4daSTom Rini }; 122*708ca4daSTom Rini 123*708ca4daSTom Rini sysclk2_ck: sysclk2_ck@304 { 124*708ca4daSTom Rini #clock-cells = <0>; 125*708ca4daSTom Rini compatible = "ti,divider-clock"; 126*708ca4daSTom Rini clocks = <&main_fapll 2>; 127*708ca4daSTom Rini ti,max-div = <7>; 128*708ca4daSTom Rini reg = <0x0304>; 129*708ca4daSTom Rini }; 130*708ca4daSTom Rini 131*708ca4daSTom Rini sysclk3_ck: sysclk3_ck@308 { 132*708ca4daSTom Rini #clock-cells = <0>; 133*708ca4daSTom Rini compatible = "ti,divider-clock"; 134*708ca4daSTom Rini clocks = <&main_fapll 3>; 135*708ca4daSTom Rini ti,max-div = <7>; 136*708ca4daSTom Rini reg = <0x0308>; 137*708ca4daSTom Rini }; 138*708ca4daSTom Rini 139*708ca4daSTom Rini sysclk4_ck: sysclk4_ck@30c { 140*708ca4daSTom Rini #clock-cells = <0>; 141*708ca4daSTom Rini compatible = "ti,divider-clock"; 142*708ca4daSTom Rini clocks = <&main_fapll 4>; 143*708ca4daSTom Rini ti,max-div = <1>; 144*708ca4daSTom Rini reg = <0x030c>; 145*708ca4daSTom Rini }; 146*708ca4daSTom Rini 147*708ca4daSTom Rini sysclk5_ck: sysclk5_ck@310 { 148*708ca4daSTom Rini #clock-cells = <0>; 149*708ca4daSTom Rini compatible = "ti,divider-clock"; 150*708ca4daSTom Rini clocks = <&sysclk4_ck>; 151*708ca4daSTom Rini ti,max-div = <1>; 152*708ca4daSTom Rini reg = <0x0310>; 153*708ca4daSTom Rini }; 154*708ca4daSTom Rini 155*708ca4daSTom Rini sysclk6_ck: sysclk6_ck@314 { 156*708ca4daSTom Rini #clock-cells = <0>; 157*708ca4daSTom Rini compatible = "ti,divider-clock"; 158*708ca4daSTom Rini clocks = <&main_fapll 4>; 159*708ca4daSTom Rini ti,dividers = <2>, <4>; 160*708ca4daSTom Rini reg = <0x0314>; 161*708ca4daSTom Rini }; 162*708ca4daSTom Rini 163*708ca4daSTom Rini sysclk10_ck: sysclk10_ck@324 { 164*708ca4daSTom Rini #clock-cells = <0>; 165*708ca4daSTom Rini compatible = "ti,divider-clock"; 166*708ca4daSTom Rini clocks = <&ddr_fapll 2>; 167*708ca4daSTom Rini ti,max-div = <7>; 168*708ca4daSTom Rini reg = <0x0324>; 169*708ca4daSTom Rini }; 170*708ca4daSTom Rini 171*708ca4daSTom Rini sysclk24_ck: sysclk24_ck@3b4 { 172*708ca4daSTom Rini #clock-cells = <0>; 173*708ca4daSTom Rini compatible = "ti,divider-clock"; 174*708ca4daSTom Rini clocks = <&main_fapll 5>; 175*708ca4daSTom Rini ti,max-div = <7>; 176*708ca4daSTom Rini reg = <0x03b4>; 177*708ca4daSTom Rini }; 178*708ca4daSTom Rini 179*708ca4daSTom Rini mpu_ck: mpu_ck@15dc { 180*708ca4daSTom Rini #clock-cells = <0>; 181*708ca4daSTom Rini compatible = "ti,gate-clock"; 182*708ca4daSTom Rini clocks = <&sysclk2_ck>; 183*708ca4daSTom Rini ti,bit-shift = <1>; 184*708ca4daSTom Rini reg = <0x15dc>; 185*708ca4daSTom Rini }; 186*708ca4daSTom Rini 187*708ca4daSTom Rini audio_pll_a_ck: audio_pll_a_ck@35c { 188*708ca4daSTom Rini #clock-cells = <0>; 189*708ca4daSTom Rini compatible = "ti,divider-clock"; 190*708ca4daSTom Rini clocks = <&audio_fapll 1>; 191*708ca4daSTom Rini ti,max-div = <7>; 192*708ca4daSTom Rini reg = <0x035c>; 193*708ca4daSTom Rini }; 194*708ca4daSTom Rini 195*708ca4daSTom Rini sysclk18_ck: sysclk18_ck@378 { 196*708ca4daSTom Rini #clock-cells = <0>; 197*708ca4daSTom Rini compatible = "ti,mux-clock"; 198*708ca4daSTom Rini clocks = <&sys_32k_ck>, <&audio_pll_a_ck>; 199*708ca4daSTom Rini reg = <0x0378>; 200*708ca4daSTom Rini }; 201*708ca4daSTom Rini 202*708ca4daSTom Rini timer1_fck: timer1_fck@390 { 203*708ca4daSTom Rini #clock-cells = <0>; 204*708ca4daSTom Rini compatible = "ti,mux-clock"; 205*708ca4daSTom Rini clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>; 206*708ca4daSTom Rini reg = <0x0390>; 207*708ca4daSTom Rini }; 208*708ca4daSTom Rini 209*708ca4daSTom Rini timer2_fck: timer2_fck@394 { 210*708ca4daSTom Rini #clock-cells = <0>; 211*708ca4daSTom Rini compatible = "ti,mux-clock"; 212*708ca4daSTom Rini clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>; 213*708ca4daSTom Rini reg = <0x0394>; 214*708ca4daSTom Rini }; 215*708ca4daSTom Rini 216*708ca4daSTom Rini timer3_fck: timer3_fck@398 { 217*708ca4daSTom Rini #clock-cells = <0>; 218*708ca4daSTom Rini compatible = "ti,mux-clock"; 219*708ca4daSTom Rini clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>; 220*708ca4daSTom Rini reg = <0x0398>; 221*708ca4daSTom Rini }; 222*708ca4daSTom Rini 223*708ca4daSTom Rini timer4_fck: timer4_fck@39c { 224*708ca4daSTom Rini #clock-cells = <0>; 225*708ca4daSTom Rini compatible = "ti,mux-clock"; 226*708ca4daSTom Rini clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>; 227*708ca4daSTom Rini reg = <0x039c>; 228*708ca4daSTom Rini }; 229*708ca4daSTom Rini 230*708ca4daSTom Rini timer5_fck: timer5_fck@3a0 { 231*708ca4daSTom Rini #clock-cells = <0>; 232*708ca4daSTom Rini compatible = "ti,mux-clock"; 233*708ca4daSTom Rini clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>; 234*708ca4daSTom Rini reg = <0x03a0>; 235*708ca4daSTom Rini }; 236*708ca4daSTom Rini 237*708ca4daSTom Rini timer6_fck: timer6_fck@3a4 { 238*708ca4daSTom Rini #clock-cells = <0>; 239*708ca4daSTom Rini compatible = "ti,mux-clock"; 240*708ca4daSTom Rini clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>; 241*708ca4daSTom Rini reg = <0x03a4>; 242*708ca4daSTom Rini }; 243*708ca4daSTom Rini 244*708ca4daSTom Rini timer7_fck: timer7_fck@3a8 { 245*708ca4daSTom Rini #clock-cells = <0>; 246*708ca4daSTom Rini compatible = "ti,mux-clock"; 247*708ca4daSTom Rini clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>; 248*708ca4daSTom Rini reg = <0x03a8>; 249*708ca4daSTom Rini }; 250*708ca4daSTom Rini}; 251