1/* 2 * Copyright (c) 2016 BayLibre, Inc. 3 * 4 * Licensed under GPLv2. 5 */ 6/dts-v1/; 7#include "da850.dtsi" 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/input/input.h> 10 11/ { 12 model = "DA850/AM1808/OMAP-L138 LCDK"; 13 compatible = "ti,da850-lcdk", "ti,da850"; 14 15 aliases { 16 serial2 = &serial2; 17 ethernet0 = ð0; 18 }; 19 20 chosen { 21 stdout-path = "serial2:115200n8"; 22 }; 23 24 memory { 25 device_type = "memory"; 26 reg = <0xc0000000 0x08000000>; 27 }; 28 29 reserved-memory { 30 #address-cells = <1>; 31 #size-cells = <1>; 32 ranges; 33 34 dsp_memory_region: dsp-memory@c3000000 { 35 compatible = "shared-dma-pool"; 36 reg = <0xc3000000 0x1000000>; 37 reusable; 38 status = "okay"; 39 }; 40 }; 41 42 sound { 43 compatible = "simple-audio-card"; 44 simple-audio-card,name = "DA850/OMAP-L138 LCDK"; 45 simple-audio-card,widgets = 46 "Line", "Line In", 47 "Line", "Line Out"; 48 simple-audio-card,routing = 49 "LINE1L", "Line In", 50 "LINE1R", "Line In", 51 "Line Out", "LLOUT", 52 "Line Out", "RLOUT"; 53 simple-audio-card,format = "dsp_b"; 54 simple-audio-card,bitclock-master = <&link0_codec>; 55 simple-audio-card,frame-master = <&link0_codec>; 56 simple-audio-card,bitclock-inversion; 57 58 simple-audio-card,cpu { 59 sound-dai = <&mcasp0>; 60 system-clock-frequency = <24576000>; 61 }; 62 63 link0_codec: simple-audio-card,codec { 64 sound-dai = <&tlv320aic3106>; 65 system-clock-frequency = <24576000>; 66 }; 67 }; 68 69 gpio-keys { 70 compatible = "gpio-keys"; 71 autorepeat; 72 73 user1 { 74 label = "GPIO Key USER1"; 75 linux,code = <BTN_0>; 76 gpios = <&gpio 36 GPIO_ACTIVE_LOW>; 77 }; 78 79 user2 { 80 label = "GPIO Key USER2"; 81 linux,code = <BTN_1>; 82 gpios = <&gpio 37 GPIO_ACTIVE_LOW>; 83 }; 84 }; 85 86 vga-bridge { 87 compatible = "ti,ths8135"; 88 #address-cells = <1>; 89 #size-cells = <0>; 90 91 ports { 92 #address-cells = <1>; 93 #size-cells = <0>; 94 95 port@0 { 96 reg = <0>; 97 98 vga_bridge_in: endpoint { 99 remote-endpoint = <&lcdc_out_vga>; 100 }; 101 }; 102 103 port@1 { 104 reg = <1>; 105 106 vga_bridge_out: endpoint { 107 remote-endpoint = <&vga_con_in>; 108 }; 109 }; 110 }; 111 }; 112 113 vga { 114 compatible = "vga-connector"; 115 116 ddc-i2c-bus = <&i2c0>; 117 118 port { 119 vga_con_in: endpoint { 120 remote-endpoint = <&vga_bridge_out>; 121 }; 122 }; 123 }; 124}; 125 126&pmx_core { 127 status = "okay"; 128 129 mcasp0_pins: pinmux_mcasp0_pins { 130 pinctrl-single,bits = < 131 /* AHCLKX AFSX ACLKX */ 132 0x00 0x00101010 0x00f0f0f0 133 /* ARX13 ARX14 */ 134 0x04 0x00000110 0x00000ff0 135 >; 136 }; 137 138 nand_pins: nand_pins { 139 pinctrl-single,bits = < 140 /* EMA_WAIT[0], EMA_OE, EMA_WE, EMA_CS[3] */ 141 0x1c 0x10110010 0xf0ff00f0 142 /* 143 * EMA_D[0], EMA_D[1], EMA_D[2], 144 * EMA_D[3], EMA_D[4], EMA_D[5], 145 * EMA_D[6], EMA_D[7] 146 */ 147 0x24 0x11111111 0xffffffff 148 /* 149 * EMA_D[8], EMA_D[9], EMA_D[10], 150 * EMA_D[11], EMA_D[12], EMA_D[13], 151 * EMA_D[14], EMA_D[15] 152 */ 153 0x20 0x11111111 0xffffffff 154 /* EMA_A[1], EMA_A[2] */ 155 0x30 0x01100000 0x0ff00000 156 >; 157 }; 158}; 159 160&serial2 { 161 pinctrl-names = "default"; 162 pinctrl-0 = <&serial2_rxtx_pins>; 163 status = "okay"; 164}; 165 166&wdt { 167 status = "okay"; 168}; 169 170&rtc0 { 171 status = "okay"; 172}; 173 174&gpio { 175 status = "okay"; 176}; 177 178&sata { 179 status = "okay"; 180}; 181 182&mdio { 183 pinctrl-names = "default"; 184 pinctrl-0 = <&mdio_pins>; 185 bus_freq = <2200000>; 186 status = "okay"; 187}; 188 189ð0 { 190 pinctrl-names = "default"; 191 pinctrl-0 = <&mii_pins>; 192 status = "okay"; 193}; 194 195&mmc0 { 196 max-frequency = <50000000>; 197 bus-width = <4>; 198 pinctrl-names = "default"; 199 pinctrl-0 = <&mmc0_pins>; 200 cd-gpios = <&gpio 64 GPIO_ACTIVE_LOW>; 201 status = "okay"; 202}; 203 204&i2c0 { 205 pinctrl-names = "default"; 206 pinctrl-0 = <&i2c0_pins>; 207 clock-frequency = <100000>; 208 status = "okay"; 209 210 tlv320aic3106: tlv320aic3106@18 { 211 #sound-dai-cells = <0>; 212 compatible = "ti,tlv320aic3106"; 213 reg = <0x18>; 214 status = "okay"; 215 }; 216}; 217 218&mcasp0 { 219 #sound-dai-cells = <0>; 220 pinctrl-names = "default"; 221 pinctrl-0 = <&mcasp0_pins>; 222 status = "okay"; 223 224 op-mode = <0>; /* DAVINCI_MCASP_IIS_MODE */ 225 tdm-slots = <2>; 226 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ 227 0 0 0 0 228 0 0 0 0 229 0 0 0 0 230 0 1 2 0 231 >; 232 tx-num-evt = <32>; 233 rx-num-evt = <32>; 234}; 235 236&usb_phy { 237 status = "okay"; 238}; 239 240&usb0 { 241 status = "okay"; 242}; 243 244&usb1 { 245 status = "okay"; 246}; 247 248&aemif { 249 pinctrl-names = "default"; 250 pinctrl-0 = <&nand_pins>; 251 status = "okay"; 252 cs3 { 253 #address-cells = <2>; 254 #size-cells = <1>; 255 clock-ranges; 256 ranges; 257 258 ti,cs-chipselect = <3>; 259 260 nand@2000000,0 { 261 compatible = "ti,davinci-nand"; 262 #address-cells = <1>; 263 #size-cells = <1>; 264 reg = <0 0x02000000 0x02000000 265 1 0x00000000 0x00008000>; 266 267 ti,davinci-chipselect = <1>; 268 ti,davinci-mask-ale = <0>; 269 ti,davinci-mask-cle = <0>; 270 ti,davinci-mask-chipsel = <0>; 271 272 ti,davinci-nand-buswidth = <16>; 273 ti,davinci-ecc-mode = "hw"; 274 ti,davinci-ecc-bits = <4>; 275 ti,davinci-nand-use-bbt; 276 277 /* 278 * The OMAP-L132/L138 Bootloader doc SPRAB41E reads: 279 * "To boot from NAND Flash, the AIS should be written 280 * to NAND block 1 (NAND block 0 is not used by default)". 281 * The same doc mentions that for ROM "Silicon Revision 2.1", 282 * "Updated NAND boot mode to offer boot from block 0 or block 1". 283 * However the limitaion is left here by default for compatibility 284 * with older silicon and because it needs new boot pin settings 285 * not possible in stock LCDK. 286 */ 287 partitions { 288 compatible = "fixed-partitions"; 289 #address-cells = <1>; 290 #size-cells = <1>; 291 292 partition@0 { 293 label = "u-boot env"; 294 reg = <0 0x020000>; 295 }; 296 partition@20000 { 297 /* The LCDK defaults to booting from this partition */ 298 label = "u-boot"; 299 reg = <0x020000 0x080000>; 300 }; 301 partition@a0000 { 302 label = "free space"; 303 reg = <0x0a0000 0>; 304 }; 305 }; 306 }; 307 }; 308}; 309 310&prictrl { 311 status = "okay"; 312}; 313 314&memctrl { 315 status = "okay"; 316}; 317 318&lcdc { 319 status = "okay"; 320 pinctrl-names = "default"; 321 pinctrl-0 = <&lcd_pins>; 322 323 port { 324 lcdc_out_vga: endpoint { 325 remote-endpoint = <&vga_bridge_in>; 326 }; 327 }; 328}; 329 330&vpif { 331 pinctrl-names = "default"; 332 pinctrl-0 = <&vpif_capture_pins>; 333 status = "okay"; 334}; 335 336&dsp { 337 memory-region = <&dsp_memory_region>; 338 status = "okay"; 339}; 340