xref: /openbmc/u-boot/arch/arm/dts/bcm2836.dtsi (revision 274bced8)
1#include "bcm283x.dtsi"
2
3/ {
4	compatible = "brcm,bcm2836";
5
6	soc {
7		ranges = <0x7e000000 0x3f000000 0x1000000>,
8			 <0x40000000 0x40000000 0x00001000>;
9		dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
10
11		local_intc: local_intc {
12			compatible = "brcm,bcm2836-l1-intc";
13			reg = <0x40000000 0x100>;
14			interrupt-controller;
15			#interrupt-cells = <1>;
16			interrupt-parent = <&local_intc>;
17		};
18
19		arm-pmu {
20			compatible = "arm,cortex-a7-pmu";
21			interrupt-parent = <&local_intc>;
22			interrupts = <9>;
23		};
24	};
25
26	timer {
27		compatible = "arm,armv7-timer";
28		interrupt-parent = <&local_intc>;
29		interrupts = <0>, // PHYS_SECURE_PPI
30			     <1>, // PHYS_NONSECURE_PPI
31			     <3>, // VIRT_PPI
32			     <2>; // HYP_PPI
33		always-on;
34	};
35
36	cpus: cpus {
37		#address-cells = <1>;
38		#size-cells = <0>;
39
40		v7_cpu0: cpu@0 {
41			device_type = "cpu";
42			compatible = "arm,cortex-a7";
43			reg = <0xf00>;
44			clock-frequency = <800000000>;
45		};
46
47		v7_cpu1: cpu@1 {
48			device_type = "cpu";
49			compatible = "arm,cortex-a7";
50			reg = <0xf01>;
51			clock-frequency = <800000000>;
52		};
53
54		v7_cpu2: cpu@2 {
55			device_type = "cpu";
56			compatible = "arm,cortex-a7";
57			reg = <0xf02>;
58			clock-frequency = <800000000>;
59		};
60
61		v7_cpu3: cpu@3 {
62			device_type = "cpu";
63			compatible = "arm,cortex-a7";
64			reg = <0xf03>;
65			clock-frequency = <800000000>;
66		};
67	};
68};
69
70/* Make the BCM2835-style global interrupt controller be a child of the
71 * CPU-local interrupt controller.
72 */
73&intc {
74	compatible = "brcm,bcm2836-armctrl-ic";
75	reg = <0x7e00b200 0x200>;
76	interrupt-parent = <&local_intc>;
77	interrupts = <8>;
78};
79