xref: /openbmc/u-boot/arch/arm/dts/at91sam9x5.dtsi (revision dd4671cb)
1/*
2 * at91sam9x5.dtsi - Device Tree Include file for AT91SAM9x5 family SoC
3 *                   applies to AT91SAM9G15, AT91SAM9G25, AT91SAM9G35,
4 *                   AT91SAM9X25, AT91SAM9X35 SoC
5 *
6 *  Copyright (C) 2012 Atmel,
7 *                2012 Nicolas Ferre <nicolas.ferre@atmel.com>
8 *
9 * Licensed under GPLv2 or later.
10 */
11
12#include "skeleton.dtsi"
13#include <dt-bindings/dma/at91.h>
14#include <dt-bindings/pinctrl/at91.h>
15#include <dt-bindings/interrupt-controller/irq.h>
16#include <dt-bindings/gpio/gpio.h>
17#include <dt-bindings/clock/at91.h>
18
19/ {
20	model = "Atmel AT91SAM9x5 family SoC";
21	compatible = "atmel,at91sam9x5";
22	interrupt-parent = <&aic>;
23
24	aliases {
25		serial0 = &dbgu;
26		serial1 = &usart0;
27		serial2 = &usart1;
28		serial3 = &usart2;
29		gpio0 = &pioA;
30		gpio1 = &pioB;
31		gpio2 = &pioC;
32		gpio3 = &pioD;
33		tcb0 = &tcb0;
34		tcb1 = &tcb1;
35		i2c0 = &i2c0;
36		i2c1 = &i2c1;
37		i2c2 = &i2c2;
38		ssc0 = &ssc0;
39		pwm0 = &pwm0;
40		spi0 = &spi0;
41	};
42
43	cpus {
44		#address-cells = <0>;
45		#size-cells = <0>;
46
47		cpu {
48			compatible = "arm,arm926ej-s";
49			device_type = "cpu";
50		};
51	};
52
53	memory {
54		reg = <0x20000000 0x10000000>;
55	};
56
57	clocks {
58		slow_xtal: slow_xtal {
59			compatible = "fixed-clock";
60			#clock-cells = <0>;
61			clock-frequency = <0>;
62		};
63
64		main_xtal: main_xtal {
65			compatible = "fixed-clock";
66			#clock-cells = <0>;
67			clock-frequency = <0>;
68		};
69
70		adc_op_clk: adc_op_clk{
71			compatible = "fixed-clock";
72			#clock-cells = <0>;
73			clock-frequency = <1000000>;
74		};
75	};
76
77	sram: sram@00300000 {
78		compatible = "mmio-sram";
79		reg = <0x00300000 0x8000>;
80	};
81
82	ahb {
83		compatible = "simple-bus";
84		#address-cells = <1>;
85		#size-cells = <1>;
86		ranges;
87		u-boot,dm-pre-reloc;
88
89		apb {
90			compatible = "simple-bus";
91			#address-cells = <1>;
92			#size-cells = <1>;
93			ranges;
94			u-boot,dm-pre-reloc;
95
96			aic: interrupt-controller@fffff000 {
97				#interrupt-cells = <3>;
98				compatible = "atmel,at91rm9200-aic";
99				interrupt-controller;
100				reg = <0xfffff000 0x200>;
101				atmel,external-irqs = <31>;
102			};
103
104			ramc0: ramc@ffffe800 {
105				compatible = "atmel,at91sam9g45-ddramc";
106				reg = <0xffffe800 0x200>;
107				clocks = <&ddrck>;
108				clock-names = "ddrck";
109			};
110
111			pmc: pmc@fffffc00 {
112				compatible = "atmel,at91sam9x5-pmc", "syscon";
113				reg = <0xfffffc00 0x200>;
114				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
115				interrupt-controller;
116				#address-cells = <1>;
117				#size-cells = <0>;
118				#interrupt-cells = <1>;
119				u-boot,dm-pre-reloc;
120
121				main_rc_osc: main_rc_osc {
122					compatible = "atmel,at91sam9x5-clk-main-rc-osc";
123					#clock-cells = <0>;
124					interrupts-extended = <&pmc AT91_PMC_MOSCRCS>;
125					clock-frequency = <12000000>;
126					clock-accuracy = <50000000>;
127				};
128
129				main_osc: main_osc {
130					compatible = "atmel,at91rm9200-clk-main-osc";
131					#clock-cells = <0>;
132					interrupts-extended = <&pmc AT91_PMC_MOSCS>;
133					clocks = <&main_xtal>;
134				};
135
136				main: mainck {
137					compatible = "atmel,at91sam9x5-clk-main";
138					#clock-cells = <0>;
139					interrupts-extended = <&pmc AT91_PMC_MOSCSELS>;
140					clocks = <&main_rc_osc>, <&main_osc>;
141				};
142
143				plla: pllack@0 {
144					compatible = "atmel,at91rm9200-clk-pll";
145					#clock-cells = <0>;
146					interrupts-extended = <&pmc AT91_PMC_LOCKA>;
147					clocks = <&main>;
148					reg = <0>;
149					atmel,clk-input-range = <2000000 32000000>;
150					#atmel,pll-clk-output-range-cells = <4>;
151					atmel,pll-clk-output-ranges = <745000000 800000000 0 0
152								       695000000 750000000 1 0
153								       645000000 700000000 2 0
154								       595000000 650000000 3 0
155								       545000000 600000000 0 1
156								       495000000 555000000 1 1
157								       445000000 500000000 2 1
158								       400000000 450000000 3 1>;
159				};
160
161				plladiv: plladivck {
162					compatible = "atmel,at91sam9x5-clk-plldiv";
163					#clock-cells = <0>;
164					clocks = <&plla>;
165				};
166
167				utmi: utmick {
168					compatible = "atmel,at91sam9x5-clk-utmi";
169					#clock-cells = <0>;
170					interrupts-extended = <&pmc AT91_PMC_LOCKU>;
171					clocks = <&main>;
172				};
173
174				mck: masterck {
175					compatible = "atmel,at91sam9x5-clk-master";
176					#clock-cells = <0>;
177					interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
178					clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
179					atmel,clk-output-range = <0 133333333>;
180					atmel,clk-divisors = <1 2 4 3>;
181					atmel,master-clk-have-div3-pres;
182					u-boot,dm-pre-reloc;
183
184				};
185
186				usb: usbck {
187					compatible = "atmel,at91sam9x5-clk-usb";
188					#clock-cells = <0>;
189					clocks = <&plladiv>, <&utmi>;
190				};
191
192				prog: progck {
193					compatible = "atmel,at91sam9x5-clk-programmable";
194					#address-cells = <1>;
195					#size-cells = <0>;
196					interrupt-parent = <&pmc>;
197					clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
198
199					prog0: prog@0 {
200						#clock-cells = <0>;
201						reg = <0>;
202						interrupts = <AT91_PMC_PCKRDY(0)>;
203					};
204
205					prog1: prog@1 {
206						#clock-cells = <0>;
207						reg = <1>;
208						interrupts = <AT91_PMC_PCKRDY(1)>;
209					};
210				};
211
212				smd: smdclk {
213					compatible = "atmel,at91sam9x5-clk-smd";
214					#clock-cells = <0>;
215					clocks = <&plladiv>, <&utmi>;
216				};
217
218				systemck {
219					compatible = "atmel,at91rm9200-clk-system";
220					#address-cells = <1>;
221					#size-cells = <0>;
222
223					ddrck: ddrck@2 {
224						#clock-cells = <0>;
225						reg = <2>;
226						clocks = <&mck>;
227					};
228
229					smdck: smdck@4 {
230						#clock-cells = <0>;
231						reg = <4>;
232						clocks = <&smd>;
233					};
234
235					uhpck: uhpck@6 {
236						#clock-cells = <0>;
237						reg = <6>;
238						clocks = <&usb>;
239					};
240
241					udpck: udpck@7 {
242						#clock-cells = <0>;
243						reg = <7>;
244						clocks = <&usb>;
245					};
246
247					pck0: pck0@8 {
248						#clock-cells = <0>;
249						reg = <8>;
250						clocks = <&prog0>;
251					};
252
253					pck1: pck1@9 {
254						#clock-cells = <0>;
255						reg = <9>;
256						clocks = <&prog1>;
257					};
258				};
259
260				periphck {
261					compatible = "atmel,at91sam9x5-clk-peripheral";
262					#address-cells = <1>;
263					#size-cells = <0>;
264					clocks = <&mck>;
265					u-boot,dm-pre-reloc;
266
267
268					pioAB_clk: pioAB_clk@2 {
269						#clock-cells = <0>;
270						reg = <2>;
271					};
272
273					pioCD_clk: pioCD_clk@3 {
274						#clock-cells = <0>;
275						reg = <3>;
276					};
277
278					smd_clk: smd_clk@4 {
279						#clock-cells = <0>;
280						reg = <4>;
281					};
282
283					usart0_clk: usart0_clk@5 {
284						#clock-cells = <0>;
285						reg = <5>;
286					};
287
288					usart1_clk: usart1_clk@6 {
289						#clock-cells = <0>;
290						reg = <6>;
291					};
292
293					usart2_clk: usart2_clk@7 {
294						#clock-cells = <0>;
295						reg = <7>;
296					};
297
298					twi0_clk: twi0_clk@9 {
299						reg = <9>;
300						#clock-cells = <0>;
301					};
302
303					twi1_clk: twi1_clk@10 {
304						#clock-cells = <0>;
305						reg = <10>;
306					};
307
308					twi2_clk: twi2_clk@11 {
309						#clock-cells = <0>;
310						reg = <11>;
311					};
312
313					mci0_clk: mci0_clk@12 {
314						#clock-cells = <0>;
315						reg = <12>;
316					};
317
318					spi0_clk: spi0_clk@13 {
319						#clock-cells = <0>;
320						reg = <13>;
321					};
322
323					spi1_clk: spi1_clk@14 {
324						#clock-cells = <0>;
325						reg = <14>;
326					};
327
328					uart0_clk: uart0_clk@15 {
329						#clock-cells = <0>;
330						reg = <15>;
331					};
332
333					uart1_clk: uart1_clk@16 {
334						#clock-cells = <0>;
335						reg = <16>;
336					};
337
338					tcb0_clk: tcb0_clk@17 {
339						#clock-cells = <0>;
340						reg = <17>;
341					};
342
343					pwm_clk: pwm_clk@18 {
344						#clock-cells = <0>;
345						reg = <18>;
346					};
347
348					adc_clk: adc_clk@19 {
349						#clock-cells = <0>;
350						reg = <19>;
351					};
352
353					dma0_clk: dma0_clk@20 {
354						#clock-cells = <0>;
355						reg = <20>;
356					};
357
358					dma1_clk: dma1_clk@21 {
359						#clock-cells = <0>;
360						reg = <21>;
361					};
362
363					uhphs_clk: uhphs_clk@22 {
364						#clock-cells = <0>;
365						reg = <22>;
366					};
367
368					udphs_clk: udphs_clk@23 {
369						#clock-cells = <0>;
370						reg = <23>;
371					};
372
373					mci1_clk: mci1_clk@26 {
374						#clock-cells = <0>;
375						reg = <26>;
376					};
377
378					ssc0_clk: ssc0_clk@28 {
379						#clock-cells = <0>;
380						reg = <28>;
381					};
382				};
383			};
384
385			rstc@fffffe00 {
386				compatible = "atmel,at91sam9g45-rstc";
387				reg = <0xfffffe00 0x10>;
388				clocks = <&clk32k>;
389			};
390
391			shdwc@fffffe10 {
392				compatible = "atmel,at91sam9x5-shdwc";
393				reg = <0xfffffe10 0x10>;
394				clocks = <&clk32k>;
395			};
396
397			pit: timer@fffffe30 {
398				compatible = "atmel,at91sam9260-pit";
399				reg = <0xfffffe30 0xf>;
400				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
401				clocks = <&mck>;
402			};
403
404			sckc@fffffe50 {
405				compatible = "atmel,at91sam9x5-sckc";
406				reg = <0xfffffe50 0x4>;
407
408				slow_osc: slow_osc {
409					compatible = "atmel,at91sam9x5-clk-slow-osc";
410					#clock-cells = <0>;
411					clocks = <&slow_xtal>;
412				};
413
414				slow_rc_osc: slow_rc_osc {
415					compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
416					#clock-cells = <0>;
417					clock-frequency = <32768>;
418					clock-accuracy = <50000000>;
419				};
420
421				clk32k: slck {
422					compatible = "atmel,at91sam9x5-clk-slow";
423					#clock-cells = <0>;
424					clocks = <&slow_rc_osc>, <&slow_osc>;
425				};
426			};
427
428			tcb0: timer@f8008000 {
429				compatible = "atmel,at91sam9x5-tcb";
430				reg = <0xf8008000 0x100>;
431				interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
432				clocks = <&tcb0_clk>, <&clk32k>;
433				clock-names = "t0_clk", "slow_clk";
434			};
435
436			tcb1: timer@f800c000 {
437				compatible = "atmel,at91sam9x5-tcb";
438				reg = <0xf800c000 0x100>;
439				interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
440				clocks = <&tcb0_clk>, <&clk32k>;
441				clock-names = "t0_clk", "slow_clk";
442			};
443
444			dma0: dma-controller@ffffec00 {
445				compatible = "atmel,at91sam9g45-dma";
446				reg = <0xffffec00 0x200>;
447				interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
448				#dma-cells = <2>;
449				clocks = <&dma0_clk>;
450				clock-names = "dma_clk";
451			};
452
453			dma1: dma-controller@ffffee00 {
454				compatible = "atmel,at91sam9g45-dma";
455				reg = <0xffffee00 0x200>;
456				interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
457				#dma-cells = <2>;
458				clocks = <&dma1_clk>;
459				clock-names = "dma_clk";
460			};
461
462			pinctrl@fffff400 {
463				#address-cells = <1>;
464				#size-cells = <1>;
465				compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
466				ranges = <0xfffff400 0xfffff400 0x800>;
467				reg = <0xfffff400 0x200		/* pioA */
468				       0xfffff600 0x200		/* pioB */
469				       0xfffff800 0x200		/* pioC */
470				       0xfffffa00 0x200		/* pioD */
471				       >;
472				u-boot,dm-pre-reloc;
473
474
475				/* shared pinctrl settings */
476				dbgu {
477					u-boot,dm-pre-reloc;
478					pinctrl_dbgu: dbgu-0 {
479						atmel,pins =
480							<AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
481							 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;
482					};
483				};
484
485				usart0 {
486					pinctrl_usart0: usart0-0 {
487						atmel,pins =
488							<AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PA0 periph A with pullup */
489							 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PA1 periph A */
490					};
491
492					pinctrl_usart0_rts: usart0_rts-0 {
493						atmel,pins =
494							<AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PA2 periph A */
495					};
496
497					pinctrl_usart0_cts: usart0_cts-0 {
498						atmel,pins =
499							<AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PA3 periph A */
500					};
501
502					pinctrl_usart0_sck: usart0_sck-0 {
503						atmel,pins =
504							<AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PA4 periph A */
505					};
506				};
507
508				usart1 {
509					pinctrl_usart1: usart1-0 {
510						atmel,pins =
511							<AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PA5 periph A with pullup */
512							 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PA6 periph A */
513					};
514
515					pinctrl_usart1_rts: usart1_rts-0 {
516						atmel,pins =
517							<AT91_PIOC 27 AT91_PERIPH_C AT91_PINCTRL_NONE>;	/* PC27 periph C */
518					};
519
520					pinctrl_usart1_cts: usart1_cts-0 {
521						atmel,pins =
522							<AT91_PIOC 28 AT91_PERIPH_C AT91_PINCTRL_NONE>;	/* PC28 periph C */
523					};
524
525					pinctrl_usart1_sck: usart1_sck-0 {
526						atmel,pins =
527							<AT91_PIOC 29 AT91_PERIPH_C AT91_PINCTRL_NONE>;	/* PC29 periph C */
528					};
529				};
530
531				usart2 {
532					pinctrl_usart2: usart2-0 {
533						atmel,pins =
534							<AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PA7 periph A with pullup */
535							 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PA8 periph A */
536					};
537
538					pinctrl_usart2_rts: usart2_rts-0 {
539						atmel,pins =
540							<AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PB0 periph B */
541					};
542
543					pinctrl_usart2_cts: usart2_cts-0 {
544						atmel,pins =
545							<AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PB1 periph B */
546					};
547
548					pinctrl_usart2_sck: usart2_sck-0 {
549						atmel,pins =
550							<AT91_PIOB 2 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PB2 periph B */
551					};
552				};
553
554				uart0 {
555					pinctrl_uart0: uart0-0 {
556						atmel,pins =
557							<AT91_PIOC 8 AT91_PERIPH_C AT91_PINCTRL_NONE	/* PC8 periph C */
558							 AT91_PIOC 9 AT91_PERIPH_C AT91_PINCTRL_PULL_UP>;	/* PC9 periph C with pullup */
559					};
560				};
561
562				uart1 {
563					pinctrl_uart1: uart1-0 {
564						atmel,pins =
565							<AT91_PIOC 16 AT91_PERIPH_C AT91_PINCTRL_NONE	/* PC16 periph C */
566							 AT91_PIOC 17 AT91_PERIPH_C AT91_PINCTRL_PULL_UP>;	/* PC17 periph C with pullup */
567					};
568				};
569
570				nand {
571					pinctrl_nand: nand-0 {
572						atmel,pins =
573							<AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PD0 periph A Read Enable */
574							 AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PD1 periph A Write Enable */
575							 AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PD2 periph A Address Latch Enable */
576							 AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PD3 periph A Command Latch Enable */
577							 AT91_PIOD 4 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP	/* PD4 gpio Chip Enable pin pull_up */
578							 AT91_PIOD 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP	/* PD5 gpio RDY/BUSY pin pull_up */
579							 AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PD6 periph A Data bit 0 */
580							 AT91_PIOD 7 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PD7 periph A Data bit 1 */
581							 AT91_PIOD 8 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PD8 periph A Data bit 2 */
582							 AT91_PIOD 9 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PD9 periph A Data bit 3 */
583							 AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PD10 periph A Data bit 4 */
584							 AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PD11 periph A Data bit 5 */
585							 AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PD12 periph A Data bit 6 */
586							 AT91_PIOD 13 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PD13 periph A Data bit 7 */
587					};
588
589					pinctrl_nand_16bits: nand_16bits-0 {
590						atmel,pins =
591							<AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PD14 periph A Data bit 8 */
592							 AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PD15 periph A Data bit 9 */
593							 AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PD16 periph A Data bit 10 */
594							 AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PD17 periph A Data bit 11 */
595							 AT91_PIOD 18 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PD18 periph A Data bit 12 */
596							 AT91_PIOD 19 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PD19 periph A Data bit 13 */
597							 AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PD20 periph A Data bit 14 */
598							 AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PD21 periph A Data bit 15 */
599					};
600				};
601
602				mmc0 {
603					pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
604						atmel,pins =
605							<AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PA17 periph A */
606							 AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PA16 periph A with pullup */
607							 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;	/* PA15 periph A with pullup */
608					};
609
610					pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
611						atmel,pins =
612							<AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PA18 periph A with pullup */
613							 AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PA19 periph A with pullup */
614							 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;	/* PA20 periph A with pullup */
615					};
616				};
617
618				mmc1 {
619					pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 {
620						atmel,pins =
621							<AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PA13 periph B */
622							 AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_PULL_UP	/* PA12 periph B with pullup */
623							 AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;	/* PA11 periph B with pullup */
624					};
625
626					pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {
627						atmel,pins =
628							<AT91_PIOA 2 AT91_PERIPH_B AT91_PINCTRL_PULL_UP	/* PA2 periph B with pullup */
629							 AT91_PIOA 3 AT91_PERIPH_B AT91_PINCTRL_PULL_UP	/* PA3 periph B with pullup */
630							 AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;	/* PA4 periph B with pullup */
631					};
632				};
633
634				ssc0 {
635					pinctrl_ssc0_tx: ssc0_tx-0 {
636						atmel,pins =
637							<AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PA24 periph B */
638							 AT91_PIOA 25 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PA25 periph B */
639							 AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PA26 periph B */
640					};
641
642					pinctrl_ssc0_rx: ssc0_rx-0 {
643						atmel,pins =
644							<AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PA27 periph B */
645							 AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PA28 periph B */
646							 AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PA29 periph B */
647					};
648				};
649
650				spi0 {
651					pinctrl_spi0: spi0-0 {
652						atmel,pins =
653							<AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PA11 periph A SPI0_MISO pin */
654							 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PA12 periph A SPI0_MOSI pin */
655							 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PA13 periph A SPI0_SPCK pin */
656					};
657				};
658
659				spi1 {
660					pinctrl_spi1: spi1-0 {
661						atmel,pins =
662							<AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PA21 periph B SPI1_MISO pin */
663							 AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PA22 periph B SPI1_MOSI pin */
664							 AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PA23 periph B SPI1_SPCK pin */
665					};
666				};
667
668				i2c0 {
669					pinctrl_i2c0: i2c0-0 {
670						atmel,pins =
671							<AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PA30 periph A I2C0 data */
672							 AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PA31 periph A I2C0 clock */
673					};
674				};
675
676				i2c1 {
677					pinctrl_i2c1: i2c1-0 {
678						atmel,pins =
679							<AT91_PIOC 0 AT91_PERIPH_C AT91_PINCTRL_NONE	/* PC0 periph C I2C1 data */
680							 AT91_PIOC 1 AT91_PERIPH_C AT91_PINCTRL_NONE>;	/* PC1 periph C I2C1 clock */
681					};
682				};
683
684				i2c2 {
685					pinctrl_i2c2: i2c2-0 {
686						atmel,pins =
687							<AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PB4 periph B I2C2 data */
688							 AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PB5 periph B I2C2 clock */
689					};
690				};
691
692				i2c_gpio0 {
693					pinctrl_i2c_gpio0: i2c_gpio0-0 {
694						atmel,pins =
695							<AT91_PIOA 30 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE	/* PA30 gpio multidrive I2C0 data */
696							 AT91_PIOA 31 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>;	/* PA31 gpio multidrive I2C0 clock */
697					};
698				};
699
700				i2c_gpio1 {
701					pinctrl_i2c_gpio1: i2c_gpio1-0 {
702						atmel,pins =
703							<AT91_PIOC 0 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE	/* PC0 gpio multidrive I2C1 data */
704							 AT91_PIOC 1 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>;	/* PC1 gpio multidrive I2C1 clock */
705					};
706				};
707
708				i2c_gpio2 {
709					pinctrl_i2c_gpio2: i2c_gpio2-0 {
710						atmel,pins =
711							<AT91_PIOB 4 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE	/* PB4 gpio multidrive I2C2 data */
712							 AT91_PIOB 5 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>;	/* PB5 gpio multidrive I2C2 clock */
713					};
714				};
715
716				pwm0 {
717					pinctrl_pwm0_pwm0_0: pwm0_pwm0-0 {
718						atmel,pins =
719							<AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>;
720					};
721					pinctrl_pwm0_pwm0_1: pwm0_pwm0-1 {
722						atmel,pins =
723							<AT91_PIOC 10 AT91_PERIPH_C AT91_PINCTRL_NONE>;
724					};
725					pinctrl_pwm0_pwm0_2: pwm0_pwm0-2 {
726						atmel,pins =
727							<AT91_PIOC 18 AT91_PERIPH_C AT91_PINCTRL_NONE>;
728					};
729
730					pinctrl_pwm0_pwm1_0: pwm0_pwm1-0 {
731						atmel,pins =
732							<AT91_PIOB 12 AT91_PERIPH_B AT91_PINCTRL_NONE>;
733					};
734					pinctrl_pwm0_pwm1_1: pwm0_pwm1-1 {
735						atmel,pins =
736							<AT91_PIOC 11 AT91_PERIPH_C AT91_PINCTRL_NONE>;
737					};
738					pinctrl_pwm0_pwm1_2: pwm0_pwm1-2 {
739						atmel,pins =
740							<AT91_PIOC 19 AT91_PERIPH_C AT91_PINCTRL_NONE>;
741					};
742
743					pinctrl_pwm0_pwm2_0: pwm0_pwm2-0 {
744						atmel,pins =
745							<AT91_PIOB 13 AT91_PERIPH_B AT91_PINCTRL_NONE>;
746					};
747					pinctrl_pwm0_pwm2_1: pwm0_pwm2-1 {
748						atmel,pins =
749							<AT91_PIOC 20 AT91_PERIPH_C AT91_PINCTRL_NONE>;
750					};
751
752					pinctrl_pwm0_pwm3_0: pwm0_pwm3-0 {
753						atmel,pins =
754							<AT91_PIOB 14 AT91_PERIPH_B AT91_PINCTRL_NONE>;
755					};
756					pinctrl_pwm0_pwm3_1: pwm0_pwm3-1 {
757						atmel,pins =
758							<AT91_PIOC 21 AT91_PERIPH_C AT91_PINCTRL_NONE>;
759					};
760				};
761
762				tcb0 {
763					pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
764						atmel,pins = <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE>;
765					};
766
767					pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
768						atmel,pins = <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE>;
769					};
770
771					pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
772						atmel,pins = <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE>;
773					};
774
775					pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
776						atmel,pins = <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>;
777					};
778
779					pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
780						atmel,pins = <AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE>;
781					};
782
783					pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
784						atmel,pins = <AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;
785					};
786
787					pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
788						atmel,pins = <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
789					};
790
791					pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
792						atmel,pins = <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
793					};
794
795					pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
796						atmel,pins = <AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
797					};
798				};
799
800				tcb1 {
801					pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
802						atmel,pins = <AT91_PIOC 4 AT91_PERIPH_C AT91_PINCTRL_NONE>;
803					};
804
805					pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
806						atmel,pins = <AT91_PIOC 7 AT91_PERIPH_C AT91_PINCTRL_NONE>;
807					};
808
809					pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
810						atmel,pins = <AT91_PIOC 14 AT91_PERIPH_C AT91_PINCTRL_NONE>;
811					};
812
813					pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
814						atmel,pins = <AT91_PIOC 2 AT91_PERIPH_C AT91_PINCTRL_NONE>;
815					};
816
817					pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
818						atmel,pins = <AT91_PIOC 5 AT91_PERIPH_C AT91_PINCTRL_NONE>;
819					};
820
821					pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
822						atmel,pins = <AT91_PIOC 12 AT91_PERIPH_C AT91_PINCTRL_NONE>;
823					};
824
825					pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
826						atmel,pins = <AT91_PIOC 3 AT91_PERIPH_C AT91_PINCTRL_NONE>;
827					};
828
829					pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
830						atmel,pins = <AT91_PIOC 6 AT91_PERIPH_C AT91_PINCTRL_NONE>;
831					};
832
833					pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
834						atmel,pins = <AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE>;
835					};
836				};
837			};
838
839			pioA: gpio@fffff400 {
840				compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
841				reg = <0xfffff400 0x200>;
842				interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
843				#gpio-cells = <2>;
844				gpio-controller;
845				interrupt-controller;
846				#interrupt-cells = <2>;
847				clocks = <&pioAB_clk>;
848			};
849
850			pioB: gpio@fffff600 {
851				compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
852				reg = <0xfffff600 0x200>;
853				interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
854				#gpio-cells = <2>;
855				gpio-controller;
856				#gpio-lines = <19>;
857				interrupt-controller;
858				#interrupt-cells = <2>;
859				clocks = <&pioAB_clk>;
860			};
861
862			pioC: gpio@fffff800 {
863				compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
864				reg = <0xfffff800 0x200>;
865				interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
866				#gpio-cells = <2>;
867				gpio-controller;
868				interrupt-controller;
869				#interrupt-cells = <2>;
870				clocks = <&pioCD_clk>;
871			};
872
873			pioD: gpio@fffffa00 {
874				compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
875				reg = <0xfffffa00 0x200>;
876				interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
877				#gpio-cells = <2>;
878				gpio-controller;
879				#gpio-lines = <22>;
880				interrupt-controller;
881				#interrupt-cells = <2>;
882				clocks = <&pioCD_clk>;
883			};
884
885			ssc0: ssc@f0010000 {
886				compatible = "atmel,at91sam9g45-ssc";
887				reg = <0xf0010000 0x4000>;
888				interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>;
889				dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(13)>,
890				       <&dma0 1 AT91_DMA_CFG_PER_ID(14)>;
891				dma-names = "tx", "rx";
892				pinctrl-names = "default";
893				pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
894				clocks = <&ssc0_clk>;
895				clock-names = "pclk";
896				status = "disabled";
897			};
898
899			mmc0: mmc@f0008000 {
900				compatible = "atmel,hsmci";
901				reg = <0xf0008000 0x600>;
902				interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
903				dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(0)>;
904				dma-names = "rxtx";
905				pinctrl-names = "default";
906				clocks = <&mci0_clk>;
907				clock-names = "mci_clk";
908				#address-cells = <1>;
909				#size-cells = <0>;
910				status = "disabled";
911			};
912
913			mmc1: mmc@f000c000 {
914				compatible = "atmel,hsmci";
915				reg = <0xf000c000 0x600>;
916				interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
917				dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(0)>;
918				dma-names = "rxtx";
919				pinctrl-names = "default";
920				clocks = <&mci1_clk>;
921				clock-names = "mci_clk";
922				#address-cells = <1>;
923				#size-cells = <0>;
924				status = "disabled";
925			};
926
927			dbgu: serial@fffff200 {
928				compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
929				reg = <0xfffff200 0x200>;
930				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
931				pinctrl-names = "default";
932				pinctrl-0 = <&pinctrl_dbgu>;
933				dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(8)>,
934				       <&dma1 1 (AT91_DMA_CFG_PER_ID(9) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
935				dma-names = "tx", "rx";
936				clocks = <&mck>;
937				clock-names = "usart";
938				status = "disabled";
939			};
940
941			usart0: serial@f801c000 {
942				compatible = "atmel,at91sam9260-usart";
943				reg = <0xf801c000 0x200>;
944				interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>;
945				pinctrl-names = "default";
946				pinctrl-0 = <&pinctrl_usart0>;
947				dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(3)>,
948				       <&dma0 1 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
949				dma-names = "tx", "rx";
950				clocks = <&usart0_clk>;
951				clock-names = "usart";
952				status = "disabled";
953			};
954
955			usart1: serial@f8020000 {
956				compatible = "atmel,at91sam9260-usart";
957				reg = <0xf8020000 0x200>;
958				interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
959				pinctrl-names = "default";
960				pinctrl-0 = <&pinctrl_usart1>;
961				dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(5)>,
962				       <&dma0 1 (AT91_DMA_CFG_PER_ID(6) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
963				dma-names = "tx", "rx";
964				clocks = <&usart1_clk>;
965				clock-names = "usart";
966				status = "disabled";
967			};
968
969			usart2: serial@f8024000 {
970				compatible = "atmel,at91sam9260-usart";
971				reg = <0xf8024000 0x200>;
972				interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
973				pinctrl-names = "default";
974				pinctrl-0 = <&pinctrl_usart2>;
975				dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(12)>,
976				       <&dma1 1 (AT91_DMA_CFG_PER_ID(13) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
977				dma-names = "tx", "rx";
978				clocks = <&usart2_clk>;
979				clock-names = "usart";
980				status = "disabled";
981			};
982
983			i2c0: i2c@f8010000 {
984				compatible = "atmel,at91sam9x5-i2c";
985				reg = <0xf8010000 0x100>;
986				interrupts = <9 IRQ_TYPE_LEVEL_HIGH 6>;
987				dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(7)>,
988				       <&dma0 1 AT91_DMA_CFG_PER_ID(8)>;
989				dma-names = "tx", "rx";
990				#address-cells = <1>;
991				#size-cells = <0>;
992				pinctrl-names = "default";
993				pinctrl-0 = <&pinctrl_i2c0>;
994				clocks = <&twi0_clk>;
995				status = "disabled";
996			};
997
998			i2c1: i2c@f8014000 {
999				compatible = "atmel,at91sam9x5-i2c";
1000				reg = <0xf8014000 0x100>;
1001				interrupts = <10 IRQ_TYPE_LEVEL_HIGH 6>;
1002				dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(5)>,
1003				       <&dma1 1 AT91_DMA_CFG_PER_ID(6)>;
1004				dma-names = "tx", "rx";
1005				#address-cells = <1>;
1006				#size-cells = <0>;
1007				pinctrl-names = "default";
1008				pinctrl-0 = <&pinctrl_i2c1>;
1009				clocks = <&twi1_clk>;
1010				status = "disabled";
1011			};
1012
1013			i2c2: i2c@f8018000 {
1014				compatible = "atmel,at91sam9x5-i2c";
1015				reg = <0xf8018000 0x100>;
1016				interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>;
1017				dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(9)>,
1018				       <&dma0 1 AT91_DMA_CFG_PER_ID(10)>;
1019				dma-names = "tx", "rx";
1020				#address-cells = <1>;
1021				#size-cells = <0>;
1022				pinctrl-names = "default";
1023				pinctrl-0 = <&pinctrl_i2c2>;
1024				clocks = <&twi2_clk>;
1025				status = "disabled";
1026			};
1027
1028			uart0: serial@f8040000 {
1029				compatible = "atmel,at91sam9260-usart";
1030				reg = <0xf8040000 0x200>;
1031				interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
1032				pinctrl-names = "default";
1033				pinctrl-0 = <&pinctrl_uart0>;
1034				clocks = <&uart0_clk>;
1035				clock-names = "usart";
1036				status = "disabled";
1037			};
1038
1039			uart1: serial@f8044000 {
1040				compatible = "atmel,at91sam9260-usart";
1041				reg = <0xf8044000 0x200>;
1042				interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
1043				pinctrl-names = "default";
1044				pinctrl-0 = <&pinctrl_uart1>;
1045				clocks = <&uart1_clk>;
1046				clock-names = "usart";
1047				status = "disabled";
1048			};
1049
1050			adc0: adc@f804c000 {
1051				#address-cells = <1>;
1052				#size-cells = <0>;
1053				compatible = "atmel,at91sam9x5-adc";
1054				reg = <0xf804c000 0x100>;
1055				interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>;
1056				clocks = <&adc_clk>,
1057					 <&adc_op_clk>;
1058				clock-names = "adc_clk", "adc_op_clk";
1059				atmel,adc-use-external-triggers;
1060				atmel,adc-channels-used = <0xffff>;
1061				atmel,adc-vref = <3300>;
1062				atmel,adc-startup-time = <40>;
1063				atmel,adc-sample-hold-time = <11>;
1064				atmel,adc-res = <8 10>;
1065				atmel,adc-res-names = "lowres", "highres";
1066				atmel,adc-use-res = "highres";
1067
1068				trigger0 {
1069					trigger-name = "external-rising";
1070					trigger-value = <0x1>;
1071					trigger-external;
1072				};
1073
1074				trigger1 {
1075					trigger-name = "external-falling";
1076					trigger-value = <0x2>;
1077					trigger-external;
1078				};
1079
1080				trigger2 {
1081					trigger-name = "external-any";
1082					trigger-value = <0x3>;
1083					trigger-external;
1084				};
1085
1086				trigger3 {
1087					trigger-name = "continuous";
1088					trigger-value = <0x6>;
1089				};
1090			};
1091
1092			spi0: spi@f0000000 {
1093				#address-cells = <1>;
1094				#size-cells = <0>;
1095				compatible = "atmel,at91rm9200-spi";
1096				reg = <0xf0000000 0x100>;
1097				interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
1098				dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(1)>,
1099				       <&dma0 1 AT91_DMA_CFG_PER_ID(2)>;
1100				dma-names = "tx", "rx";
1101				pinctrl-names = "default";
1102				pinctrl-0 = <&pinctrl_spi0>;
1103				clocks = <&spi0_clk>;
1104				clock-names = "spi_clk";
1105				status = "disabled";
1106			};
1107
1108			spi1: spi@f0004000 {
1109				#address-cells = <1>;
1110				#size-cells = <0>;
1111				compatible = "atmel,at91rm9200-spi";
1112				reg = <0xf0004000 0x100>;
1113				interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>;
1114				dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(1)>,
1115				       <&dma1 1 AT91_DMA_CFG_PER_ID(2)>;
1116				dma-names = "tx", "rx";
1117				pinctrl-names = "default";
1118				pinctrl-0 = <&pinctrl_spi1>;
1119				clocks = <&spi1_clk>;
1120				clock-names = "spi_clk";
1121				status = "disabled";
1122			};
1123
1124			usb2: gadget@f803c000 {
1125				#address-cells = <1>;
1126				#size-cells = <0>;
1127				compatible = "atmel,at91sam9g45-udc";
1128				reg = <0x00500000 0x80000
1129				       0xf803c000 0x400>;
1130				interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>;
1131				clocks = <&utmi>, <&udphs_clk>;
1132				clock-names = "hclk", "pclk";
1133				status = "disabled";
1134
1135				ep@0 {
1136					reg = <0>;
1137					atmel,fifo-size = <64>;
1138					atmel,nb-banks = <1>;
1139				};
1140
1141				ep@1 {
1142					reg = <1>;
1143					atmel,fifo-size = <1024>;
1144					atmel,nb-banks = <2>;
1145					atmel,can-dma;
1146					atmel,can-isoc;
1147				};
1148
1149				ep@2 {
1150					reg = <2>;
1151					atmel,fifo-size = <1024>;
1152					atmel,nb-banks = <2>;
1153					atmel,can-dma;
1154					atmel,can-isoc;
1155				};
1156
1157				ep@3 {
1158					reg = <3>;
1159					atmel,fifo-size = <1024>;
1160					atmel,nb-banks = <3>;
1161					atmel,can-dma;
1162				};
1163
1164				ep@4 {
1165					reg = <4>;
1166					atmel,fifo-size = <1024>;
1167					atmel,nb-banks = <3>;
1168					atmel,can-dma;
1169				};
1170
1171				ep@5 {
1172					reg = <5>;
1173					atmel,fifo-size = <1024>;
1174					atmel,nb-banks = <3>;
1175					atmel,can-dma;
1176					atmel,can-isoc;
1177				};
1178
1179				ep@6 {
1180					reg = <6>;
1181					atmel,fifo-size = <1024>;
1182					atmel,nb-banks = <3>;
1183					atmel,can-dma;
1184					atmel,can-isoc;
1185				};
1186			};
1187
1188			watchdog@fffffe40 {
1189				compatible = "atmel,at91sam9260-wdt";
1190				reg = <0xfffffe40 0x10>;
1191				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
1192				clocks = <&clk32k>;
1193				atmel,watchdog-type = "hardware";
1194				atmel,reset-type = "all";
1195				atmel,dbg-halt;
1196				status = "disabled";
1197			};
1198
1199			rtc@fffffeb0 {
1200				compatible = "atmel,at91sam9x5-rtc";
1201				reg = <0xfffffeb0 0x40>;
1202				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
1203				clocks = <&clk32k>;
1204				status = "disabled";
1205			};
1206
1207			pwm0: pwm@f8034000 {
1208				compatible = "atmel,at91sam9rl-pwm";
1209				reg = <0xf8034000 0x300>;
1210				interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>;
1211				clocks = <&pwm_clk>;
1212				#pwm-cells = <3>;
1213				status = "disabled";
1214			};
1215		};
1216
1217		nand0: nand@40000000 {
1218			compatible = "atmel,at91rm9200-nand";
1219			#address-cells = <1>;
1220			#size-cells = <1>;
1221			reg = <0x40000000 0x10000000
1222			       0xffffe000 0x600		/* PMECC Registers */
1223			       0xffffe600 0x200		/* PMECC Error Location Registers */
1224			       0x00108000 0x18000	/* PMECC looup table in ROM code  */
1225			      >;
1226			atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
1227			atmel,nand-addr-offset = <21>;
1228			atmel,nand-cmd-offset = <22>;
1229			atmel,nand-has-dma;
1230			pinctrl-names = "default";
1231			pinctrl-0 = <&pinctrl_nand>;
1232			gpios = <&pioD 5 GPIO_ACTIVE_HIGH
1233				 &pioD 4 GPIO_ACTIVE_HIGH
1234				 0
1235				>;
1236			status = "disabled";
1237		};
1238
1239		usb0: ohci@00600000 {
1240			compatible = "atmel,at91rm9200-ohci", "usb-ohci";
1241			reg = <0x00600000 0x100000>;
1242			interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
1243			clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
1244			clock-names = "ohci_clk", "hclk", "uhpck";
1245			status = "disabled";
1246		};
1247
1248		usb1: ehci@00700000 {
1249			compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
1250			reg = <0x00700000 0x100000>;
1251			interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
1252			clocks = <&utmi>, <&uhphs_clk>;
1253			clock-names = "usb_clk", "ehci_clk";
1254			status = "disabled";
1255		};
1256	};
1257
1258	i2c-gpio-0 {
1259		compatible = "i2c-gpio";
1260		gpios = <&pioA 30 GPIO_ACTIVE_HIGH /* sda */
1261			 &pioA 31 GPIO_ACTIVE_HIGH /* scl */
1262			>;
1263		i2c-gpio,sda-open-drain;
1264		i2c-gpio,scl-open-drain;
1265		i2c-gpio,delay-us = <2>;	/* ~100 kHz */
1266		#address-cells = <1>;
1267		#size-cells = <0>;
1268		pinctrl-names = "default";
1269		pinctrl-0 = <&pinctrl_i2c_gpio0>;
1270		status = "disabled";
1271	};
1272
1273	i2c-gpio-1 {
1274		compatible = "i2c-gpio";
1275		gpios = <&pioC 0 GPIO_ACTIVE_HIGH /* sda */
1276			 &pioC 1 GPIO_ACTIVE_HIGH /* scl */
1277			>;
1278		i2c-gpio,sda-open-drain;
1279		i2c-gpio,scl-open-drain;
1280		i2c-gpio,delay-us = <2>;	/* ~100 kHz */
1281		#address-cells = <1>;
1282		#size-cells = <0>;
1283		pinctrl-names = "default";
1284		pinctrl-0 = <&pinctrl_i2c_gpio1>;
1285		status = "disabled";
1286	};
1287
1288	i2c-gpio-2 {
1289		compatible = "i2c-gpio";
1290		gpios = <&pioB 4 GPIO_ACTIVE_HIGH /* sda */
1291			 &pioB 5 GPIO_ACTIVE_HIGH /* scl */
1292			>;
1293		i2c-gpio,sda-open-drain;
1294		i2c-gpio,scl-open-drain;
1295		i2c-gpio,delay-us = <2>;	/* ~100 kHz */
1296		#address-cells = <1>;
1297		#size-cells = <0>;
1298		pinctrl-names = "default";
1299		pinctrl-0 = <&pinctrl_i2c_gpio2>;
1300		status = "disabled";
1301	};
1302};
1303