1/* 2 * at91sam9x5.dtsi - Device Tree Include file for AT91SAM9x5 family SoC 3 * applies to AT91SAM9G15, AT91SAM9G25, AT91SAM9G35, 4 * AT91SAM9X25, AT91SAM9X35 SoC 5 * 6 * Copyright (C) 2012 Atmel, 7 * 2012 Nicolas Ferre <nicolas.ferre@atmel.com> 8 * 9 * Licensed under GPLv2 or later. 10 */ 11 12#include "skeleton.dtsi" 13#include <dt-bindings/dma/at91.h> 14#include <dt-bindings/pinctrl/at91.h> 15#include <dt-bindings/interrupt-controller/irq.h> 16#include <dt-bindings/gpio/gpio.h> 17#include <dt-bindings/clock/at91.h> 18 19/ { 20 model = "Atmel AT91SAM9x5 family SoC"; 21 compatible = "atmel,at91sam9x5"; 22 interrupt-parent = <&aic>; 23 24 aliases { 25 serial0 = &dbgu; 26 serial1 = &usart0; 27 serial2 = &usart1; 28 serial3 = &usart2; 29 gpio0 = &pioA; 30 gpio1 = &pioB; 31 gpio2 = &pioC; 32 gpio3 = &pioD; 33 tcb0 = &tcb0; 34 tcb1 = &tcb1; 35 i2c0 = &i2c0; 36 i2c1 = &i2c1; 37 i2c2 = &i2c2; 38 ssc0 = &ssc0; 39 pwm0 = &pwm0; 40 spi0 = &spi0; 41 }; 42 43 cpus { 44 cpu { 45 compatible = "arm,arm926ej-s"; 46 device_type = "cpu"; 47 }; 48 }; 49 50 memory { 51 reg = <0x20000000 0x10000000>; 52 }; 53 54 clocks { 55 slow_xtal: slow_xtal { 56 compatible = "fixed-clock"; 57 #clock-cells = <0>; 58 clock-frequency = <0>; 59 }; 60 61 main_xtal: main_xtal { 62 compatible = "fixed-clock"; 63 #clock-cells = <0>; 64 clock-frequency = <0>; 65 }; 66 67 adc_op_clk: adc_op_clk{ 68 compatible = "fixed-clock"; 69 #clock-cells = <0>; 70 clock-frequency = <1000000>; 71 }; 72 }; 73 74 sram: sram@00300000 { 75 compatible = "mmio-sram"; 76 reg = <0x00300000 0x8000>; 77 }; 78 79 ahb { 80 compatible = "simple-bus"; 81 #address-cells = <1>; 82 #size-cells = <1>; 83 ranges; 84 u-boot,dm-pre-reloc; 85 86 apb { 87 compatible = "simple-bus"; 88 #address-cells = <1>; 89 #size-cells = <1>; 90 ranges; 91 u-boot,dm-pre-reloc; 92 93 aic: interrupt-controller@fffff000 { 94 #interrupt-cells = <3>; 95 compatible = "atmel,at91rm9200-aic"; 96 interrupt-controller; 97 reg = <0xfffff000 0x200>; 98 atmel,external-irqs = <31>; 99 }; 100 101 ramc0: ramc@ffffe800 { 102 compatible = "atmel,at91sam9g45-ddramc"; 103 reg = <0xffffe800 0x200>; 104 clocks = <&ddrck>; 105 clock-names = "ddrck"; 106 }; 107 108 pmc: pmc@fffffc00 { 109 compatible = "atmel,at91sam9x5-pmc", "syscon"; 110 reg = <0xfffffc00 0x200>; 111 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 112 interrupt-controller; 113 #address-cells = <1>; 114 #size-cells = <0>; 115 #interrupt-cells = <1>; 116 u-boot,dm-pre-reloc; 117 118 main_rc_osc: main_rc_osc { 119 compatible = "atmel,at91sam9x5-clk-main-rc-osc"; 120 #clock-cells = <0>; 121 interrupts-extended = <&pmc AT91_PMC_MOSCRCS>; 122 clock-frequency = <12000000>; 123 clock-accuracy = <50000000>; 124 }; 125 126 main_osc: main_osc { 127 compatible = "atmel,at91rm9200-clk-main-osc"; 128 #clock-cells = <0>; 129 interrupts-extended = <&pmc AT91_PMC_MOSCS>; 130 clocks = <&main_xtal>; 131 }; 132 133 main: mainck { 134 compatible = "atmel,at91sam9x5-clk-main"; 135 #clock-cells = <0>; 136 interrupts-extended = <&pmc AT91_PMC_MOSCSELS>; 137 clocks = <&main_rc_osc>, <&main_osc>; 138 }; 139 140 plla: pllack@0 { 141 compatible = "atmel,at91rm9200-clk-pll"; 142 #clock-cells = <0>; 143 interrupts-extended = <&pmc AT91_PMC_LOCKA>; 144 clocks = <&main>; 145 reg = <0>; 146 atmel,clk-input-range = <2000000 32000000>; 147 #atmel,pll-clk-output-range-cells = <4>; 148 atmel,pll-clk-output-ranges = <745000000 800000000 0 0 149 695000000 750000000 1 0 150 645000000 700000000 2 0 151 595000000 650000000 3 0 152 545000000 600000000 0 1 153 495000000 555000000 1 1 154 445000000 500000000 2 1 155 400000000 450000000 3 1>; 156 }; 157 158 plladiv: plladivck { 159 compatible = "atmel,at91sam9x5-clk-plldiv"; 160 #clock-cells = <0>; 161 clocks = <&plla>; 162 }; 163 164 utmi: utmick { 165 compatible = "atmel,at91sam9x5-clk-utmi"; 166 #clock-cells = <0>; 167 interrupts-extended = <&pmc AT91_PMC_LOCKU>; 168 clocks = <&main>; 169 }; 170 171 mck: masterck { 172 compatible = "atmel,at91sam9x5-clk-master"; 173 #clock-cells = <0>; 174 interrupts-extended = <&pmc AT91_PMC_MCKRDY>; 175 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>; 176 atmel,clk-output-range = <0 133333333>; 177 atmel,clk-divisors = <1 2 4 3>; 178 atmel,master-clk-have-div3-pres; 179 u-boot,dm-pre-reloc; 180 181 }; 182 183 usb: usbck { 184 compatible = "atmel,at91sam9x5-clk-usb"; 185 #clock-cells = <0>; 186 clocks = <&plladiv>, <&utmi>; 187 }; 188 189 prog: progck { 190 compatible = "atmel,at91sam9x5-clk-programmable"; 191 #address-cells = <1>; 192 #size-cells = <0>; 193 interrupt-parent = <&pmc>; 194 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>; 195 196 prog0: prog@0 { 197 #clock-cells = <0>; 198 reg = <0>; 199 interrupts = <AT91_PMC_PCKRDY(0)>; 200 }; 201 202 prog1: prog@1 { 203 #clock-cells = <0>; 204 reg = <1>; 205 interrupts = <AT91_PMC_PCKRDY(1)>; 206 }; 207 }; 208 209 smd: smdclk { 210 compatible = "atmel,at91sam9x5-clk-smd"; 211 #clock-cells = <0>; 212 clocks = <&plladiv>, <&utmi>; 213 }; 214 215 systemck { 216 compatible = "atmel,at91rm9200-clk-system"; 217 #address-cells = <1>; 218 #size-cells = <0>; 219 220 ddrck: ddrck@2 { 221 #clock-cells = <0>; 222 reg = <2>; 223 clocks = <&mck>; 224 }; 225 226 smdck: smdck@4 { 227 #clock-cells = <0>; 228 reg = <4>; 229 clocks = <&smd>; 230 }; 231 232 uhpck: uhpck@6 { 233 #clock-cells = <0>; 234 reg = <6>; 235 clocks = <&usb>; 236 }; 237 238 udpck: udpck@7 { 239 #clock-cells = <0>; 240 reg = <7>; 241 clocks = <&usb>; 242 }; 243 244 pck0: pck0@8 { 245 #clock-cells = <0>; 246 reg = <8>; 247 clocks = <&prog0>; 248 }; 249 250 pck1: pck1@9 { 251 #clock-cells = <0>; 252 reg = <9>; 253 clocks = <&prog1>; 254 }; 255 }; 256 257 periphck { 258 compatible = "atmel,at91sam9x5-clk-peripheral"; 259 #address-cells = <1>; 260 #size-cells = <0>; 261 clocks = <&mck>; 262 u-boot,dm-pre-reloc; 263 264 265 pioAB_clk: pioAB_clk@2 { 266 #clock-cells = <0>; 267 reg = <2>; 268 }; 269 270 pioCD_clk: pioCD_clk@3 { 271 #clock-cells = <0>; 272 reg = <3>; 273 }; 274 275 smd_clk: smd_clk@4 { 276 #clock-cells = <0>; 277 reg = <4>; 278 }; 279 280 usart0_clk: usart0_clk@5 { 281 #clock-cells = <0>; 282 reg = <5>; 283 }; 284 285 usart1_clk: usart1_clk@6 { 286 #clock-cells = <0>; 287 reg = <6>; 288 }; 289 290 usart2_clk: usart2_clk@7 { 291 #clock-cells = <0>; 292 reg = <7>; 293 }; 294 295 twi0_clk: twi0_clk@9 { 296 reg = <9>; 297 #clock-cells = <0>; 298 }; 299 300 twi1_clk: twi1_clk@10 { 301 #clock-cells = <0>; 302 reg = <10>; 303 }; 304 305 twi2_clk: twi2_clk@11 { 306 #clock-cells = <0>; 307 reg = <11>; 308 }; 309 310 mci0_clk: mci0_clk@12 { 311 #clock-cells = <0>; 312 reg = <12>; 313 }; 314 315 spi0_clk: spi0_clk@13 { 316 #clock-cells = <0>; 317 reg = <13>; 318 }; 319 320 spi1_clk: spi1_clk@14 { 321 #clock-cells = <0>; 322 reg = <14>; 323 }; 324 325 uart0_clk: uart0_clk@15 { 326 #clock-cells = <0>; 327 reg = <15>; 328 }; 329 330 uart1_clk: uart1_clk@16 { 331 #clock-cells = <0>; 332 reg = <16>; 333 }; 334 335 tcb0_clk: tcb0_clk@17 { 336 #clock-cells = <0>; 337 reg = <17>; 338 }; 339 340 pwm_clk: pwm_clk@18 { 341 #clock-cells = <0>; 342 reg = <18>; 343 }; 344 345 adc_clk: adc_clk@19 { 346 #clock-cells = <0>; 347 reg = <19>; 348 }; 349 350 dma0_clk: dma0_clk@20 { 351 #clock-cells = <0>; 352 reg = <20>; 353 }; 354 355 dma1_clk: dma1_clk@21 { 356 #clock-cells = <0>; 357 reg = <21>; 358 }; 359 360 uhphs_clk: uhphs_clk@22 { 361 #clock-cells = <0>; 362 reg = <22>; 363 }; 364 365 udphs_clk: udphs_clk@23 { 366 #clock-cells = <0>; 367 reg = <23>; 368 }; 369 370 mci1_clk: mci1_clk@26 { 371 #clock-cells = <0>; 372 reg = <26>; 373 }; 374 375 ssc0_clk: ssc0_clk@28 { 376 #clock-cells = <0>; 377 reg = <28>; 378 }; 379 }; 380 }; 381 382 rstc@fffffe00 { 383 compatible = "atmel,at91sam9g45-rstc"; 384 reg = <0xfffffe00 0x10>; 385 clocks = <&clk32k>; 386 }; 387 388 shdwc@fffffe10 { 389 compatible = "atmel,at91sam9x5-shdwc"; 390 reg = <0xfffffe10 0x10>; 391 clocks = <&clk32k>; 392 }; 393 394 pit: timer@fffffe30 { 395 compatible = "atmel,at91sam9260-pit"; 396 reg = <0xfffffe30 0xf>; 397 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 398 clocks = <&mck>; 399 }; 400 401 sckc@fffffe50 { 402 compatible = "atmel,at91sam9x5-sckc"; 403 reg = <0xfffffe50 0x4>; 404 405 slow_osc: slow_osc { 406 compatible = "atmel,at91sam9x5-clk-slow-osc"; 407 #clock-cells = <0>; 408 clocks = <&slow_xtal>; 409 }; 410 411 slow_rc_osc: slow_rc_osc { 412 compatible = "atmel,at91sam9x5-clk-slow-rc-osc"; 413 #clock-cells = <0>; 414 clock-frequency = <32768>; 415 clock-accuracy = <50000000>; 416 }; 417 418 clk32k: slck { 419 compatible = "atmel,at91sam9x5-clk-slow"; 420 #clock-cells = <0>; 421 clocks = <&slow_rc_osc>, <&slow_osc>; 422 }; 423 }; 424 425 tcb0: timer@f8008000 { 426 compatible = "atmel,at91sam9x5-tcb"; 427 reg = <0xf8008000 0x100>; 428 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; 429 clocks = <&tcb0_clk>, <&clk32k>; 430 clock-names = "t0_clk", "slow_clk"; 431 }; 432 433 tcb1: timer@f800c000 { 434 compatible = "atmel,at91sam9x5-tcb"; 435 reg = <0xf800c000 0x100>; 436 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; 437 clocks = <&tcb0_clk>, <&clk32k>; 438 clock-names = "t0_clk", "slow_clk"; 439 }; 440 441 dma0: dma-controller@ffffec00 { 442 compatible = "atmel,at91sam9g45-dma"; 443 reg = <0xffffec00 0x200>; 444 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; 445 #dma-cells = <2>; 446 clocks = <&dma0_clk>; 447 clock-names = "dma_clk"; 448 }; 449 450 dma1: dma-controller@ffffee00 { 451 compatible = "atmel,at91sam9g45-dma"; 452 reg = <0xffffee00 0x200>; 453 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>; 454 #dma-cells = <2>; 455 clocks = <&dma1_clk>; 456 clock-names = "dma_clk"; 457 }; 458 459 pinctrl@fffff400 { 460 #address-cells = <1>; 461 #size-cells = <1>; 462 compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus"; 463 ranges = <0xfffff400 0xfffff400 0x800>; 464 reg = <0xfffff400 0x200 /* pioA */ 465 0xfffff600 0x200 /* pioB */ 466 0xfffff800 0x200 /* pioC */ 467 0xfffffa00 0x200 /* pioD */ 468 >; 469 u-boot,dm-pre-reloc; 470 471 472 /* shared pinctrl settings */ 473 dbgu { 474 u-boot,dm-pre-reloc; 475 pinctrl_dbgu: dbgu-0 { 476 atmel,pins = 477 <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP 478 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; 479 }; 480 }; 481 482 usart0 { 483 pinctrl_usart0: usart0-0 { 484 atmel,pins = 485 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA0 periph A with pullup */ 486 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA1 periph A */ 487 }; 488 489 pinctrl_usart0_rts: usart0_rts-0 { 490 atmel,pins = 491 <AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA2 periph A */ 492 }; 493 494 pinctrl_usart0_cts: usart0_cts-0 { 495 atmel,pins = 496 <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA3 periph A */ 497 }; 498 499 pinctrl_usart0_sck: usart0_sck-0 { 500 atmel,pins = 501 <AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA4 periph A */ 502 }; 503 }; 504 505 usart1 { 506 pinctrl_usart1: usart1-0 { 507 atmel,pins = 508 <AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA5 periph A with pullup */ 509 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA6 periph A */ 510 }; 511 512 pinctrl_usart1_rts: usart1_rts-0 { 513 atmel,pins = 514 <AT91_PIOC 27 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC27 periph C */ 515 }; 516 517 pinctrl_usart1_cts: usart1_cts-0 { 518 atmel,pins = 519 <AT91_PIOC 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC28 periph C */ 520 }; 521 522 pinctrl_usart1_sck: usart1_sck-0 { 523 atmel,pins = 524 <AT91_PIOC 29 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC29 periph C */ 525 }; 526 }; 527 528 usart2 { 529 pinctrl_usart2: usart2-0 { 530 atmel,pins = 531 <AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA7 periph A with pullup */ 532 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA8 periph A */ 533 }; 534 535 pinctrl_usart2_rts: usart2_rts-0 { 536 atmel,pins = 537 <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB0 periph B */ 538 }; 539 540 pinctrl_usart2_cts: usart2_cts-0 { 541 atmel,pins = 542 <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB1 periph B */ 543 }; 544 545 pinctrl_usart2_sck: usart2_sck-0 { 546 atmel,pins = 547 <AT91_PIOB 2 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB2 periph B */ 548 }; 549 }; 550 551 uart0 { 552 pinctrl_uart0: uart0-0 { 553 atmel,pins = 554 <AT91_PIOC 8 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC8 periph C */ 555 AT91_PIOC 9 AT91_PERIPH_C AT91_PINCTRL_PULL_UP>; /* PC9 periph C with pullup */ 556 }; 557 }; 558 559 uart1 { 560 pinctrl_uart1: uart1-0 { 561 atmel,pins = 562 <AT91_PIOC 16 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC16 periph C */ 563 AT91_PIOC 17 AT91_PERIPH_C AT91_PINCTRL_PULL_UP>; /* PC17 periph C with pullup */ 564 }; 565 }; 566 567 nand { 568 pinctrl_nand: nand-0 { 569 atmel,pins = 570 <AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD0 periph A Read Enable */ 571 AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD1 periph A Write Enable */ 572 AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD2 periph A Address Latch Enable */ 573 AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD3 periph A Command Latch Enable */ 574 AT91_PIOD 4 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PD4 gpio Chip Enable pin pull_up */ 575 AT91_PIOD 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PD5 gpio RDY/BUSY pin pull_up */ 576 AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD6 periph A Data bit 0 */ 577 AT91_PIOD 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD7 periph A Data bit 1 */ 578 AT91_PIOD 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD8 periph A Data bit 2 */ 579 AT91_PIOD 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD9 periph A Data bit 3 */ 580 AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD10 periph A Data bit 4 */ 581 AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD11 periph A Data bit 5 */ 582 AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD12 periph A Data bit 6 */ 583 AT91_PIOD 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD13 periph A Data bit 7 */ 584 }; 585 586 pinctrl_nand_16bits: nand_16bits-0 { 587 atmel,pins = 588 <AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD14 periph A Data bit 8 */ 589 AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD15 periph A Data bit 9 */ 590 AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD16 periph A Data bit 10 */ 591 AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD17 periph A Data bit 11 */ 592 AT91_PIOD 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD18 periph A Data bit 12 */ 593 AT91_PIOD 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD19 periph A Data bit 13 */ 594 AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD20 periph A Data bit 14 */ 595 AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD21 periph A Data bit 15 */ 596 }; 597 }; 598 599 mmc0 { 600 pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 { 601 atmel,pins = 602 <AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA17 periph A */ 603 AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA16 periph A with pullup */ 604 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA15 periph A with pullup */ 605 }; 606 607 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { 608 atmel,pins = 609 <AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA18 periph A with pullup */ 610 AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA19 periph A with pullup */ 611 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA20 periph A with pullup */ 612 }; 613 }; 614 615 mmc1 { 616 pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 { 617 atmel,pins = 618 <AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA13 periph B */ 619 AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA12 periph B with pullup */ 620 AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA11 periph B with pullup */ 621 }; 622 623 pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 { 624 atmel,pins = 625 <AT91_PIOA 2 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA2 periph B with pullup */ 626 AT91_PIOA 3 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA3 periph B with pullup */ 627 AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA4 periph B with pullup */ 628 }; 629 }; 630 631 ssc0 { 632 pinctrl_ssc0_tx: ssc0_tx-0 { 633 atmel,pins = 634 <AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA24 periph B */ 635 AT91_PIOA 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA25 periph B */ 636 AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA26 periph B */ 637 }; 638 639 pinctrl_ssc0_rx: ssc0_rx-0 { 640 atmel,pins = 641 <AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA27 periph B */ 642 AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA28 periph B */ 643 AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA29 periph B */ 644 }; 645 }; 646 647 spi0 { 648 pinctrl_spi0: spi0-0 { 649 atmel,pins = 650 <AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A SPI0_MISO pin */ 651 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A SPI0_MOSI pin */ 652 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA13 periph A SPI0_SPCK pin */ 653 }; 654 }; 655 656 spi1 { 657 pinctrl_spi1: spi1-0 { 658 atmel,pins = 659 <AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA21 periph B SPI1_MISO pin */ 660 AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA22 periph B SPI1_MOSI pin */ 661 AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA23 periph B SPI1_SPCK pin */ 662 }; 663 }; 664 665 i2c0 { 666 pinctrl_i2c0: i2c0-0 { 667 atmel,pins = 668 <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA30 periph A I2C0 data */ 669 AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA31 periph A I2C0 clock */ 670 }; 671 }; 672 673 i2c1 { 674 pinctrl_i2c1: i2c1-0 { 675 atmel,pins = 676 <AT91_PIOC 0 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC0 periph C I2C1 data */ 677 AT91_PIOC 1 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC1 periph C I2C1 clock */ 678 }; 679 }; 680 681 i2c2 { 682 pinctrl_i2c2: i2c2-0 { 683 atmel,pins = 684 <AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB4 periph B I2C2 data */ 685 AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB5 periph B I2C2 clock */ 686 }; 687 }; 688 689 i2c_gpio0 { 690 pinctrl_i2c_gpio0: i2c_gpio0-0 { 691 atmel,pins = 692 <AT91_PIOA 30 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE /* PA30 gpio multidrive I2C0 data */ 693 AT91_PIOA 31 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>; /* PA31 gpio multidrive I2C0 clock */ 694 }; 695 }; 696 697 i2c_gpio1 { 698 pinctrl_i2c_gpio1: i2c_gpio1-0 { 699 atmel,pins = 700 <AT91_PIOC 0 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE /* PC0 gpio multidrive I2C1 data */ 701 AT91_PIOC 1 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>; /* PC1 gpio multidrive I2C1 clock */ 702 }; 703 }; 704 705 i2c_gpio2 { 706 pinctrl_i2c_gpio2: i2c_gpio2-0 { 707 atmel,pins = 708 <AT91_PIOB 4 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE /* PB4 gpio multidrive I2C2 data */ 709 AT91_PIOB 5 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>; /* PB5 gpio multidrive I2C2 clock */ 710 }; 711 }; 712 713 pwm0 { 714 pinctrl_pwm0_pwm0_0: pwm0_pwm0-0 { 715 atmel,pins = 716 <AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; 717 }; 718 pinctrl_pwm0_pwm0_1: pwm0_pwm0-1 { 719 atmel,pins = 720 <AT91_PIOC 10 AT91_PERIPH_C AT91_PINCTRL_NONE>; 721 }; 722 pinctrl_pwm0_pwm0_2: pwm0_pwm0-2 { 723 atmel,pins = 724 <AT91_PIOC 18 AT91_PERIPH_C AT91_PINCTRL_NONE>; 725 }; 726 727 pinctrl_pwm0_pwm1_0: pwm0_pwm1-0 { 728 atmel,pins = 729 <AT91_PIOB 12 AT91_PERIPH_B AT91_PINCTRL_NONE>; 730 }; 731 pinctrl_pwm0_pwm1_1: pwm0_pwm1-1 { 732 atmel,pins = 733 <AT91_PIOC 11 AT91_PERIPH_C AT91_PINCTRL_NONE>; 734 }; 735 pinctrl_pwm0_pwm1_2: pwm0_pwm1-2 { 736 atmel,pins = 737 <AT91_PIOC 19 AT91_PERIPH_C AT91_PINCTRL_NONE>; 738 }; 739 740 pinctrl_pwm0_pwm2_0: pwm0_pwm2-0 { 741 atmel,pins = 742 <AT91_PIOB 13 AT91_PERIPH_B AT91_PINCTRL_NONE>; 743 }; 744 pinctrl_pwm0_pwm2_1: pwm0_pwm2-1 { 745 atmel,pins = 746 <AT91_PIOC 20 AT91_PERIPH_C AT91_PINCTRL_NONE>; 747 }; 748 749 pinctrl_pwm0_pwm3_0: pwm0_pwm3-0 { 750 atmel,pins = 751 <AT91_PIOB 14 AT91_PERIPH_B AT91_PINCTRL_NONE>; 752 }; 753 pinctrl_pwm0_pwm3_1: pwm0_pwm3-1 { 754 atmel,pins = 755 <AT91_PIOC 21 AT91_PERIPH_C AT91_PINCTRL_NONE>; 756 }; 757 }; 758 759 tcb0 { 760 pinctrl_tcb0_tclk0: tcb0_tclk0-0 { 761 atmel,pins = <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; 762 }; 763 764 pinctrl_tcb0_tclk1: tcb0_tclk1-0 { 765 atmel,pins = <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; 766 }; 767 768 pinctrl_tcb0_tclk2: tcb0_tclk2-0 { 769 atmel,pins = <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; 770 }; 771 772 pinctrl_tcb0_tioa0: tcb0_tioa0-0 { 773 atmel,pins = <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; 774 }; 775 776 pinctrl_tcb0_tioa1: tcb0_tioa1-0 { 777 atmel,pins = <AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE>; 778 }; 779 780 pinctrl_tcb0_tioa2: tcb0_tioa2-0 { 781 atmel,pins = <AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; 782 }; 783 784 pinctrl_tcb0_tiob0: tcb0_tiob0-0 { 785 atmel,pins = <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; 786 }; 787 788 pinctrl_tcb0_tiob1: tcb0_tiob1-0 { 789 atmel,pins = <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; 790 }; 791 792 pinctrl_tcb0_tiob2: tcb0_tiob2-0 { 793 atmel,pins = <AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; 794 }; 795 }; 796 797 tcb1 { 798 pinctrl_tcb1_tclk0: tcb1_tclk0-0 { 799 atmel,pins = <AT91_PIOC 4 AT91_PERIPH_C AT91_PINCTRL_NONE>; 800 }; 801 802 pinctrl_tcb1_tclk1: tcb1_tclk1-0 { 803 atmel,pins = <AT91_PIOC 7 AT91_PERIPH_C AT91_PINCTRL_NONE>; 804 }; 805 806 pinctrl_tcb1_tclk2: tcb1_tclk2-0 { 807 atmel,pins = <AT91_PIOC 14 AT91_PERIPH_C AT91_PINCTRL_NONE>; 808 }; 809 810 pinctrl_tcb1_tioa0: tcb1_tioa0-0 { 811 atmel,pins = <AT91_PIOC 2 AT91_PERIPH_C AT91_PINCTRL_NONE>; 812 }; 813 814 pinctrl_tcb1_tioa1: tcb1_tioa1-0 { 815 atmel,pins = <AT91_PIOC 5 AT91_PERIPH_C AT91_PINCTRL_NONE>; 816 }; 817 818 pinctrl_tcb1_tioa2: tcb1_tioa2-0 { 819 atmel,pins = <AT91_PIOC 12 AT91_PERIPH_C AT91_PINCTRL_NONE>; 820 }; 821 822 pinctrl_tcb1_tiob0: tcb1_tiob0-0 { 823 atmel,pins = <AT91_PIOC 3 AT91_PERIPH_C AT91_PINCTRL_NONE>; 824 }; 825 826 pinctrl_tcb1_tiob1: tcb1_tiob1-0 { 827 atmel,pins = <AT91_PIOC 6 AT91_PERIPH_C AT91_PINCTRL_NONE>; 828 }; 829 830 pinctrl_tcb1_tiob2: tcb1_tiob2-0 { 831 atmel,pins = <AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE>; 832 }; 833 }; 834 }; 835 836 pioA: gpio@fffff400 { 837 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 838 reg = <0xfffff400 0x200>; 839 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; 840 #gpio-cells = <2>; 841 gpio-controller; 842 interrupt-controller; 843 #interrupt-cells = <2>; 844 clocks = <&pioAB_clk>; 845 }; 846 847 pioB: gpio@fffff600 { 848 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 849 reg = <0xfffff600 0x200>; 850 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; 851 #gpio-cells = <2>; 852 gpio-controller; 853 #gpio-lines = <19>; 854 interrupt-controller; 855 #interrupt-cells = <2>; 856 clocks = <&pioAB_clk>; 857 }; 858 859 pioC: gpio@fffff800 { 860 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 861 reg = <0xfffff800 0x200>; 862 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; 863 #gpio-cells = <2>; 864 gpio-controller; 865 interrupt-controller; 866 #interrupt-cells = <2>; 867 clocks = <&pioCD_clk>; 868 }; 869 870 pioD: gpio@fffffa00 { 871 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 872 reg = <0xfffffa00 0x200>; 873 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; 874 #gpio-cells = <2>; 875 gpio-controller; 876 #gpio-lines = <22>; 877 interrupt-controller; 878 #interrupt-cells = <2>; 879 clocks = <&pioCD_clk>; 880 }; 881 882 ssc0: ssc@f0010000 { 883 compatible = "atmel,at91sam9g45-ssc"; 884 reg = <0xf0010000 0x4000>; 885 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>; 886 dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(13)>, 887 <&dma0 1 AT91_DMA_CFG_PER_ID(14)>; 888 dma-names = "tx", "rx"; 889 pinctrl-names = "default"; 890 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; 891 clocks = <&ssc0_clk>; 892 clock-names = "pclk"; 893 status = "disabled"; 894 }; 895 896 mmc0: mmc@f0008000 { 897 compatible = "atmel,hsmci"; 898 reg = <0xf0008000 0x600>; 899 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; 900 dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(0)>; 901 dma-names = "rxtx"; 902 pinctrl-names = "default"; 903 clocks = <&mci0_clk>; 904 clock-names = "mci_clk"; 905 #address-cells = <1>; 906 #size-cells = <0>; 907 status = "disabled"; 908 }; 909 910 mmc1: mmc@f000c000 { 911 compatible = "atmel,hsmci"; 912 reg = <0xf000c000 0x600>; 913 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>; 914 dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(0)>; 915 dma-names = "rxtx"; 916 pinctrl-names = "default"; 917 clocks = <&mci1_clk>; 918 clock-names = "mci_clk"; 919 #address-cells = <1>; 920 #size-cells = <0>; 921 status = "disabled"; 922 }; 923 924 dbgu: serial@fffff200 { 925 compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; 926 reg = <0xfffff200 0x200>; 927 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 928 pinctrl-names = "default"; 929 pinctrl-0 = <&pinctrl_dbgu>; 930 dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(8)>, 931 <&dma1 1 (AT91_DMA_CFG_PER_ID(9) | AT91_DMA_CFG_FIFOCFG_ASAP)>; 932 dma-names = "tx", "rx"; 933 clocks = <&mck>; 934 clock-names = "usart"; 935 status = "disabled"; 936 }; 937 938 usart0: serial@f801c000 { 939 compatible = "atmel,at91sam9260-usart"; 940 reg = <0xf801c000 0x200>; 941 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>; 942 pinctrl-names = "default"; 943 pinctrl-0 = <&pinctrl_usart0>; 944 dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(3)>, 945 <&dma0 1 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASAP)>; 946 dma-names = "tx", "rx"; 947 clocks = <&usart0_clk>; 948 clock-names = "usart"; 949 status = "disabled"; 950 }; 951 952 usart1: serial@f8020000 { 953 compatible = "atmel,at91sam9260-usart"; 954 reg = <0xf8020000 0x200>; 955 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; 956 pinctrl-names = "default"; 957 pinctrl-0 = <&pinctrl_usart1>; 958 dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(5)>, 959 <&dma0 1 (AT91_DMA_CFG_PER_ID(6) | AT91_DMA_CFG_FIFOCFG_ASAP)>; 960 dma-names = "tx", "rx"; 961 clocks = <&usart1_clk>; 962 clock-names = "usart"; 963 status = "disabled"; 964 }; 965 966 usart2: serial@f8024000 { 967 compatible = "atmel,at91sam9260-usart"; 968 reg = <0xf8024000 0x200>; 969 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; 970 pinctrl-names = "default"; 971 pinctrl-0 = <&pinctrl_usart2>; 972 dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(12)>, 973 <&dma1 1 (AT91_DMA_CFG_PER_ID(13) | AT91_DMA_CFG_FIFOCFG_ASAP)>; 974 dma-names = "tx", "rx"; 975 clocks = <&usart2_clk>; 976 clock-names = "usart"; 977 status = "disabled"; 978 }; 979 980 i2c0: i2c@f8010000 { 981 compatible = "atmel,at91sam9x5-i2c"; 982 reg = <0xf8010000 0x100>; 983 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 6>; 984 dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(7)>, 985 <&dma0 1 AT91_DMA_CFG_PER_ID(8)>; 986 dma-names = "tx", "rx"; 987 #address-cells = <1>; 988 #size-cells = <0>; 989 pinctrl-names = "default"; 990 pinctrl-0 = <&pinctrl_i2c0>; 991 clocks = <&twi0_clk>; 992 status = "disabled"; 993 }; 994 995 i2c1: i2c@f8014000 { 996 compatible = "atmel,at91sam9x5-i2c"; 997 reg = <0xf8014000 0x100>; 998 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 6>; 999 dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(5)>, 1000 <&dma1 1 AT91_DMA_CFG_PER_ID(6)>; 1001 dma-names = "tx", "rx"; 1002 #address-cells = <1>; 1003 #size-cells = <0>; 1004 pinctrl-names = "default"; 1005 pinctrl-0 = <&pinctrl_i2c1>; 1006 clocks = <&twi1_clk>; 1007 status = "disabled"; 1008 }; 1009 1010 i2c2: i2c@f8018000 { 1011 compatible = "atmel,at91sam9x5-i2c"; 1012 reg = <0xf8018000 0x100>; 1013 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>; 1014 dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(9)>, 1015 <&dma0 1 AT91_DMA_CFG_PER_ID(10)>; 1016 dma-names = "tx", "rx"; 1017 #address-cells = <1>; 1018 #size-cells = <0>; 1019 pinctrl-names = "default"; 1020 pinctrl-0 = <&pinctrl_i2c2>; 1021 clocks = <&twi2_clk>; 1022 status = "disabled"; 1023 }; 1024 1025 uart0: serial@f8040000 { 1026 compatible = "atmel,at91sam9260-usart"; 1027 reg = <0xf8040000 0x200>; 1028 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; 1029 pinctrl-names = "default"; 1030 pinctrl-0 = <&pinctrl_uart0>; 1031 clocks = <&uart0_clk>; 1032 clock-names = "usart"; 1033 status = "disabled"; 1034 }; 1035 1036 uart1: serial@f8044000 { 1037 compatible = "atmel,at91sam9260-usart"; 1038 reg = <0xf8044000 0x200>; 1039 interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; 1040 pinctrl-names = "default"; 1041 pinctrl-0 = <&pinctrl_uart1>; 1042 clocks = <&uart1_clk>; 1043 clock-names = "usart"; 1044 status = "disabled"; 1045 }; 1046 1047 adc0: adc@f804c000 { 1048 compatible = "atmel,at91sam9x5-adc"; 1049 reg = <0xf804c000 0x100>; 1050 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>; 1051 clocks = <&adc_clk>, 1052 <&adc_op_clk>; 1053 clock-names = "adc_clk", "adc_op_clk"; 1054 atmel,adc-use-external-triggers; 1055 atmel,adc-channels-used = <0xffff>; 1056 atmel,adc-vref = <3300>; 1057 atmel,adc-startup-time = <40>; 1058 atmel,adc-sample-hold-time = <11>; 1059 atmel,adc-res = <8 10>; 1060 atmel,adc-res-names = "lowres", "highres"; 1061 atmel,adc-use-res = "highres"; 1062 1063 trigger0 { 1064 trigger-name = "external-rising"; 1065 trigger-value = <0x1>; 1066 trigger-external; 1067 }; 1068 1069 trigger1 { 1070 trigger-name = "external-falling"; 1071 trigger-value = <0x2>; 1072 trigger-external; 1073 }; 1074 1075 trigger2 { 1076 trigger-name = "external-any"; 1077 trigger-value = <0x3>; 1078 trigger-external; 1079 }; 1080 1081 trigger3 { 1082 trigger-name = "continuous"; 1083 trigger-value = <0x6>; 1084 }; 1085 }; 1086 1087 spi0: spi@f0000000 { 1088 #address-cells = <1>; 1089 #size-cells = <0>; 1090 compatible = "atmel,at91rm9200-spi"; 1091 reg = <0xf0000000 0x100>; 1092 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>; 1093 dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(1)>, 1094 <&dma0 1 AT91_DMA_CFG_PER_ID(2)>; 1095 dma-names = "tx", "rx"; 1096 pinctrl-names = "default"; 1097 pinctrl-0 = <&pinctrl_spi0>; 1098 clocks = <&spi0_clk>; 1099 clock-names = "spi_clk"; 1100 status = "disabled"; 1101 }; 1102 1103 spi1: spi@f0004000 { 1104 #address-cells = <1>; 1105 #size-cells = <0>; 1106 compatible = "atmel,at91rm9200-spi"; 1107 reg = <0xf0004000 0x100>; 1108 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>; 1109 dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(1)>, 1110 <&dma1 1 AT91_DMA_CFG_PER_ID(2)>; 1111 dma-names = "tx", "rx"; 1112 pinctrl-names = "default"; 1113 pinctrl-0 = <&pinctrl_spi1>; 1114 clocks = <&spi1_clk>; 1115 clock-names = "spi_clk"; 1116 status = "disabled"; 1117 }; 1118 1119 usb2: gadget@f803c000 { 1120 #address-cells = <1>; 1121 #size-cells = <0>; 1122 compatible = "atmel,at91sam9g45-udc"; 1123 reg = <0x00500000 0x80000 1124 0xf803c000 0x400>; 1125 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>; 1126 clocks = <&utmi>, <&udphs_clk>; 1127 clock-names = "hclk", "pclk"; 1128 status = "disabled"; 1129 1130 ep@0 { 1131 reg = <0>; 1132 atmel,fifo-size = <64>; 1133 atmel,nb-banks = <1>; 1134 }; 1135 1136 ep@1 { 1137 reg = <1>; 1138 atmel,fifo-size = <1024>; 1139 atmel,nb-banks = <2>; 1140 atmel,can-dma; 1141 atmel,can-isoc; 1142 }; 1143 1144 ep@2 { 1145 reg = <2>; 1146 atmel,fifo-size = <1024>; 1147 atmel,nb-banks = <2>; 1148 atmel,can-dma; 1149 atmel,can-isoc; 1150 }; 1151 1152 ep@3 { 1153 reg = <3>; 1154 atmel,fifo-size = <1024>; 1155 atmel,nb-banks = <3>; 1156 atmel,can-dma; 1157 }; 1158 1159 ep@4 { 1160 reg = <4>; 1161 atmel,fifo-size = <1024>; 1162 atmel,nb-banks = <3>; 1163 atmel,can-dma; 1164 }; 1165 1166 ep@5 { 1167 reg = <5>; 1168 atmel,fifo-size = <1024>; 1169 atmel,nb-banks = <3>; 1170 atmel,can-dma; 1171 atmel,can-isoc; 1172 }; 1173 1174 ep@6 { 1175 reg = <6>; 1176 atmel,fifo-size = <1024>; 1177 atmel,nb-banks = <3>; 1178 atmel,can-dma; 1179 atmel,can-isoc; 1180 }; 1181 }; 1182 1183 watchdog@fffffe40 { 1184 compatible = "atmel,at91sam9260-wdt"; 1185 reg = <0xfffffe40 0x10>; 1186 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 1187 clocks = <&clk32k>; 1188 atmel,watchdog-type = "hardware"; 1189 atmel,reset-type = "all"; 1190 atmel,dbg-halt; 1191 status = "disabled"; 1192 }; 1193 1194 rtc@fffffeb0 { 1195 compatible = "atmel,at91sam9x5-rtc"; 1196 reg = <0xfffffeb0 0x40>; 1197 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 1198 clocks = <&clk32k>; 1199 status = "disabled"; 1200 }; 1201 1202 pwm0: pwm@f8034000 { 1203 compatible = "atmel,at91sam9rl-pwm"; 1204 reg = <0xf8034000 0x300>; 1205 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>; 1206 clocks = <&pwm_clk>; 1207 #pwm-cells = <3>; 1208 status = "disabled"; 1209 }; 1210 }; 1211 1212 nand0: nand@40000000 { 1213 compatible = "atmel,at91rm9200-nand"; 1214 #address-cells = <1>; 1215 #size-cells = <1>; 1216 reg = <0x40000000 0x10000000 1217 0xffffe000 0x600 /* PMECC Registers */ 1218 0xffffe600 0x200 /* PMECC Error Location Registers */ 1219 0x00108000 0x18000 /* PMECC looup table in ROM code */ 1220 >; 1221 atmel,pmecc-lookup-table-offset = <0x0 0x8000>; 1222 atmel,nand-addr-offset = <21>; 1223 atmel,nand-cmd-offset = <22>; 1224 atmel,nand-has-dma; 1225 pinctrl-names = "default"; 1226 pinctrl-0 = <&pinctrl_nand>; 1227 gpios = <&pioD 5 GPIO_ACTIVE_HIGH 1228 &pioD 4 GPIO_ACTIVE_HIGH 1229 0 1230 >; 1231 status = "disabled"; 1232 }; 1233 1234 usb0: ohci@00600000 { 1235 compatible = "atmel,at91rm9200-ohci", "usb-ohci"; 1236 reg = <0x00600000 0x100000>; 1237 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; 1238 clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>; 1239 clock-names = "ohci_clk", "hclk", "uhpck"; 1240 status = "disabled"; 1241 }; 1242 1243 usb1: ehci@00700000 { 1244 compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; 1245 reg = <0x00700000 0x100000>; 1246 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; 1247 clocks = <&utmi>, <&uhphs_clk>; 1248 clock-names = "usb_clk", "ehci_clk"; 1249 status = "disabled"; 1250 }; 1251 }; 1252 1253 i2c-gpio-0 { 1254 compatible = "i2c-gpio"; 1255 gpios = <&pioA 30 GPIO_ACTIVE_HIGH /* sda */ 1256 &pioA 31 GPIO_ACTIVE_HIGH /* scl */ 1257 >; 1258 i2c-gpio,sda-open-drain; 1259 i2c-gpio,scl-open-drain; 1260 i2c-gpio,delay-us = <2>; /* ~100 kHz */ 1261 #address-cells = <1>; 1262 #size-cells = <0>; 1263 pinctrl-names = "default"; 1264 pinctrl-0 = <&pinctrl_i2c_gpio0>; 1265 status = "disabled"; 1266 }; 1267 1268 i2c-gpio-1 { 1269 compatible = "i2c-gpio"; 1270 gpios = <&pioC 0 GPIO_ACTIVE_HIGH /* sda */ 1271 &pioC 1 GPIO_ACTIVE_HIGH /* scl */ 1272 >; 1273 i2c-gpio,sda-open-drain; 1274 i2c-gpio,scl-open-drain; 1275 i2c-gpio,delay-us = <2>; /* ~100 kHz */ 1276 #address-cells = <1>; 1277 #size-cells = <0>; 1278 pinctrl-names = "default"; 1279 pinctrl-0 = <&pinctrl_i2c_gpio1>; 1280 status = "disabled"; 1281 }; 1282 1283 i2c-gpio-2 { 1284 compatible = "i2c-gpio"; 1285 gpios = <&pioB 4 GPIO_ACTIVE_HIGH /* sda */ 1286 &pioB 5 GPIO_ACTIVE_HIGH /* scl */ 1287 >; 1288 i2c-gpio,sda-open-drain; 1289 i2c-gpio,scl-open-drain; 1290 i2c-gpio,delay-us = <2>; /* ~100 kHz */ 1291 #address-cells = <1>; 1292 #size-cells = <0>; 1293 pinctrl-names = "default"; 1294 pinctrl-0 = <&pinctrl_i2c_gpio2>; 1295 status = "disabled"; 1296 }; 1297}; 1298