1/* 2 * at91sam9g45.dtsi - Device Tree Include file for AT91SAM9G45 family SoC 3 * applies to AT91SAM9G45, AT91SAM9M10, 4 * AT91SAM9G46, AT91SAM9M11 SoC 5 * 6 * Copyright (C) 2011 Atmel, 7 * 2011 Nicolas Ferre <nicolas.ferre@atmel.com> 8 * 9 * Licensed under GPLv2 or later. 10 */ 11 12#include "skeleton.dtsi" 13#include <dt-bindings/dma/at91.h> 14#include <dt-bindings/pinctrl/at91.h> 15#include <dt-bindings/interrupt-controller/irq.h> 16#include <dt-bindings/gpio/gpio.h> 17#include <dt-bindings/clock/at91.h> 18 19/ { 20 model = "Atmel AT91SAM9G45 family SoC"; 21 compatible = "atmel,at91sam9g45"; 22 interrupt-parent = <&aic>; 23 24 aliases { 25 serial0 = &dbgu; 26 serial1 = &usart0; 27 serial2 = &usart1; 28 serial3 = &usart2; 29 serial4 = &usart3; 30 gpio0 = &pioA; 31 gpio1 = &pioB; 32 gpio2 = &pioC; 33 gpio3 = &pioD; 34 gpio4 = &pioE; 35 tcb0 = &tcb0; 36 tcb1 = &tcb1; 37 i2c0 = &i2c0; 38 i2c1 = &i2c1; 39 ssc0 = &ssc0; 40 ssc1 = &ssc1; 41 pwm0 = &pwm0; 42 }; 43 cpus { 44 cpu { 45 compatible = "arm,arm926ej-s"; 46 device_type = "cpu"; 47 }; 48 }; 49 50 memory { 51 reg = <0x70000000 0x10000000>; 52 }; 53 54 clocks { 55 slow_xtal: slow_xtal { 56 compatible = "fixed-clock"; 57 #clock-cells = <0>; 58 clock-frequency = <0>; 59 }; 60 61 main_xtal: main_xtal { 62 compatible = "fixed-clock"; 63 #clock-cells = <0>; 64 clock-frequency = <0>; 65 }; 66 67 adc_op_clk: adc_op_clk{ 68 compatible = "fixed-clock"; 69 #clock-cells = <0>; 70 clock-frequency = <300000>; 71 }; 72 }; 73 74 sram: sram@00300000 { 75 compatible = "mmio-sram"; 76 reg = <0x00300000 0x10000>; 77 }; 78 79 ahb { 80 compatible = "simple-bus"; 81 #address-cells = <1>; 82 #size-cells = <1>; 83 ranges; 84 u-boot,dm-pre-reloc; 85 86 apb { 87 compatible = "simple-bus"; 88 #address-cells = <1>; 89 #size-cells = <1>; 90 ranges; 91 u-boot,dm-pre-reloc; 92 93 aic: interrupt-controller@fffff000 { 94 #interrupt-cells = <3>; 95 compatible = "atmel,at91rm9200-aic"; 96 interrupt-controller; 97 reg = <0xfffff000 0x200>; 98 atmel,external-irqs = <31>; 99 }; 100 101 ramc0: ramc@ffffe400 { 102 compatible = "atmel,at91sam9g45-ddramc"; 103 reg = <0xffffe400 0x200>; 104 clocks = <&ddrck>; 105 clock-names = "ddrck"; 106 }; 107 108 ramc1: ramc@ffffe600 { 109 compatible = "atmel,at91sam9g45-ddramc"; 110 reg = <0xffffe600 0x200>; 111 clocks = <&ddrck>; 112 clock-names = "ddrck"; 113 }; 114 115 pmc: pmc@fffffc00 { 116 compatible = "atmel,at91sam9g45-pmc", "syscon"; 117 reg = <0xfffffc00 0x100>; 118 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 119 interrupt-controller; 120 #address-cells = <1>; 121 #size-cells = <0>; 122 #interrupt-cells = <1>; 123 u-boot,dm-pre-reloc; 124 125 main_osc: main_osc { 126 compatible = "atmel,at91rm9200-clk-main-osc"; 127 #clock-cells = <0>; 128 interrupts-extended = <&pmc AT91_PMC_MOSCS>; 129 clocks = <&main_xtal>; 130 }; 131 132 main: mainck { 133 compatible = "atmel,at91rm9200-clk-main"; 134 #clock-cells = <0>; 135 clocks = <&main_osc>; 136 }; 137 138 plla: pllack@0 { 139 compatible = "atmel,at91rm9200-clk-pll"; 140 #clock-cells = <0>; 141 interrupts-extended = <&pmc AT91_PMC_LOCKA>; 142 clocks = <&main>; 143 reg = <0>; 144 atmel,clk-input-range = <2000000 32000000>; 145 #atmel,pll-clk-output-range-cells = <4>; 146 atmel,pll-clk-output-ranges = <745000000 800000000 0 0 147 695000000 750000000 1 0 148 645000000 700000000 2 0 149 595000000 650000000 3 0 150 545000000 600000000 0 1 151 495000000 555000000 1 1 152 445000000 500000000 2 1 153 400000000 450000000 3 1>; 154 }; 155 156 plladiv: plladivck { 157 compatible = "atmel,at91sam9x5-clk-plldiv"; 158 #clock-cells = <0>; 159 clocks = <&plla>; 160 }; 161 162 utmi: utmick { 163 compatible = "atmel,at91sam9x5-clk-utmi"; 164 #clock-cells = <0>; 165 interrupts-extended = <&pmc AT91_PMC_LOCKU>; 166 clocks = <&main>; 167 }; 168 169 mck: masterck { 170 compatible = "atmel,at91rm9200-clk-master"; 171 #clock-cells = <0>; 172 interrupts-extended = <&pmc AT91_PMC_MCKRDY>; 173 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>; 174 atmel,clk-output-range = <0 133333333>; 175 atmel,clk-divisors = <1 2 4 3>; 176 u-boot,dm-pre-reloc; 177 }; 178 179 usb: usbck { 180 compatible = "atmel,at91sam9x5-clk-usb"; 181 #clock-cells = <0>; 182 clocks = <&plladiv>, <&utmi>; 183 }; 184 185 prog: progck { 186 compatible = "atmel,at91sam9g45-clk-programmable"; 187 #address-cells = <1>; 188 #size-cells = <0>; 189 interrupt-parent = <&pmc>; 190 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>; 191 192 prog0: prog@0 { 193 #clock-cells = <0>; 194 reg = <0>; 195 interrupts = <AT91_PMC_PCKRDY(0)>; 196 }; 197 198 prog1: prog@1 { 199 #clock-cells = <0>; 200 reg = <1>; 201 interrupts = <AT91_PMC_PCKRDY(1)>; 202 }; 203 }; 204 205 systemck { 206 compatible = "atmel,at91rm9200-clk-system"; 207 #address-cells = <1>; 208 #size-cells = <0>; 209 210 ddrck: ddrck@2 { 211 #clock-cells = <0>; 212 reg = <2>; 213 clocks = <&mck>; 214 }; 215 216 uhpck: uhpck@6 { 217 #clock-cells = <0>; 218 reg = <6>; 219 clocks = <&usb>; 220 }; 221 222 pck0: pck0@8 { 223 #clock-cells = <0>; 224 reg = <8>; 225 clocks = <&prog0>; 226 }; 227 228 pck1: pck1@9 { 229 #clock-cells = <0>; 230 reg = <9>; 231 clocks = <&prog1>; 232 }; 233 }; 234 235 periphck { 236 compatible = "atmel,at91rm9200-clk-peripheral"; 237 #address-cells = <1>; 238 #size-cells = <0>; 239 clocks = <&mck>; 240 241 pioA_clk: pioA_clk@2 { 242 #clock-cells = <0>; 243 reg = <2>; 244 }; 245 246 pioB_clk: pioB_clk@3 { 247 #clock-cells = <0>; 248 reg = <3>; 249 }; 250 251 pioC_clk: pioC_clk@4 { 252 #clock-cells = <0>; 253 reg = <4>; 254 }; 255 256 pioDE_clk: pioDE_clk@5 { 257 #clock-cells = <0>; 258 reg = <5>; 259 }; 260 261 trng_clk: trng_clk@6 { 262 #clock-cells = <0>; 263 reg = <6>; 264 }; 265 266 usart0_clk: usart0_clk@7 { 267 #clock-cells = <0>; 268 reg = <7>; 269 }; 270 271 usart1_clk: usart1_clk@8 { 272 #clock-cells = <0>; 273 reg = <8>; 274 }; 275 276 usart2_clk: usart2_clk@9 { 277 #clock-cells = <0>; 278 reg = <9>; 279 }; 280 281 usart3_clk: usart3_clk@10 { 282 #clock-cells = <0>; 283 reg = <10>; 284 }; 285 286 mci0_clk: mci0_clk@11 { 287 #clock-cells = <0>; 288 reg = <11>; 289 }; 290 291 twi0_clk: twi0_clk@12 { 292 #clock-cells = <0>; 293 reg = <12>; 294 }; 295 296 twi1_clk: twi1_clk@13 { 297 #clock-cells = <0>; 298 reg = <13>; 299 }; 300 301 spi0_clk: spi0_clk@14 { 302 #clock-cells = <0>; 303 reg = <14>; 304 }; 305 306 spi1_clk: spi1_clk@15 { 307 #clock-cells = <0>; 308 reg = <15>; 309 }; 310 311 ssc0_clk: ssc0_clk@16 { 312 #clock-cells = <0>; 313 reg = <16>; 314 }; 315 316 ssc1_clk: ssc1_clk@17 { 317 #clock-cells = <0>; 318 reg = <17>; 319 }; 320 321 tcb0_clk: tcb0_clk@18 { 322 #clock-cells = <0>; 323 reg = <18>; 324 }; 325 326 pwm_clk: pwm_clk@19 { 327 #clock-cells = <0>; 328 reg = <19>; 329 }; 330 331 adc_clk: adc_clk@20 { 332 #clock-cells = <0>; 333 reg = <20>; 334 }; 335 336 dma0_clk: dma0_clk@21 { 337 #clock-cells = <0>; 338 reg = <21>; 339 }; 340 341 uhphs_clk: uhphs_clk@22 { 342 #clock-cells = <0>; 343 reg = <22>; 344 }; 345 346 lcd_clk: lcd_clk@23 { 347 #clock-cells = <0>; 348 reg = <23>; 349 }; 350 351 ac97_clk: ac97_clk@24 { 352 #clock-cells = <0>; 353 reg = <24>; 354 }; 355 356 macb0_clk: macb0_clk@25 { 357 #clock-cells = <0>; 358 reg = <25>; 359 }; 360 361 isi_clk: isi_clk@26 { 362 #clock-cells = <0>; 363 reg = <26>; 364 }; 365 366 udphs_clk: udphs_clk@27 { 367 #clock-cells = <0>; 368 reg = <27>; 369 }; 370 371 aestdessha_clk: aestdessha_clk@28 { 372 #clock-cells = <0>; 373 reg = <28>; 374 }; 375 376 mci1_clk: mci1_clk@29 { 377 #clock-cells = <0>; 378 reg = <29>; 379 }; 380 381 vdec_clk: vdec_clk@30 { 382 #clock-cells = <0>; 383 reg = <30>; 384 }; 385 }; 386 }; 387 388 rstc@fffffd00 { 389 compatible = "atmel,at91sam9g45-rstc"; 390 reg = <0xfffffd00 0x10>; 391 clocks = <&clk32k>; 392 }; 393 394 pit: timer@fffffd30 { 395 compatible = "atmel,at91sam9260-pit"; 396 reg = <0xfffffd30 0xf>; 397 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 398 clocks = <&mck>; 399 }; 400 401 402 shdwc@fffffd10 { 403 compatible = "atmel,at91sam9rl-shdwc"; 404 reg = <0xfffffd10 0x10>; 405 clocks = <&clk32k>; 406 }; 407 408 tcb0: timer@fff7c000 { 409 compatible = "atmel,at91rm9200-tcb"; 410 reg = <0xfff7c000 0x100>; 411 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>; 412 clocks = <&tcb0_clk>, <&tcb0_clk>, <&tcb0_clk>, <&clk32k>; 413 clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; 414 }; 415 416 tcb1: timer@fffd4000 { 417 compatible = "atmel,at91rm9200-tcb"; 418 reg = <0xfffd4000 0x100>; 419 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>; 420 clocks = <&tcb0_clk>, <&tcb0_clk>, <&tcb0_clk>, <&clk32k>; 421 clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; 422 }; 423 424 dma: dma-controller@ffffec00 { 425 compatible = "atmel,at91sam9g45-dma"; 426 reg = <0xffffec00 0x200>; 427 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>; 428 #dma-cells = <2>; 429 clocks = <&dma0_clk>; 430 clock-names = "dma_clk"; 431 }; 432 433 pinctrl@fffff200 { 434 #address-cells = <1>; 435 #size-cells = <1>; 436 compatible = "atmel,at91rm9200-pinctrl", "simple-bus"; 437 ranges = <0xfffff200 0xfffff200 0xa00>; 438 reg = <0xfffff200 0x200 439 0xfffff400 0x200 440 0xfffff600 0x200 441 0xfffff800 0x200 442 0xfffffa00 0x200 443 >; 444 u-boot,dm-pre-reloc; 445 446 atmel,mux-mask = < 447 /* A B */ 448 0xffffffff 0xffc003ff /* pioA */ 449 0xffffffff 0x800f8f00 /* pioB */ 450 0xffffffff 0x00000e00 /* pioC */ 451 0xffffffff 0xff0c1381 /* pioD */ 452 0xffffffff 0x81ffff81 /* pioE */ 453 >; 454 455 /* shared pinctrl settings */ 456 adc0 { 457 pinctrl_adc0_adtrg: adc0_adtrg { 458 atmel,pins = <AT91_PIOD 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; 459 }; 460 pinctrl_adc0_ad0: adc0_ad0 { 461 atmel,pins = <AT91_PIOD 20 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; 462 }; 463 pinctrl_adc0_ad1: adc0_ad1 { 464 atmel,pins = <AT91_PIOD 21 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; 465 }; 466 pinctrl_adc0_ad2: adc0_ad2 { 467 atmel,pins = <AT91_PIOD 22 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; 468 }; 469 pinctrl_adc0_ad3: adc0_ad3 { 470 atmel,pins = <AT91_PIOD 23 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; 471 }; 472 pinctrl_adc0_ad4: adc0_ad4 { 473 atmel,pins = <AT91_PIOD 24 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; 474 }; 475 pinctrl_adc0_ad5: adc0_ad5 { 476 atmel,pins = <AT91_PIOD 25 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; 477 }; 478 pinctrl_adc0_ad6: adc0_ad6 { 479 atmel,pins = <AT91_PIOD 26 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; 480 }; 481 pinctrl_adc0_ad7: adc0_ad7 { 482 atmel,pins = <AT91_PIOD 27 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; 483 }; 484 }; 485 486 dbgu { 487 u-boot,dm-pre-reloc; 488 pinctrl_dbgu: dbgu-0 { 489 atmel,pins = 490 <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_PULL_UP 491 AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; 492 }; 493 }; 494 495 i2c0 { 496 pinctrl_i2c0: i2c0-0 { 497 atmel,pins = 498 <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA21 periph A TWCK0 */ 499 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA20 periph A TWD0 */ 500 }; 501 }; 502 503 i2c1 { 504 pinctrl_i2c1: i2c1-0 { 505 atmel,pins = 506 <AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A TWCK1 */ 507 AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A TWD1 */ 508 }; 509 }; 510 511 isi { 512 pinctrl_isi_data_0_7: isi-0-data-0-7 { 513 atmel,pins = 514 <AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* D0 */ 515 AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* D1 */ 516 AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* D2 */ 517 AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* D3 */ 518 AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* D4 */ 519 AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* D5 */ 520 AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* D6 */ 521 AT91_PIOB 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* D7 */ 522 AT91_PIOB 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PCK */ 523 AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* VSYNC */ 524 AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* HSYNC */ 525 }; 526 527 pinctrl_isi_data_8_9: isi-0-data-8-9 { 528 atmel,pins = 529 <AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE /* D8 */ 530 AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* D9 */ 531 }; 532 533 pinctrl_isi_data_10_11: isi-0-data-10-11 { 534 atmel,pins = 535 <AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* D10 */ 536 AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* D11 */ 537 }; 538 }; 539 540 usart0 { 541 pinctrl_usart0: usart0-0 { 542 atmel,pins = 543 <AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB19 periph A with pullup */ 544 AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB18 periph A */ 545 }; 546 547 pinctrl_usart0_rts: usart0_rts-0 { 548 atmel,pins = 549 <AT91_PIOB 17 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB17 periph B */ 550 }; 551 552 pinctrl_usart0_cts: usart0_cts-0 { 553 atmel,pins = 554 <AT91_PIOB 15 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB15 periph B */ 555 }; 556 }; 557 558 uart1 { 559 pinctrl_usart1: usart1-0 { 560 atmel,pins = 561 <AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB4 periph A with pullup */ 562 AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB5 periph A */ 563 }; 564 565 pinctrl_usart1_rts: usart1_rts-0 { 566 atmel,pins = 567 <AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD16 periph A */ 568 }; 569 570 pinctrl_usart1_cts: usart1_cts-0 { 571 atmel,pins = 572 <AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD17 periph A */ 573 }; 574 }; 575 576 usart2 { 577 pinctrl_usart2: usart2-0 { 578 atmel,pins = 579 <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB6 periph A with pullup */ 580 AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB7 periph A */ 581 }; 582 583 pinctrl_usart2_rts: usart2_rts-0 { 584 atmel,pins = 585 <AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC9 periph B */ 586 }; 587 588 pinctrl_usart2_cts: usart2_cts-0 { 589 atmel,pins = 590 <AT91_PIOC 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC11 periph B */ 591 }; 592 }; 593 594 usart3 { 595 pinctrl_usart3: usart3-0 { 596 atmel,pins = 597 <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB9 periph A with pullup */ 598 AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB8 periph A */ 599 }; 600 601 pinctrl_usart3_rts: usart3_rts-0 { 602 atmel,pins = 603 <AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA23 periph B */ 604 }; 605 606 pinctrl_usart3_cts: usart3_cts-0 { 607 atmel,pins = 608 <AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA24 periph B */ 609 }; 610 }; 611 612 nand { 613 pinctrl_nand: nand-0 { 614 atmel,pins = 615 <AT91_PIOC 8 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PC8 gpio RDY pin pull_up*/ 616 AT91_PIOC 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PC14 gpio enable pin pull_up */ 617 }; 618 }; 619 620 macb { 621 pinctrl_macb_rmii: macb_rmii-0 { 622 atmel,pins = 623 <AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA10 periph A */ 624 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A */ 625 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A */ 626 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA13 periph A */ 627 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA14 periph A */ 628 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA15 periph A */ 629 AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA16 periph A */ 630 AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA17 periph A */ 631 AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA18 periph A */ 632 AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA19 periph A */ 633 }; 634 635 pinctrl_macb_rmii_mii: macb_rmii_mii-0 { 636 atmel,pins = 637 <AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA6 periph B */ 638 AT91_PIOA 7 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA7 periph B */ 639 AT91_PIOA 8 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA8 periph B */ 640 AT91_PIOA 9 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA9 periph B */ 641 AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA27 periph B */ 642 AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA28 periph B */ 643 AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA29 periph B */ 644 AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA30 periph B */ 645 }; 646 }; 647 648 mmc0 { 649 pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 { 650 atmel,pins = 651 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA0 periph A */ 652 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA1 periph A with pullup */ 653 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA2 periph A with pullup */ 654 }; 655 656 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { 657 atmel,pins = 658 <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA3 periph A with pullup */ 659 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA4 periph A with pullup */ 660 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA5 periph A with pullup */ 661 }; 662 663 pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 { 664 atmel,pins = 665 <AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA6 periph A with pullup */ 666 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA7 periph A with pullup */ 667 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA8 periph A with pullup */ 668 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA9 periph A with pullup */ 669 }; 670 }; 671 672 mmc1 { 673 pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 { 674 atmel,pins = 675 <AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA31 periph A */ 676 AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA22 periph A with pullup */ 677 AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA23 periph A with pullup */ 678 }; 679 680 pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 { 681 atmel,pins = 682 <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA24 periph A with pullup */ 683 AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA25 periph A with pullup */ 684 AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA26 periph A with pullup */ 685 }; 686 687 pinctrl_mmc1_slot0_dat4_7: mmc1_slot0_dat4_7-0 { 688 atmel,pins = 689 <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA27 periph A with pullup */ 690 AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA28 periph A with pullup */ 691 AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA29 periph A with pullup */ 692 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA30 periph A with pullup */ 693 }; 694 }; 695 696 ssc0 { 697 pinctrl_ssc0_tx: ssc0_tx-0 { 698 atmel,pins = 699 <AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD0 periph A */ 700 AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD1 periph A */ 701 AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD2 periph A */ 702 }; 703 704 pinctrl_ssc0_rx: ssc0_rx-0 { 705 atmel,pins = 706 <AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD3 periph A */ 707 AT91_PIOD 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD4 periph A */ 708 AT91_PIOD 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD5 periph A */ 709 }; 710 }; 711 712 ssc1 { 713 pinctrl_ssc1_tx: ssc1_tx-0 { 714 atmel,pins = 715 <AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD10 periph A */ 716 AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD11 periph A */ 717 AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD12 periph A */ 718 }; 719 720 pinctrl_ssc1_rx: ssc1_rx-0 { 721 atmel,pins = 722 <AT91_PIOD 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD13 periph A */ 723 AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD14 periph A */ 724 AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD15 periph A */ 725 }; 726 }; 727 728 spi0 { 729 pinctrl_spi0: spi0-0 { 730 atmel,pins = 731 <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A SPI0_MISO pin */ 732 AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A SPI0_MOSI pin */ 733 AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB2 periph A SPI0_SPCK pin */ 734 }; 735 }; 736 737 spi1 { 738 pinctrl_spi1: spi1-0 { 739 atmel,pins = 740 <AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A SPI1_MISO pin */ 741 AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB15 periph A SPI1_MOSI pin */ 742 AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB16 periph A SPI1_SPCK pin */ 743 }; 744 }; 745 746 tcb0 { 747 pinctrl_tcb0_tclk0: tcb0_tclk0-0 { 748 atmel,pins = <AT91_PIOD 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; 749 }; 750 751 pinctrl_tcb0_tclk1: tcb0_tclk1-0 { 752 atmel,pins = <AT91_PIOD 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; 753 }; 754 755 pinctrl_tcb0_tclk2: tcb0_tclk2-0 { 756 atmel,pins = <AT91_PIOC 10 AT91_PERIPH_B AT91_PINCTRL_NONE>; 757 }; 758 759 pinctrl_tcb0_tioa0: tcb0_tioa0-0 { 760 atmel,pins = <AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; 761 }; 762 763 pinctrl_tcb0_tioa1: tcb0_tioa1-0 { 764 atmel,pins = <AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; 765 }; 766 767 pinctrl_tcb0_tioa2: tcb0_tioa2-0 { 768 atmel,pins = <AT91_PIOD 22 AT91_PERIPH_A AT91_PINCTRL_NONE>; 769 }; 770 771 pinctrl_tcb0_tiob0: tcb0_tiob0-0 { 772 atmel,pins = <AT91_PIOD 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; 773 }; 774 775 pinctrl_tcb0_tiob1: tcb0_tiob1-0 { 776 atmel,pins = <AT91_PIOD 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; 777 }; 778 779 pinctrl_tcb0_tiob2: tcb0_tiob2-0 { 780 atmel,pins = <AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; 781 }; 782 }; 783 784 tcb1 { 785 pinctrl_tcb1_tclk0: tcb1_tclk0-0 { 786 atmel,pins = <AT91_PIOA 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; 787 }; 788 789 pinctrl_tcb1_tclk1: tcb1_tclk1-0 { 790 atmel,pins = <AT91_PIOA 3 AT91_PERIPH_B AT91_PINCTRL_NONE>; 791 }; 792 793 pinctrl_tcb1_tclk2: tcb1_tclk2-0 { 794 atmel,pins = <AT91_PIOD 9 AT91_PERIPH_B AT91_PINCTRL_NONE>; 795 }; 796 797 pinctrl_tcb1_tioa0: tcb1_tioa0-0 { 798 atmel,pins = <AT91_PIOA 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; 799 }; 800 801 pinctrl_tcb1_tioa1: tcb1_tioa1-0 { 802 atmel,pins = <AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_NONE>; 803 }; 804 805 pinctrl_tcb1_tioa2: tcb1_tioa2-0 { 806 atmel,pins = <AT91_PIOD 7 AT91_PERIPH_B AT91_PINCTRL_NONE>; 807 }; 808 809 pinctrl_tcb1_tiob0: tcb1_tiob0-0 { 810 atmel,pins = <AT91_PIOA 2 AT91_PERIPH_B AT91_PINCTRL_NONE>; 811 }; 812 813 pinctrl_tcb1_tiob1: tcb1_tiob1-0 { 814 atmel,pins = <AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_NONE>; 815 }; 816 817 pinctrl_tcb1_tiob2: tcb1_tiob2-0 { 818 atmel,pins = <AT91_PIOD 8 AT91_PERIPH_B AT91_PINCTRL_NONE>; 819 }; 820 }; 821 822 fb { 823 pinctrl_fb: fb-0 { 824 atmel,pins = 825 <AT91_PIOE 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE0 periph A */ 826 AT91_PIOE 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE2 periph A */ 827 AT91_PIOE 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE3 periph A */ 828 AT91_PIOE 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE4 periph A */ 829 AT91_PIOE 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE5 periph A */ 830 AT91_PIOE 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE6 periph A */ 831 AT91_PIOE 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE7 periph A */ 832 AT91_PIOE 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE8 periph A */ 833 AT91_PIOE 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE9 periph A */ 834 AT91_PIOE 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE10 periph A */ 835 AT91_PIOE 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE11 periph A */ 836 AT91_PIOE 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE12 periph A */ 837 AT91_PIOE 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE13 periph A */ 838 AT91_PIOE 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE14 periph A */ 839 AT91_PIOE 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE15 periph A */ 840 AT91_PIOE 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE16 periph A */ 841 AT91_PIOE 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE17 periph A */ 842 AT91_PIOE 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE18 periph A */ 843 AT91_PIOE 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE19 periph A */ 844 AT91_PIOE 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE20 periph A */ 845 AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE21 periph A */ 846 AT91_PIOE 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE22 periph A */ 847 AT91_PIOE 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE23 periph A */ 848 AT91_PIOE 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE24 periph A */ 849 AT91_PIOE 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE25 periph A */ 850 AT91_PIOE 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE26 periph A */ 851 AT91_PIOE 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE27 periph A */ 852 AT91_PIOE 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE28 periph A */ 853 AT91_PIOE 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE29 periph A */ 854 AT91_PIOE 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PE30 periph A */ 855 }; 856 }; 857 }; 858 859 pioA: gpio@fffff200 { 860 compatible = "atmel,at91rm9200-gpio"; 861 reg = <0xfffff200 0x200>; 862 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; 863 #gpio-cells = <2>; 864 gpio-controller; 865 interrupt-controller; 866 #interrupt-cells = <2>; 867 clocks = <&pioA_clk>; 868 }; 869 870 pioB: gpio@fffff400 { 871 compatible = "atmel,at91rm9200-gpio"; 872 reg = <0xfffff400 0x200>; 873 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; 874 #gpio-cells = <2>; 875 gpio-controller; 876 interrupt-controller; 877 #interrupt-cells = <2>; 878 clocks = <&pioB_clk>; 879 }; 880 881 pioC: gpio@fffff600 { 882 compatible = "atmel,at91rm9200-gpio"; 883 reg = <0xfffff600 0x200>; 884 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; 885 #gpio-cells = <2>; 886 gpio-controller; 887 interrupt-controller; 888 #interrupt-cells = <2>; 889 clocks = <&pioC_clk>; 890 }; 891 892 pioD: gpio@fffff800 { 893 compatible = "atmel,at91rm9200-gpio"; 894 reg = <0xfffff800 0x200>; 895 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>; 896 #gpio-cells = <2>; 897 gpio-controller; 898 interrupt-controller; 899 #interrupt-cells = <2>; 900 clocks = <&pioDE_clk>; 901 }; 902 903 pioE: gpio@fffffa00 { 904 compatible = "atmel,at91rm9200-gpio"; 905 reg = <0xfffffa00 0x200>; 906 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>; 907 #gpio-cells = <2>; 908 gpio-controller; 909 interrupt-controller; 910 #interrupt-cells = <2>; 911 clocks = <&pioDE_clk>; 912 }; 913 914 dbgu: serial@ffffee00 { 915 compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; 916 reg = <0xffffee00 0x200>; 917 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 918 pinctrl-names = "default"; 919 pinctrl-0 = <&pinctrl_dbgu>; 920 clocks = <&mck>; 921 clock-names = "usart"; 922 status = "disabled"; 923 }; 924 925 usart0: serial@fff8c000 { 926 compatible = "atmel,at91sam9260-usart"; 927 reg = <0xfff8c000 0x200>; 928 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; 929 atmel,use-dma-rx; 930 atmel,use-dma-tx; 931 pinctrl-names = "default"; 932 pinctrl-0 = <&pinctrl_usart0>; 933 clocks = <&usart0_clk>; 934 clock-names = "usart"; 935 status = "disabled"; 936 }; 937 938 usart1: serial@fff90000 { 939 compatible = "atmel,at91sam9260-usart"; 940 reg = <0xfff90000 0x200>; 941 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; 942 atmel,use-dma-rx; 943 atmel,use-dma-tx; 944 pinctrl-names = "default"; 945 pinctrl-0 = <&pinctrl_usart1>; 946 clocks = <&usart1_clk>; 947 clock-names = "usart"; 948 status = "disabled"; 949 }; 950 951 usart2: serial@fff94000 { 952 compatible = "atmel,at91sam9260-usart"; 953 reg = <0xfff94000 0x200>; 954 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 5>; 955 atmel,use-dma-rx; 956 atmel,use-dma-tx; 957 pinctrl-names = "default"; 958 pinctrl-0 = <&pinctrl_usart2>; 959 clocks = <&usart2_clk>; 960 clock-names = "usart"; 961 status = "disabled"; 962 }; 963 964 usart3: serial@fff98000 { 965 compatible = "atmel,at91sam9260-usart"; 966 reg = <0xfff98000 0x200>; 967 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 5>; 968 atmel,use-dma-rx; 969 atmel,use-dma-tx; 970 pinctrl-names = "default"; 971 pinctrl-0 = <&pinctrl_usart3>; 972 clocks = <&usart3_clk>; 973 clock-names = "usart"; 974 status = "disabled"; 975 }; 976 977 macb0: ethernet@fffbc000 { 978 compatible = "cdns,at91sam9260-macb", "cdns,macb"; 979 reg = <0xfffbc000 0x100>; 980 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 3>; 981 pinctrl-names = "default"; 982 pinctrl-0 = <&pinctrl_macb_rmii>; 983 clocks = <&macb0_clk>, <&macb0_clk>; 984 clock-names = "hclk", "pclk"; 985 status = "disabled"; 986 }; 987 988 trng@fffcc000 { 989 compatible = "atmel,at91sam9g45-trng"; 990 reg = <0xfffcc000 0x100>; 991 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>; 992 clocks = <&trng_clk>; 993 }; 994 995 i2c0: i2c@fff84000 { 996 compatible = "atmel,at91sam9g10-i2c"; 997 reg = <0xfff84000 0x100>; 998 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>; 999 pinctrl-names = "default"; 1000 pinctrl-0 = <&pinctrl_i2c0>; 1001 #address-cells = <1>; 1002 #size-cells = <0>; 1003 clocks = <&twi0_clk>; 1004 status = "disabled"; 1005 }; 1006 1007 i2c1: i2c@fff88000 { 1008 compatible = "atmel,at91sam9g10-i2c"; 1009 reg = <0xfff88000 0x100>; 1010 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 6>; 1011 pinctrl-names = "default"; 1012 pinctrl-0 = <&pinctrl_i2c1>; 1013 #address-cells = <1>; 1014 #size-cells = <0>; 1015 clocks = <&twi1_clk>; 1016 status = "disabled"; 1017 }; 1018 1019 ssc0: ssc@fff9c000 { 1020 compatible = "atmel,at91sam9g45-ssc"; 1021 reg = <0xfff9c000 0x4000>; 1022 interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; 1023 pinctrl-names = "default"; 1024 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; 1025 clocks = <&ssc0_clk>; 1026 clock-names = "pclk"; 1027 status = "disabled"; 1028 }; 1029 1030 ssc1: ssc@fffa0000 { 1031 compatible = "atmel,at91sam9g45-ssc"; 1032 reg = <0xfffa0000 0x4000>; 1033 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>; 1034 pinctrl-names = "default"; 1035 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; 1036 clocks = <&ssc1_clk>; 1037 clock-names = "pclk"; 1038 status = "disabled"; 1039 }; 1040 1041 adc0: adc@fffb0000 { 1042 compatible = "atmel,at91sam9g45-adc"; 1043 reg = <0xfffb0000 0x100>; 1044 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; 1045 clocks = <&adc_clk>, <&adc_op_clk>; 1046 clock-names = "adc_clk", "adc_op_clk"; 1047 atmel,adc-channels-used = <0xff>; 1048 atmel,adc-vref = <3300>; 1049 atmel,adc-startup-time = <40>; 1050 atmel,adc-res = <8 10>; 1051 atmel,adc-res-names = "lowres", "highres"; 1052 atmel,adc-use-res = "highres"; 1053 1054 trigger0 { 1055 trigger-name = "external-rising"; 1056 trigger-value = <0x1>; 1057 trigger-external; 1058 }; 1059 trigger1 { 1060 trigger-name = "external-falling"; 1061 trigger-value = <0x2>; 1062 trigger-external; 1063 }; 1064 1065 trigger2 { 1066 trigger-name = "external-any"; 1067 trigger-value = <0x3>; 1068 trigger-external; 1069 }; 1070 1071 trigger3 { 1072 trigger-name = "continuous"; 1073 trigger-value = <0x6>; 1074 }; 1075 }; 1076 1077 isi@fffb4000 { 1078 compatible = "atmel,at91sam9g45-isi"; 1079 reg = <0xfffb4000 0x4000>; 1080 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 5>; 1081 clocks = <&isi_clk>; 1082 clock-names = "isi_clk"; 1083 status = "disabled"; 1084 }; 1085 1086 pwm0: pwm@fffb8000 { 1087 compatible = "atmel,at91sam9rl-pwm"; 1088 reg = <0xfffb8000 0x300>; 1089 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 4>; 1090 #pwm-cells = <3>; 1091 clocks = <&pwm_clk>; 1092 status = "disabled"; 1093 }; 1094 1095 mmc0: mmc@fff80000 { 1096 compatible = "atmel,hsmci"; 1097 reg = <0xfff80000 0x600>; 1098 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>; 1099 pinctrl-names = "default"; 1100 dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>; 1101 dma-names = "rxtx"; 1102 #address-cells = <1>; 1103 #size-cells = <0>; 1104 clocks = <&mci0_clk>; 1105 clock-names = "mci_clk"; 1106 status = "disabled"; 1107 }; 1108 1109 mmc1: mmc@fffd0000 { 1110 compatible = "atmel,hsmci"; 1111 reg = <0xfffd0000 0x600>; 1112 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 0>; 1113 pinctrl-names = "default"; 1114 dmas = <&dma 1 AT91_DMA_CFG_PER_ID(13)>; 1115 dma-names = "rxtx"; 1116 #address-cells = <1>; 1117 #size-cells = <0>; 1118 clocks = <&mci1_clk>; 1119 clock-names = "mci_clk"; 1120 status = "disabled"; 1121 }; 1122 1123 watchdog@fffffd40 { 1124 compatible = "atmel,at91sam9260-wdt"; 1125 reg = <0xfffffd40 0x10>; 1126 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 1127 clocks = <&clk32k>; 1128 atmel,watchdog-type = "hardware"; 1129 atmel,reset-type = "all"; 1130 atmel,dbg-halt; 1131 status = "disabled"; 1132 }; 1133 1134 spi0: spi@fffa4000 { 1135 #address-cells = <1>; 1136 #size-cells = <0>; 1137 compatible = "atmel,at91rm9200-spi"; 1138 reg = <0xfffa4000 0x200>; 1139 interrupts = <14 4 3>; 1140 pinctrl-names = "default"; 1141 pinctrl-0 = <&pinctrl_spi0>; 1142 clocks = <&spi0_clk>; 1143 clock-names = "spi_clk"; 1144 status = "disabled"; 1145 }; 1146 1147 spi1: spi@fffa8000 { 1148 #address-cells = <1>; 1149 #size-cells = <0>; 1150 compatible = "atmel,at91rm9200-spi"; 1151 reg = <0xfffa8000 0x200>; 1152 interrupts = <15 4 3>; 1153 pinctrl-names = "default"; 1154 pinctrl-0 = <&pinctrl_spi1>; 1155 clocks = <&spi1_clk>; 1156 clock-names = "spi_clk"; 1157 status = "disabled"; 1158 }; 1159 1160 usb2: gadget@fff78000 { 1161 #address-cells = <1>; 1162 #size-cells = <0>; 1163 compatible = "atmel,at91sam9g45-udc"; 1164 reg = <0x00600000 0x80000 1165 0xfff78000 0x400>; 1166 interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>; 1167 clocks = <&udphs_clk>, <&utmi>; 1168 clock-names = "pclk", "hclk"; 1169 status = "disabled"; 1170 1171 ep@0 { 1172 reg = <0>; 1173 atmel,fifo-size = <64>; 1174 atmel,nb-banks = <1>; 1175 }; 1176 1177 ep@1 { 1178 reg = <1>; 1179 atmel,fifo-size = <1024>; 1180 atmel,nb-banks = <2>; 1181 atmel,can-dma; 1182 atmel,can-isoc; 1183 }; 1184 1185 ep@2 { 1186 reg = <2>; 1187 atmel,fifo-size = <1024>; 1188 atmel,nb-banks = <2>; 1189 atmel,can-dma; 1190 atmel,can-isoc; 1191 }; 1192 1193 ep@3 { 1194 reg = <3>; 1195 atmel,fifo-size = <1024>; 1196 atmel,nb-banks = <3>; 1197 atmel,can-dma; 1198 }; 1199 1200 ep@4 { 1201 reg = <4>; 1202 atmel,fifo-size = <1024>; 1203 atmel,nb-banks = <3>; 1204 atmel,can-dma; 1205 }; 1206 1207 ep@5 { 1208 reg = <5>; 1209 atmel,fifo-size = <1024>; 1210 atmel,nb-banks = <3>; 1211 atmel,can-dma; 1212 atmel,can-isoc; 1213 }; 1214 1215 ep@6 { 1216 reg = <6>; 1217 atmel,fifo-size = <1024>; 1218 atmel,nb-banks = <3>; 1219 atmel,can-dma; 1220 atmel,can-isoc; 1221 }; 1222 }; 1223 1224 sckc@fffffd50 { 1225 compatible = "atmel,at91sam9x5-sckc"; 1226 reg = <0xfffffd50 0x4>; 1227 1228 slow_osc: slow_osc { 1229 compatible = "atmel,at91sam9x5-clk-slow-osc"; 1230 #clock-cells = <0>; 1231 atmel,startup-time-usec = <1200000>; 1232 clocks = <&slow_xtal>; 1233 }; 1234 1235 slow_rc_osc: slow_rc_osc { 1236 compatible = "atmel,at91sam9x5-clk-slow-rc-osc"; 1237 #clock-cells = <0>; 1238 atmel,startup-time-usec = <75>; 1239 clock-frequency = <32768>; 1240 clock-accuracy = <50000000>; 1241 }; 1242 1243 clk32k: slck { 1244 compatible = "atmel,at91sam9x5-clk-slow"; 1245 #clock-cells = <0>; 1246 clocks = <&slow_rc_osc &slow_osc>; 1247 }; 1248 }; 1249 1250 rtc@fffffd20 { 1251 compatible = "atmel,at91sam9260-rtt"; 1252 reg = <0xfffffd20 0x10>; 1253 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 1254 clocks = <&clk32k>; 1255 status = "disabled"; 1256 }; 1257 1258 rtc@fffffdb0 { 1259 compatible = "atmel,at91rm9200-rtc"; 1260 reg = <0xfffffdb0 0x30>; 1261 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 1262 clocks = <&clk32k>; 1263 status = "disabled"; 1264 }; 1265 1266 gpbr: syscon@fffffd60 { 1267 compatible = "atmel,at91sam9260-gpbr", "syscon"; 1268 reg = <0xfffffd60 0x10>; 1269 status = "disabled"; 1270 }; 1271 }; 1272 1273 fb0: fb@0x00500000 { 1274 compatible = "atmel,at91sam9g45-lcdc"; 1275 reg = <0x00500000 0x1000>; 1276 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 3>; 1277 pinctrl-names = "default"; 1278 pinctrl-0 = <&pinctrl_fb>; 1279 clocks = <&lcd_clk>, <&lcd_clk>; 1280 clock-names = "hclk", "lcdc_clk"; 1281 status = "disabled"; 1282 }; 1283 1284 nand0: nand@40000000 { 1285 compatible = "atmel,at91rm9200-nand"; 1286 #address-cells = <1>; 1287 #size-cells = <1>; 1288 reg = <0x40000000 0x10000000 1289 0xffffe200 0x200 1290 >; 1291 atmel,nand-addr-offset = <21>; 1292 atmel,nand-cmd-offset = <22>; 1293 atmel,nand-has-dma; 1294 pinctrl-names = "default"; 1295 pinctrl-0 = <&pinctrl_nand>; 1296 gpios = <&pioC 8 GPIO_ACTIVE_HIGH 1297 &pioC 14 GPIO_ACTIVE_HIGH 1298 0 1299 >; 1300 status = "disabled"; 1301 }; 1302 1303 usb0: ohci@00700000 { 1304 compatible = "atmel,at91rm9200-ohci", "usb-ohci"; 1305 reg = <0x00700000 0x100000>; 1306 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; 1307 clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>; 1308 clock-names = "ohci_clk", "hclk", "uhpck"; 1309 status = "disabled"; 1310 }; 1311 1312 usb1: ehci@00800000 { 1313 compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; 1314 reg = <0x00800000 0x100000>; 1315 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; 1316 clocks = <&utmi>, <&uhphs_clk>; 1317 clock-names = "usb_clk", "ehci_clk"; 1318 status = "disabled"; 1319 }; 1320 }; 1321 1322 i2c-gpio-0 { 1323 compatible = "i2c-gpio"; 1324 gpios = <&pioA 20 GPIO_ACTIVE_HIGH /* sda */ 1325 &pioA 21 GPIO_ACTIVE_HIGH /* scl */ 1326 >; 1327 i2c-gpio,sda-open-drain; 1328 i2c-gpio,scl-open-drain; 1329 i2c-gpio,delay-us = <5>; /* ~100 kHz */ 1330 #address-cells = <1>; 1331 #size-cells = <0>; 1332 status = "disabled"; 1333 }; 1334}; 1335