1/* 2 * at91sam9263.dtsi - Device Tree Include file for AT91SAM9263 family SoC 3 * 4 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> 5 * 6 * Licensed under GPLv2 only. 7 */ 8 9#include "skeleton.dtsi" 10#include <dt-bindings/pinctrl/at91.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/clock/at91.h> 14 15/ { 16 model = "Atmel AT91SAM9263 family SoC"; 17 compatible = "atmel,at91sam9263"; 18 interrupt-parent = <&aic>; 19 20 aliases { 21 serial0 = &dbgu; 22 serial1 = &usart0; 23 serial2 = &usart1; 24 serial3 = &usart2; 25 gpio0 = &pioA; 26 gpio1 = &pioB; 27 gpio2 = &pioC; 28 gpio3 = &pioD; 29 gpio4 = &pioE; 30 tcb0 = &tcb0; 31 i2c0 = &i2c0; 32 ssc0 = &ssc0; 33 ssc1 = &ssc1; 34 pwm0 = &pwm0; 35 spi0 = &spi0; 36 }; 37 38 cpus { 39 #address-cells = <0>; 40 #size-cells = <0>; 41 42 cpu { 43 compatible = "arm,arm926ej-s"; 44 device_type = "cpu"; 45 }; 46 }; 47 48 memory { 49 reg = <0x20000000 0x08000000>; 50 }; 51 52 clocks { 53 main_xtal: main_xtal { 54 compatible = "fixed-clock"; 55 #clock-cells = <0>; 56 clock-frequency = <0>; 57 }; 58 59 slow_xtal: slow_xtal { 60 compatible = "fixed-clock"; 61 #clock-cells = <0>; 62 clock-frequency = <0>; 63 }; 64 }; 65 66 sram0: sram@00300000 { 67 compatible = "mmio-sram"; 68 reg = <0x00300000 0x14000>; 69 }; 70 71 sram1: sram@00500000 { 72 compatible = "mmio-sram"; 73 reg = <0x00500000 0x4000>; 74 }; 75 76 ahb { 77 compatible = "simple-bus"; 78 #address-cells = <1>; 79 #size-cells = <1>; 80 ranges; 81 u-boot,dm-pre-reloc; 82 83 apb { 84 compatible = "simple-bus"; 85 #address-cells = <1>; 86 #size-cells = <1>; 87 ranges; 88 u-boot,dm-pre-reloc; 89 90 aic: interrupt-controller@fffff000 { 91 #interrupt-cells = <3>; 92 compatible = "atmel,at91rm9200-aic"; 93 interrupt-controller; 94 reg = <0xfffff000 0x200>; 95 atmel,external-irqs = <30 31>; 96 }; 97 98 pmc: pmc@fffffc00 { 99 compatible = "atmel,at91rm9200-pmc", "syscon"; 100 reg = <0xfffffc00 0x100>; 101 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 102 interrupt-controller; 103 #address-cells = <1>; 104 #size-cells = <0>; 105 #interrupt-cells = <1>; 106 u-boot,dm-pre-reloc; 107 108 main_osc: main_osc { 109 compatible = "atmel,at91rm9200-clk-main-osc"; 110 #clock-cells = <0>; 111 interrupts-extended = <&pmc AT91_PMC_MOSCS>; 112 clocks = <&main_xtal>; 113 }; 114 115 main: mainck { 116 compatible = "atmel,at91rm9200-clk-main"; 117 #clock-cells = <0>; 118 clocks = <&main_osc>; 119 }; 120 121 plla: pllack@0 { 122 compatible = "atmel,at91rm9200-clk-pll"; 123 #clock-cells = <0>; 124 interrupts-extended = <&pmc AT91_PMC_LOCKA>; 125 clocks = <&main>; 126 reg = <0>; 127 atmel,clk-input-range = <1000000 32000000>; 128 #atmel,pll-clk-output-range-cells = <4>; 129 atmel,pll-clk-output-ranges = <80000000 200000000 0 1>, 130 <190000000 240000000 2 1>; 131 }; 132 133 pllb: pllbck@1 { 134 compatible = "atmel,at91rm9200-clk-pll"; 135 #clock-cells = <0>; 136 interrupts-extended = <&pmc AT91_PMC_LOCKB>; 137 clocks = <&main>; 138 reg = <1>; 139 atmel,clk-input-range = <1000000 32000000>; 140 #atmel,pll-clk-output-range-cells = <4>; 141 atmel,pll-clk-output-ranges = <80000000 200000000 0 1>, 142 <190000000 240000000 2 1>; 143 }; 144 145 mck: masterck { 146 compatible = "atmel,at91rm9200-clk-master"; 147 #clock-cells = <0>; 148 interrupts-extended = <&pmc AT91_PMC_MCKRDY>; 149 clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>; 150 atmel,clk-output-range = <0 120000000>; 151 atmel,clk-divisors = <1 2 4 0>; 152 u-boot,dm-pre-reloc; 153 }; 154 155 usb: usbck { 156 compatible = "atmel,at91rm9200-clk-usb"; 157 #clock-cells = <0>; 158 atmel,clk-divisors = <1 2 4 0>; 159 clocks = <&pllb>; 160 }; 161 162 prog: progck { 163 compatible = "atmel,at91rm9200-clk-programmable"; 164 #address-cells = <1>; 165 #size-cells = <0>; 166 interrupt-parent = <&pmc>; 167 clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>; 168 169 prog0: prog@0 { 170 #clock-cells = <0>; 171 reg = <0>; 172 interrupts = <AT91_PMC_PCKRDY(0)>; 173 }; 174 175 prog1: prog@1 { 176 #clock-cells = <0>; 177 reg = <1>; 178 interrupts = <AT91_PMC_PCKRDY(1)>; 179 }; 180 181 prog2: prog@2 { 182 #clock-cells = <0>; 183 reg = <2>; 184 interrupts = <AT91_PMC_PCKRDY(2)>; 185 }; 186 187 prog3: prog@3 { 188 #clock-cells = <0>; 189 reg = <3>; 190 interrupts = <AT91_PMC_PCKRDY(3)>; 191 }; 192 }; 193 194 systemck { 195 compatible = "atmel,at91rm9200-clk-system"; 196 #address-cells = <1>; 197 #size-cells = <0>; 198 199 uhpck: uhpck@6 { 200 #clock-cells = <0>; 201 reg = <6>; 202 clocks = <&usb>; 203 }; 204 205 udpck: udpck@7 { 206 #clock-cells = <0>; 207 reg = <7>; 208 clocks = <&usb>; 209 }; 210 211 pck0: pck0@8 { 212 #clock-cells = <0>; 213 reg = <8>; 214 clocks = <&prog0>; 215 }; 216 217 pck1: pck1@9 { 218 #clock-cells = <0>; 219 reg = <9>; 220 clocks = <&prog1>; 221 }; 222 223 pck2: pck2@10 { 224 #clock-cells = <0>; 225 reg = <10>; 226 clocks = <&prog2>; 227 }; 228 229 pck3: pck3@11 { 230 #clock-cells = <0>; 231 reg = <11>; 232 clocks = <&prog3>; 233 }; 234 }; 235 236 periphck { 237 compatible = "atmel,at91rm9200-clk-peripheral"; 238 #address-cells = <1>; 239 #size-cells = <0>; 240 clocks = <&mck>; 241 u-boot,dm-pre-reloc; 242 243 pioA_clk: pioA_clk@2 { 244 #clock-cells = <0>; 245 reg = <2>; 246 u-boot,dm-pre-reloc; 247 }; 248 249 pioB_clk: pioB_clk@3 { 250 #clock-cells = <0>; 251 reg = <3>; 252 u-boot,dm-pre-reloc; 253 }; 254 255 pioCDE_clk: pioCDE_clk@4 { 256 #clock-cells = <0>; 257 reg = <4>; 258 u-boot,dm-pre-reloc; 259 }; 260 261 usart0_clk: usart0_clk@7 { 262 #clock-cells = <0>; 263 reg = <7>; 264 }; 265 266 usart1_clk: usart1_clk@8 { 267 #clock-cells = <0>; 268 reg = <8>; 269 }; 270 271 usart2_clk: usart2_clk@9 { 272 #clock-cells = <0>; 273 reg = <9>; 274 }; 275 276 mci0_clk: mci0_clk@10 { 277 #clock-cells = <0>; 278 reg = <10>; 279 }; 280 281 mci1_clk: mci1_clk@11 { 282 #clock-cells = <0>; 283 reg = <11>; 284 }; 285 286 can_clk: can_clk@12 { 287 #clock-cells = <0>; 288 reg = <12>; 289 }; 290 291 twi0_clk: twi0_clk@13 { 292 #clock-cells = <0>; 293 reg = <13>; 294 }; 295 296 spi0_clk: spi0_clk@14 { 297 #clock-cells = <0>; 298 reg = <14>; 299 }; 300 301 spi1_clk: spi1_clk@15 { 302 #clock-cells = <0>; 303 reg = <15>; 304 }; 305 306 ssc0_clk: ssc0_clk@16 { 307 #clock-cells = <0>; 308 reg = <16>; 309 }; 310 311 ssc1_clk: ssc1_clk@17 { 312 #clock-cells = <0>; 313 reg = <17>; 314 }; 315 316 ac97_clk: ac97_clk@18 { 317 #clock-cells = <0>; 318 reg = <18>; 319 }; 320 321 tcb_clk: tcb_clk@19 { 322 #clock-cells = <0>; 323 reg = <19>; 324 }; 325 326 pwm_clk: pwm_clk@20 { 327 #clock-cells = <0>; 328 reg = <20>; 329 }; 330 331 macb0_clk: macb0_clk@21 { 332 #clock-cells = <0>; 333 reg = <21>; 334 }; 335 336 g2de_clk: g2de_clk@23 { 337 #clock-cells = <0>; 338 reg = <23>; 339 }; 340 341 udc_clk: udc_clk@24 { 342 #clock-cells = <0>; 343 reg = <24>; 344 }; 345 346 isi_clk: isi_clk@25 { 347 #clock-cells = <0>; 348 reg = <25>; 349 }; 350 351 lcd_clk: lcd_clk@26 { 352 #clock-cells = <0>; 353 reg = <26>; 354 }; 355 356 dma_clk: dma_clk@27 { 357 #clock-cells = <0>; 358 reg = <27>; 359 }; 360 361 ohci_clk: ohci_clk@29 { 362 #clock-cells = <0>; 363 reg = <29>; 364 }; 365 }; 366 }; 367 368 ramc0: ramc@ffffe200 { 369 compatible = "atmel,at91sam9260-sdramc"; 370 reg = <0xffffe200 0x200>; 371 }; 372 373 ramc1: ramc@ffffe800 { 374 compatible = "atmel,at91sam9260-sdramc"; 375 reg = <0xffffe800 0x200>; 376 }; 377 378 pit: timer@fffffd30 { 379 compatible = "atmel,at91sam9260-pit"; 380 reg = <0xfffffd30 0xf>; 381 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 382 clocks = <&mck>; 383 }; 384 385 tcb0: timer@fff7c000 { 386 compatible = "atmel,at91rm9200-tcb"; 387 reg = <0xfff7c000 0x100>; 388 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>; 389 clocks = <&tcb_clk>, <&slow_xtal>; 390 clock-names = "t0_clk", "slow_clk"; 391 }; 392 393 rstc@fffffd00 { 394 compatible = "atmel,at91sam9260-rstc"; 395 reg = <0xfffffd00 0x10>; 396 clocks = <&slow_xtal>; 397 }; 398 399 shdwc@fffffd10 { 400 compatible = "atmel,at91sam9260-shdwc"; 401 reg = <0xfffffd10 0x10>; 402 clocks = <&slow_xtal>; 403 }; 404 405 pinctrl@fffff200 { 406 #address-cells = <1>; 407 #size-cells = <1>; 408 compatible = "atmel,at91rm9200-pinctrl", "simple-bus"; 409 ranges = <0xfffff200 0xfffff200 0xa00>; 410 reg = <0xfffff200 0x200 411 0xfffff400 0x200 412 0xfffff600 0x200 413 0xfffff800 0x200 414 0xfffffa00 0x200 415 >; 416 417 atmel,mux-mask = < 418 /* A B */ 419 0xfffffffb 0xffffe07f /* pioA */ 420 0x0007ffff 0x39072fff /* pioB */ 421 0xffffffff 0x3ffffff8 /* pioC */ 422 0xfffffbff 0xffffffff /* pioD */ 423 0xffe00fff 0xfbfcff00 /* pioE */ 424 >; 425 426 /* shared pinctrl settings */ 427 dbgu { 428 pinctrl_dbgu: dbgu-0 { 429 atmel,pins = 430 <AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP 431 AT91_PIOC 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; 432 }; 433 }; 434 435 usart0 { 436 pinctrl_usart0: usart0-0 { 437 atmel,pins = 438 <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA26 periph A with pullup */ 439 AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA27 periph A */ 440 }; 441 442 pinctrl_usart0_rts: usart0_rts-0 { 443 atmel,pins = 444 <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA28 periph A */ 445 }; 446 447 pinctrl_usart0_cts: usart0_cts-0 { 448 atmel,pins = 449 <AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA29 periph A */ 450 }; 451 }; 452 453 usart1 { 454 pinctrl_usart1: usart1-0 { 455 atmel,pins = 456 <AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD0 periph A with pullup */ 457 AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD1 periph A */ 458 }; 459 460 pinctrl_usart1_rts: usart1_rts-0 { 461 atmel,pins = 462 <AT91_PIOD 7 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD7 periph B */ 463 }; 464 465 pinctrl_usart1_cts: usart1_cts-0 { 466 atmel,pins = 467 <AT91_PIOD 8 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD8 periph B */ 468 }; 469 }; 470 471 usart2 { 472 pinctrl_usart2: usart2-0 { 473 atmel,pins = 474 <AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD2 periph A with pullup */ 475 AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD3 periph A */ 476 }; 477 478 pinctrl_usart2_rts: usart2_rts-0 { 479 atmel,pins = 480 <AT91_PIOD 5 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD5 periph B */ 481 }; 482 483 pinctrl_usart2_cts: usart2_cts-0 { 484 atmel,pins = 485 <AT91_PIOD 6 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD6 periph B */ 486 }; 487 }; 488 489 nand { 490 pinctrl_nand: nand-0 { 491 atmel,pins = 492 <AT91_PIOA 22 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PA22 gpio RDY pin pull_up*/ 493 AT91_PIOD 15 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PD15 gpio enable pin pull_up */ 494 }; 495 }; 496 497 macb { 498 pinctrl_macb_rmii: macb_rmii-0 { 499 atmel,pins = 500 <AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC25 periph B */ 501 AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE21 periph A */ 502 AT91_PIOE 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE23 periph A */ 503 AT91_PIOE 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE24 periph A */ 504 AT91_PIOE 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE25 periph A */ 505 AT91_PIOE 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE26 periph A */ 506 AT91_PIOE 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE27 periph A */ 507 AT91_PIOE 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE28 periph A */ 508 AT91_PIOE 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE29 periph A */ 509 AT91_PIOE 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PE30 periph A */ 510 }; 511 512 pinctrl_macb_rmii_mii: macb_rmii_mii-0 { 513 atmel,pins = 514 <AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC20 periph B */ 515 AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC21 periph B */ 516 AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC22 periph B */ 517 AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC23 periph B */ 518 AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC24 periph B */ 519 AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC25 periph B */ 520 AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC27 periph B */ 521 AT91_PIOE 22 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PE22 periph B */ 522 }; 523 }; 524 525 mmc0 { 526 pinctrl_mmc0_clk: mmc0_clk-0 { 527 atmel,pins = 528 <AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA12 periph A */ 529 }; 530 531 pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 { 532 atmel,pins = 533 <AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA1 periph A with pullup */ 534 AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA0 periph A with pullup */ 535 }; 536 537 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { 538 atmel,pins = 539 <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA3 periph A with pullup */ 540 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA4 periph A with pullup */ 541 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA5 periph A with pullup */ 542 }; 543 544 pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 { 545 atmel,pins = 546 <AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA16 periph A with pullup */ 547 AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA17 periph A with pullup */ 548 }; 549 550 pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 { 551 atmel,pins = 552 <AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA18 periph A with pullup */ 553 AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA19 periph A with pullup */ 554 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA20 periph A with pullup */ 555 }; 556 }; 557 558 mmc1 { 559 pinctrl_mmc1_clk: mmc1_clk-0 { 560 atmel,pins = 561 <AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA6 periph A */ 562 }; 563 564 pinctrl_mmc1_slot0_cmd_dat0: mmc1_slot0_cmd_dat0-0 { 565 atmel,pins = 566 <AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA7 periph A with pullup */ 567 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA8 periph A with pullup */ 568 }; 569 570 pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 { 571 atmel,pins = 572 <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA9 periph A with pullup */ 573 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA10 periph A with pullup */ 574 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA11 periph A with pullup */ 575 }; 576 577 pinctrl_mmc1_slot1_cmd_dat0: mmc1_slot1_cmd_dat0-0 { 578 atmel,pins = 579 <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA21 periph A with pullup */ 580 AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA22 periph A with pullup */ 581 }; 582 583 pinctrl_mmc1_slot1_dat1_3: mmc1_slot1_dat1_3-0 { 584 atmel,pins = 585 <AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA23 periph A with pullup */ 586 AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA24 periph A with pullup */ 587 AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA25 periph A with pullup */ 588 }; 589 }; 590 591 ssc0 { 592 pinctrl_ssc0_tx: ssc0_tx-0 { 593 atmel,pins = 594 <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB0 periph B */ 595 AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB1 periph B */ 596 AT91_PIOB 2 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB2 periph B */ 597 }; 598 599 pinctrl_ssc0_rx: ssc0_rx-0 { 600 atmel,pins = 601 <AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB3 periph B */ 602 AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB4 periph B */ 603 AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB5 periph B */ 604 }; 605 }; 606 607 ssc1 { 608 pinctrl_ssc1_tx: ssc1_tx-0 { 609 atmel,pins = 610 <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A */ 611 AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB7 periph A */ 612 AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB8 periph A */ 613 }; 614 615 pinctrl_ssc1_rx: ssc1_rx-0 { 616 atmel,pins = 617 <AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A */ 618 AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB10 periph A */ 619 AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB11 periph A */ 620 }; 621 }; 622 623 spi0 { 624 pinctrl_spi0: spi0-0 { 625 atmel,pins = 626 <AT91_PIOA 0 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA0 periph B SPI0_MISO pin */ 627 AT91_PIOA 1 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA1 periph B SPI0_MOSI pin */ 628 AT91_PIOA 2 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA2 periph B SPI0_SPCK pin */ 629 }; 630 }; 631 632 spi1 { 633 pinctrl_spi1: spi1-0 { 634 atmel,pins = 635 <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A SPI1_MISO pin */ 636 AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A SPI1_MOSI pin */ 637 AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB14 periph A SPI1_SPCK pin */ 638 }; 639 }; 640 641 tcb0 { 642 pinctrl_tcb0_tclk0: tcb0_tclk0-0 { 643 atmel,pins = <AT91_PIOB 28 AT91_PERIPH_B AT91_PINCTRL_NONE>; 644 }; 645 646 pinctrl_tcb0_tclk1: tcb0_tclk1-0 { 647 atmel,pins = <AT91_PIOC 28 AT91_PERIPH_B AT91_PINCTRL_NONE>; 648 }; 649 650 pinctrl_tcb0_tclk2: tcb0_tclk2-0 { 651 atmel,pins = <AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE>; 652 }; 653 654 pinctrl_tcb0_tioa0: tcb0_tioa0-0 { 655 atmel,pins = <AT91_PIOE 18 AT91_PERIPH_B AT91_PINCTRL_NONE>; 656 }; 657 658 pinctrl_tcb0_tioa1: tcb0_tioa1-0 { 659 atmel,pins = <AT91_PIOE 8 AT91_PERIPH_B AT91_PINCTRL_NONE>; 660 }; 661 662 pinctrl_tcb0_tioa2: tcb0_tioa2-0 { 663 atmel,pins = <AT91_PIOB 17 AT91_PERIPH_B AT91_PINCTRL_NONE>; 664 }; 665 666 pinctrl_tcb0_tiob0: tcb0_tiob0-0 { 667 atmel,pins = <AT91_PIOE 19 AT91_PERIPH_B AT91_PINCTRL_NONE>; 668 }; 669 670 pinctrl_tcb0_tiob1: tcb0_tiob1-0 { 671 atmel,pins = <AT91_PIOE 9 AT91_PERIPH_B AT91_PINCTRL_NONE>; 672 }; 673 674 pinctrl_tcb0_tiob2: tcb0_tiob2-0 { 675 atmel,pins = <AT91_PIOB 18 AT91_PERIPH_B AT91_PINCTRL_NONE>; 676 }; 677 }; 678 679 fb { 680 pinctrl_fb: fb-0 { 681 atmel,pins = 682 <AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC1 periph A */ 683 AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC2 periph A */ 684 AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC3 periph A */ 685 AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB9 periph B */ 686 AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC6 periph A */ 687 AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC7 periph A */ 688 AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC8 periph A */ 689 AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC9 periph A */ 690 AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC10 periph A */ 691 AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC11 periph A */ 692 AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC14 periph A */ 693 AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC15 periph A */ 694 AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC16 periph A */ 695 AT91_PIOC 12 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC12 periph B */ 696 AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC18 periph A */ 697 AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC19 periph A */ 698 AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC22 periph A */ 699 AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC23 periph A */ 700 AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC24 periph A */ 701 AT91_PIOC 17 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC17 periph B */ 702 AT91_PIOC 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC26 periph A */ 703 AT91_PIOC 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC27 periph A */ 704 }; 705 }; 706 707 can { 708 pinctrl_can_rx_tx: can_rx_tx { 709 atmel,pins = 710 <AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* CANRX, conflicts with IRQ0 */ 711 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* CANTX, conflicts with PCK0 */ 712 }; 713 }; 714 715 ac97 { 716 pinctrl_ac97: ac97-0 { 717 atmel,pins = 718 <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A AC97FS pin */ 719 AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A AC97CK pin */ 720 AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A AC97TX pin */ 721 AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB14 periph A AC97RX pin */ 722 }; 723 }; 724 725 }; 726 727 pioA: gpio@fffff200 { 728 compatible = "atmel,at91rm9200-gpio"; 729 reg = <0xfffff200 0x200>; 730 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; 731 #gpio-cells = <2>; 732 gpio-controller; 733 interrupt-controller; 734 #interrupt-cells = <2>; 735 clocks = <&pioA_clk>; 736 u-boot,dm-pre-reloc; 737 }; 738 739 pioB: gpio@fffff400 { 740 compatible = "atmel,at91rm9200-gpio"; 741 reg = <0xfffff400 0x200>; 742 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; 743 #gpio-cells = <2>; 744 gpio-controller; 745 interrupt-controller; 746 #interrupt-cells = <2>; 747 clocks = <&pioB_clk>; 748 u-boot,dm-pre-reloc; 749 }; 750 751 pioC: gpio@fffff600 { 752 compatible = "atmel,at91rm9200-gpio"; 753 reg = <0xfffff600 0x200>; 754 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; 755 #gpio-cells = <2>; 756 gpio-controller; 757 interrupt-controller; 758 #interrupt-cells = <2>; 759 clocks = <&pioCDE_clk>; 760 u-boot,dm-pre-reloc; 761 }; 762 763 pioD: gpio@fffff800 { 764 compatible = "atmel,at91rm9200-gpio"; 765 reg = <0xfffff800 0x200>; 766 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; 767 #gpio-cells = <2>; 768 gpio-controller; 769 interrupt-controller; 770 #interrupt-cells = <2>; 771 clocks = <&pioCDE_clk>; 772 u-boot,dm-pre-reloc; 773 }; 774 775 pioE: gpio@fffffa00 { 776 compatible = "atmel,at91rm9200-gpio"; 777 reg = <0xfffffa00 0x200>; 778 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; 779 #gpio-cells = <2>; 780 gpio-controller; 781 interrupt-controller; 782 #interrupt-cells = <2>; 783 clocks = <&pioCDE_clk>; 784 u-boot,dm-pre-reloc; 785 }; 786 787 dbgu: serial@ffffee00 { 788 compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; 789 reg = <0xffffee00 0x200>; 790 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 791 pinctrl-names = "default"; 792 pinctrl-0 = <&pinctrl_dbgu>; 793 clocks = <&mck>; 794 clock-names = "usart"; 795 status = "disabled"; 796 }; 797 798 usart0: serial@fff8c000 { 799 compatible = "atmel,at91sam9260-usart"; 800 reg = <0xfff8c000 0x200>; 801 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; 802 atmel,use-dma-rx; 803 atmel,use-dma-tx; 804 pinctrl-names = "default"; 805 pinctrl-0 = <&pinctrl_usart0>; 806 clocks = <&usart0_clk>; 807 clock-names = "usart"; 808 status = "disabled"; 809 }; 810 811 usart1: serial@fff90000 { 812 compatible = "atmel,at91sam9260-usart"; 813 reg = <0xfff90000 0x200>; 814 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; 815 atmel,use-dma-rx; 816 atmel,use-dma-tx; 817 pinctrl-names = "default"; 818 pinctrl-0 = <&pinctrl_usart1>; 819 clocks = <&usart1_clk>; 820 clock-names = "usart"; 821 status = "disabled"; 822 }; 823 824 usart2: serial@fff94000 { 825 compatible = "atmel,at91sam9260-usart"; 826 reg = <0xfff94000 0x200>; 827 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 5>; 828 atmel,use-dma-rx; 829 atmel,use-dma-tx; 830 pinctrl-names = "default"; 831 pinctrl-0 = <&pinctrl_usart2>; 832 clocks = <&usart2_clk>; 833 clock-names = "usart"; 834 status = "disabled"; 835 }; 836 837 ssc0: ssc@fff98000 { 838 compatible = "atmel,at91rm9200-ssc"; 839 reg = <0xfff98000 0x4000>; 840 interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; 841 pinctrl-names = "default"; 842 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; 843 clocks = <&ssc0_clk>; 844 clock-names = "pclk"; 845 status = "disabled"; 846 }; 847 848 ssc1: ssc@fff9c000 { 849 compatible = "atmel,at91rm9200-ssc"; 850 reg = <0xfff9c000 0x4000>; 851 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>; 852 pinctrl-names = "default"; 853 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; 854 clocks = <&ssc1_clk>; 855 clock-names = "pclk"; 856 status = "disabled"; 857 }; 858 859 ac97: sound@fffa0000 { 860 compatible = "atmel,at91sam9263-ac97c"; 861 reg = <0xfffa0000 0x4000>; 862 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 5>; 863 pinctrl-names = "default"; 864 pinctrl-0 = <&pinctrl_ac97>; 865 clocks = <&ac97_clk>; 866 clock-names = "ac97_clk"; 867 status = "disabled"; 868 }; 869 870 macb0: ethernet@fffbc000 { 871 compatible = "cdns,at91sam9260-macb", "cdns,macb"; 872 reg = <0xfffbc000 0x100>; 873 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>; 874 pinctrl-names = "default"; 875 pinctrl-0 = <&pinctrl_macb_rmii>; 876 clocks = <&macb0_clk>, <&macb0_clk>; 877 clock-names = "hclk", "pclk"; 878 status = "disabled"; 879 }; 880 881 usb1: gadget@fff78000 { 882 compatible = "atmel,at91sam9263-udc"; 883 reg = <0xfff78000 0x4000>; 884 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 2>; 885 clocks = <&udc_clk>, <&udpck>; 886 clock-names = "pclk", "hclk"; 887 status = "disabled"; 888 }; 889 890 i2c0: i2c@fff88000 { 891 compatible = "atmel,at91sam9260-i2c"; 892 reg = <0xfff88000 0x100>; 893 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 6>; 894 #address-cells = <1>; 895 #size-cells = <0>; 896 clocks = <&twi0_clk>; 897 status = "disabled"; 898 }; 899 900 mmc0: mmc@fff80000 { 901 compatible = "atmel,hsmci"; 902 reg = <0xfff80000 0x600>; 903 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>; 904 pinctrl-names = "default"; 905 #address-cells = <1>; 906 #size-cells = <0>; 907 clocks = <&mci0_clk>; 908 clock-names = "mci_clk"; 909 status = "disabled"; 910 }; 911 912 mmc1: mmc@fff84000 { 913 compatible = "atmel,hsmci"; 914 reg = <0xfff84000 0x600>; 915 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>; 916 pinctrl-names = "default"; 917 #address-cells = <1>; 918 #size-cells = <0>; 919 clocks = <&mci1_clk>; 920 clock-names = "mci_clk"; 921 status = "disabled"; 922 }; 923 924 watchdog@fffffd40 { 925 compatible = "atmel,at91sam9260-wdt"; 926 reg = <0xfffffd40 0x10>; 927 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 928 clocks = <&slow_xtal>; 929 atmel,watchdog-type = "hardware"; 930 atmel,reset-type = "all"; 931 atmel,dbg-halt; 932 status = "disabled"; 933 }; 934 935 spi0: spi@fffa4000 { 936 #address-cells = <1>; 937 #size-cells = <0>; 938 compatible = "atmel,at91rm9200-spi"; 939 reg = <0xfffa4000 0x200>; 940 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>; 941 pinctrl-names = "default"; 942 pinctrl-0 = <&pinctrl_spi0>; 943 clocks = <&spi0_clk>; 944 clock-names = "spi_clk"; 945 status = "disabled"; 946 }; 947 948 spi1: spi@fffa8000 { 949 #address-cells = <1>; 950 #size-cells = <0>; 951 compatible = "atmel,at91rm9200-spi"; 952 reg = <0xfffa8000 0x200>; 953 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 3>; 954 pinctrl-names = "default"; 955 pinctrl-0 = <&pinctrl_spi1>; 956 clocks = <&spi1_clk>; 957 clock-names = "spi_clk"; 958 status = "disabled"; 959 }; 960 961 pwm0: pwm@fffb8000 { 962 compatible = "atmel,at91sam9rl-pwm"; 963 reg = <0xfffb8000 0x300>; 964 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 4>; 965 #pwm-cells = <3>; 966 clocks = <&pwm_clk>; 967 clock-names = "pwm_clk"; 968 status = "disabled"; 969 }; 970 971 can: can@fffac000 { 972 compatible = "atmel,at91sam9263-can"; 973 reg = <0xfffac000 0x300>; 974 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 3>; 975 pinctrl-names = "default"; 976 pinctrl-0 = <&pinctrl_can_rx_tx>; 977 clocks = <&can_clk>; 978 clock-names = "can_clk"; 979 }; 980 981 rtc@fffffd20 { 982 compatible = "atmel,at91sam9260-rtt"; 983 reg = <0xfffffd20 0x10>; 984 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 985 clocks = <&slow_xtal>; 986 status = "disabled"; 987 }; 988 989 rtc@fffffd50 { 990 compatible = "atmel,at91sam9260-rtt"; 991 reg = <0xfffffd50 0x10>; 992 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 993 clocks = <&slow_xtal>; 994 status = "disabled"; 995 }; 996 997 gpbr: syscon@fffffd60 { 998 compatible = "atmel,at91sam9260-gpbr", "syscon"; 999 reg = <0xfffffd60 0x50>; 1000 status = "disabled"; 1001 }; 1002 }; 1003 1004 fb0: fb@0x00700000 { 1005 compatible = "atmel,at91sam9263-lcdc"; 1006 reg = <0x00700000 0x1000>; 1007 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 3>; 1008 pinctrl-names = "default"; 1009 pinctrl-0 = <&pinctrl_fb>; 1010 clocks = <&lcd_clk>, <&lcd_clk>; 1011 clock-names = "lcdc_clk", "hclk"; 1012 status = "disabled"; 1013 }; 1014 1015 nand0: nand@40000000 { 1016 compatible = "atmel,at91rm9200-nand"; 1017 #address-cells = <1>; 1018 #size-cells = <1>; 1019 reg = <0x40000000 0x10000000 1020 0xffffe000 0x200 1021 >; 1022 atmel,nand-addr-offset = <21>; 1023 atmel,nand-cmd-offset = <22>; 1024 pinctrl-names = "default"; 1025 pinctrl-0 = <&pinctrl_nand>; 1026 gpios = <&pioA 22 GPIO_ACTIVE_HIGH 1027 &pioD 15 GPIO_ACTIVE_HIGH 1028 0 1029 >; 1030 status = "disabled"; 1031 }; 1032 1033 usb0: ohci@00a00000 { 1034 compatible = "atmel,at91rm9200-ohci", "usb-ohci"; 1035 reg = <0x00a00000 0x100000>; 1036 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 2>; 1037 clocks = <&ohci_clk>, <&ohci_clk>, <&uhpck>; 1038 clock-names = "ohci_clk", "hclk", "uhpck"; 1039 status = "disabled"; 1040 }; 1041 }; 1042 1043 i2c-gpio-0 { 1044 compatible = "i2c-gpio"; 1045 gpios = <&pioB 4 GPIO_ACTIVE_HIGH /* sda */ 1046 &pioB 5 GPIO_ACTIVE_HIGH /* scl */ 1047 >; 1048 i2c-gpio,sda-open-drain; 1049 i2c-gpio,scl-open-drain; 1050 i2c-gpio,delay-us = <2>; /* ~100 kHz */ 1051 #address-cells = <1>; 1052 #size-cells = <0>; 1053 status = "disabled"; 1054 }; 1055}; 1056