1/dts-v1/; 2 3#include "ast2600-u-boot.dtsi" 4 5/ { 6 memory { 7 device_type = "memory"; 8 reg = <0x80000000 0x40000000>; 9 }; 10 11 chosen { 12 stdout-path = &uart5; 13 }; 14 15 aliases { 16 mmc0 = &emmc_slot0; 17 mmc1 = &sdhci_slot0; 18 mmc2 = &sdhci_slot1; 19 spi0 = &fmc; 20 spi1 = &spi1; 21 spi2 = &spi2; 22 23 ethernet0 = &mac1; 24 ethernet1 = &mac2; 25 ethernet2 = &mac3; 26 }; 27 28 cpus { 29 cpu@0 { 30 clock-frequency = <800000000>; 31 }; 32 cpu@1 { 33 clock-frequency = <800000000>; 34 }; 35 }; 36}; 37 38&uart5 { 39 u-boot,dm-pre-reloc; 40 status = "okay"; 41}; 42 43&sdrammc { 44 clock-frequency = <400000000>; 45}; 46 47&wdt1 { 48 u-boot,dm-pre-reloc; 49 status = "okay"; 50}; 51 52&wdt2 { 53 u-boot,dm-pre-reloc; 54 status = "okay"; 55}; 56 57&wdt3 { 58 u-boot,dm-pre-reloc; 59 status = "okay"; 60}; 61 62&mdio { 63 status = "okay"; 64 #address-cells = <1>; 65 #size-cells = <0>; 66 ethphy1: ethernet-phy@1 { 67 reg = <0>; 68 }; 69 70 ethphy2: ethernet-phy@2 { 71 reg = <0>; 72 }; 73 74 ethphy3: ethernet-phy@3 { 75 reg = <0>; 76 }; 77 78 ethphy4: ethernet-phy@4 { 79 reg = <0>; 80 }; 81}; 82 83 84&mac1 { 85 status = "okay"; 86 phy-mode = "rgmii"; 87 phy-handle = <ðphy2>; 88 pinctrl-names = "default"; 89 pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mac2link_default &pinctrl_mdio2_default>; 90}; 91 92&mac2 { 93 status = "okay"; 94 phy-mode = "rgmii"; 95 phy-handle = <ðphy3>; 96 pinctrl-names = "default"; 97 pinctrl-0 = <&pinctrl_rgmii3_default &pinctrl_mac3link_default &pinctrl_mdio3_default>; 98}; 99 100&mac3 { 101 status = "okay"; 102 phy-mode = "rgmii"; 103 phy-handle = <ðphy4>; 104 pinctrl-names = "default"; 105 pinctrl-0 = <&pinctrl_rgmii4_default &pinctrl_mac4link_default &pinctrl_mdio4_default>; 106}; 107 108&fmc { 109 status = "okay"; 110 111 pinctrl-names = "default"; 112 pinctrl-0 = <&pinctrl_fmcquad_default>; 113 114 flash@0 { 115 compatible = "spi-flash", "sst,w25q256"; 116 status = "okay"; 117 spi-max-frequency = <50000000>; 118 spi-tx-bus-width = <4>; 119 spi-rx-bus-width = <4>; 120 }; 121 122 flash@1 { 123 compatible = "spi-flash", "sst,w25q256"; 124 status = "okay"; 125 spi-max-frequency = <50000000>; 126 spi-tx-bus-width = <4>; 127 spi-rx-bus-width = <4>; 128 }; 129 130 flash@2 { 131 compatible = "spi-flash", "sst,w25q256"; 132 status = "okay"; 133 spi-max-frequency = <50000000>; 134 spi-tx-bus-width = <4>; 135 spi-rx-bus-width = <4>; 136 }; 137}; 138 139&spi1 { 140 status = "okay"; 141 142 pinctrl-names = "default"; 143 pinctrl-0 = <&pinctrl_spi1_default &pinctrl_spi1abr_default 144 &pinctrl_spi1cs1_default &pinctrl_spi1wp_default 145 &pinctrl_spi1wp_default &pinctrl_spi1quad_default>; 146 147 flash@0 { 148 compatible = "spi-flash", "sst,w25q256"; 149 status = "okay"; 150 spi-max-frequency = <50000000>; 151 spi-tx-bus-width = <4>; 152 spi-rx-bus-width = <4>; 153 }; 154 155 flash@1 { 156 compatible = "spi-flash", "sst,w25q256"; 157 status = "okay"; 158 spi-max-frequency = <50000000>; 159 spi-tx-bus-width = <4>; 160 spi-rx-bus-width = <4>; 161 }; 162}; 163 164&spi2 { 165 status = "okay"; 166 167 pinctrl-names = "default"; 168 pinctrl-0 = <&pinctrl_spi2_default &pinctrl_spi2cs1_default 169 &pinctrl_spi2cs2_default &pinctrl_spi2quad_default>; 170 171 flash@0 { 172 compatible = "spi-flash", "sst,w25q256"; 173 status = "okay"; 174 spi-max-frequency = <50000000>; 175 spi-tx-bus-width = <4>; 176 spi-rx-bus-width = <4>; 177 }; 178 179 flash@1 { 180 compatible = "spi-flash", "sst,w25q256"; 181 status = "okay"; 182 spi-max-frequency = <50000000>; 183 spi-tx-bus-width = <4>; 184 spi-rx-bus-width = <4>; 185 }; 186 187 flash@2 { 188 compatible = "spi-flash", "sst,w25q256"; 189 status = "okay"; 190 spi-max-frequency = <50000000>; 191 spi-tx-bus-width = <4>; 192 spi-rx-bus-width = <4>; 193 }; 194}; 195 196&emmc_slot0 { 197 status = "okay"; 198 199#if 1 200 bus-width = <4>; 201 pinctrl-names = "default"; 202 pinctrl-0 = <&pinctrl_emmc_default>; 203#else 204 bus-width = <8>; 205 pinctrl-names = "default"; 206 pinctrl-0 = <&pinctrl_emmcg8_default>; 207#endif 208}; 209 210&sdhci_slot0 { 211 status = "okay"; 212 bus-width = <4>; 213 pwr-gpios = <&gpio0 ASPEED_GPIO(V, 0) GPIO_ACTIVE_HIGH>; 214 pwr-sw-gpios = <&gpio0 ASPEED_GPIO(V, 1) GPIO_ACTIVE_HIGH>; 215 pinctrl-names = "default"; 216 pinctrl-0 = <&pinctrl_sd1_default>; 217}; 218 219&sdhci_slot1 { 220 status = "okay"; 221 bus-width = <4>; 222 pwr-gpios = <&gpio0 ASPEED_GPIO(V, 2) GPIO_ACTIVE_HIGH>; 223 pwr-sw-gpios = <&gpio0 ASPEED_GPIO(V, 3) GPIO_ACTIVE_HIGH>; 224 pinctrl-names = "default"; 225 pinctrl-0 = <&pinctrl_sd2_default>; 226}; 227 228&i2c4 { 229 status = "okay"; 230 231 pinctrl-names = "default"; 232 pinctrl-0 = <&pinctrl_i2c5_default>; 233}; 234 235&i2c5 { 236 status = "okay"; 237 238 pinctrl-names = "default"; 239 pinctrl-0 = <&pinctrl_i2c6_default>; 240}; 241 242&i2c6 { 243 status = "okay"; 244 245 pinctrl-names = "default"; 246 pinctrl-0 = <&pinctrl_i2c7_default>; 247}; 248 249&i2c7 { 250 status = "okay"; 251 252 pinctrl-names = "default"; 253 pinctrl-0 = <&pinctrl_i2c8_default>; 254}; 255 256&i2c8 { 257 status = "okay"; 258 259 pinctrl-names = "default"; 260 pinctrl-0 = <&pinctrl_i2c9_default>; 261}; 262 263#if 0 264&pcie_bridge0 { 265 status = "okay"; 266}; 267#endif 268 269&pcie_bridge1 { 270 status = "okay"; 271}; 272 273&h2x { 274 status = "okay"; 275}; 276 277#if 0 278&fsim0 { 279 status = "okay"; 280}; 281 282&fsim1 { 283 status = "okay"; 284}; 285#endif 286 287&ehci1 { 288 status = "okay"; 289}; 290