xref: /openbmc/u-boot/arch/arm/dts/ast2600a0-evb.dts (revision 25fde1c0) 
1/dts-v1/;
2
3#include "ast2600-u-boot.dtsi"
4
5/ {
6        model = "AST2600 EVB";
7        compatible = "aspeed,ast2600-evb", "aspeed,ast2600";
8
9	memory {
10		device_type = "memory";
11		reg = <0x80000000 0x40000000>;
12	};
13
14	chosen {
15		stdout-path = &uart5;
16	};
17
18	aliases {
19		mmc0 = &emmc_slot0;
20		mmc1 = &sdhci_slot0;
21		mmc2 = &sdhci_slot1;
22		spi0 = &fmc;
23		spi1 = &spi1;
24		spi2 = &spi2;
25
26		ethernet0 = &mac1;
27		ethernet1 = &mac2;
28		ethernet2 = &mac3;
29	};
30
31	cpus {
32		cpu@0 {
33			clock-frequency = <800000000>;
34		};
35		cpu@1 {
36			clock-frequency = <800000000>;
37		};
38	};
39};
40
41&uart5 {
42	u-boot,dm-pre-reloc;
43	status = "okay";
44};
45
46&sdrammc {
47	clock-frequency = <400000000>;
48};
49
50&wdt1 {
51	u-boot,dm-pre-reloc;
52	status = "okay";
53};
54
55&wdt2 {
56	u-boot,dm-pre-reloc;
57	status = "okay";
58};
59
60&wdt3 {
61	u-boot,dm-pre-reloc;
62	status = "okay";
63};
64
65&mdio {
66	status = "okay";
67	#address-cells = <1>;
68	#size-cells = <0>;
69	ethphy1: ethernet-phy@1 {
70		reg = <0>;
71	};
72
73	ethphy2: ethernet-phy@2 {
74		reg = <0>;
75	};
76
77	ethphy3: ethernet-phy@3 {
78		reg = <0>;
79	};
80
81	ethphy4: ethernet-phy@4 {
82		reg = <0>;
83	};
84};
85
86
87&mac1 {
88	status = "okay";
89	phy-mode = "rgmii";
90	phy-handle = <&ethphy2>;
91	pinctrl-names = "default";
92	pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mac2link_default &pinctrl_mdio2_default>;
93};
94
95&mac2 {
96	status = "okay";
97	phy-mode = "rgmii";
98	phy-handle = <&ethphy3>;
99	pinctrl-names = "default";
100	pinctrl-0 = <&pinctrl_rgmii3_default &pinctrl_mac3link_default &pinctrl_mdio3_default>;
101};
102
103&mac3 {
104	status = "okay";
105	phy-mode = "rgmii";
106	phy-handle = <&ethphy4>;
107	pinctrl-names = "default";
108	pinctrl-0 = <&pinctrl_rgmii4_default &pinctrl_mac4link_default &pinctrl_mdio4_default>;
109};
110
111&fmc {
112	status = "okay";
113
114	pinctrl-names = "default";
115	pinctrl-0 = <&pinctrl_fmcquad_default>;
116
117	flash@0 {
118		status = "okay";
119		spi-max-frequency = <50000000>;
120		spi-tx-bus-width = <4>;
121		spi-rx-bus-width = <4>;
122	};
123
124	flash@1 {
125		status = "okay";
126		spi-max-frequency = <50000000>;
127		spi-tx-bus-width = <4>;
128		spi-rx-bus-width = <4>;
129	};
130
131	flash@2 {
132		status = "disabled";
133		spi-max-frequency = <50000000>;
134		spi-tx-bus-width = <4>;
135		spi-rx-bus-width = <4>;
136	};
137};
138
139&spi1 {
140	status = "okay";
141
142	pinctrl-names = "default";
143	pinctrl-0 = <&pinctrl_spi1_default &pinctrl_spi1abr_default
144			&pinctrl_spi1cs1_default &pinctrl_spi1wp_default
145			&pinctrl_spi1wp_default &pinctrl_spi1quad_default>;
146
147	flash@0 {
148		status = "okay";
149		spi-max-frequency = <50000000>;
150		spi-tx-bus-width = <4>;
151		spi-rx-bus-width = <4>;
152	};
153
154	flash@1 {
155		status = "disabled";
156		spi-max-frequency = <50000000>;
157		spi-tx-bus-width = <4>;
158		spi-rx-bus-width = <4>;
159	};
160};
161
162&spi2 {
163	status = "okay";
164
165	pinctrl-names = "default";
166	pinctrl-0 = <&pinctrl_spi2_default &pinctrl_spi2cs1_default
167			&pinctrl_spi2cs2_default &pinctrl_spi2quad_default>;
168
169	flash@0 {
170		status = "okay";
171		spi-max-frequency = <50000000>;
172		spi-tx-bus-width = <4>;
173		spi-rx-bus-width = <4>;
174	};
175
176	flash@1 {
177		status = "disabled";
178		spi-max-frequency = <50000000>;
179		spi-tx-bus-width = <4>;
180		spi-rx-bus-width = <4>;
181	};
182
183	flash@2 {
184		status = "disabled";
185		spi-max-frequency = <50000000>;
186		spi-tx-bus-width = <4>;
187		spi-rx-bus-width = <4>;
188	};
189};
190
191&emmc_slot0 {
192	status = "okay";
193
194#if 1
195	bus-width = <4>;
196	pinctrl-names = "default";
197	pinctrl-0 = <&pinctrl_emmc_default>;
198#else
199	bus-width = <8>;
200	pinctrl-names = "default";
201	pinctrl-0 = <&pinctrl_emmcg8_default>;
202#endif
203};
204
205&sdhci_slot0 {
206	status = "okay";
207	bus-width = <4>;
208	pwr-gpios = <&gpio0 ASPEED_GPIO(V, 0) GPIO_ACTIVE_HIGH>;
209	pwr-sw-gpios = <&gpio0 ASPEED_GPIO(V, 1) GPIO_ACTIVE_HIGH>;
210	pinctrl-names = "default";
211	pinctrl-0 = <&pinctrl_sd1_default>;
212};
213
214&sdhci_slot1 {
215	status = "okay";
216	bus-width = <4>;
217	pwr-gpios = <&gpio0 ASPEED_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
218	pwr-sw-gpios = <&gpio0 ASPEED_GPIO(V, 3) GPIO_ACTIVE_HIGH>;
219	pinctrl-names = "default";
220	pinctrl-0 = <&pinctrl_sd2_default>;
221};
222
223&i2c4 {
224	status = "okay";
225
226	pinctrl-names = "default";
227	pinctrl-0 = <&pinctrl_i2c5_default>;
228};
229
230&i2c5 {
231	status = "okay";
232
233	pinctrl-names = "default";
234	pinctrl-0 = <&pinctrl_i2c6_default>;
235};
236
237&i2c6 {
238	status = "okay";
239
240	pinctrl-names = "default";
241	pinctrl-0 = <&pinctrl_i2c7_default>;
242};
243
244&i2c7 {
245	status = "okay";
246
247	pinctrl-names = "default";
248	pinctrl-0 = <&pinctrl_i2c8_default>;
249};
250
251&i2c8 {
252	status = "okay";
253
254	pinctrl-names = "default";
255	pinctrl-0 = <&pinctrl_i2c9_default>;
256};
257
258
259#if 0
260&fsim0 {
261	status = "okay";
262};
263
264&fsim1 {
265	status = "okay";
266};
267#endif
268
269&ehci1 {
270	status = "okay";
271};
272