1// SPDX-License-Identifier: GPL-2.0+ 2#include <dt-bindings/interrupt-controller/arm-gic.h> 3#include <dt-bindings/gpio/aspeed-gpio.h> 4#include "skeleton.dtsi" 5 6/ { 7 model = "Aspeed BMC"; 8 compatible = "aspeed,ast2600"; 9 #address-cells = <1>; 10 #size-cells = <1>; 11 interrupt-parent = <&gic>; 12 13 aliases { 14 i2c0 = &i2c0; 15 i2c1 = &i2c1; 16 i2c2 = &i2c2; 17 i2c3 = &i2c3; 18 i2c4 = &i2c4; 19 i2c5 = &i2c5; 20 i2c6 = &i2c6; 21 i2c7 = &i2c7; 22 i2c8 = &i2c8; 23 i2c9 = &i2c9; 24 i2c10 = &i2c10; 25 i2c11 = &i2c11; 26 i2c12 = &i2c12; 27 i2c13 = &i2c13; 28 i2c14 = &i2c14; 29 i2c15 = &i2c15; 30 serial0 = &uart1; 31 serial1 = &uart2; 32 serial2 = &uart3; 33 serial3 = &uart4; 34 serial4 = &uart5; 35 serial5 = &uart6; 36 serial6 = &uart7; 37 serial7 = &uart8; 38 serial8 = &uart9; 39 serial9 = &uart10; 40 serial10 = &uart11; 41 serial11 = &uart12; 42 serial12 = &uart13; 43 }; 44 45 cpus { 46 #address-cells = <1>; 47 #size-cells = <0>; 48 enable-method = "aspeed,ast2600-smp"; 49 50 cpu@0 { 51 compatible = "arm,cortex-a7"; 52 device_type = "cpu"; 53 reg = <0>; 54 }; 55 56 cpu@1 { 57 compatible = "arm,cortex-a7"; 58 device_type = "cpu"; 59 reg = <1>; 60 }; 61 62 }; 63 64 timer { 65 compatible = "arm,armv7-timer"; 66 interrupt-parent = <&gic>; 67 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 68 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 69 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 70 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 71 }; 72 73 reserved-memory { 74 #address-cells = <1>; 75 #size-cells = <1>; 76 ranges; 77 78 gfx_memory: framebuffer { 79 size = <0x01000000>; 80 alignment = <0x01000000>; 81 compatible = "shared-dma-pool"; 82 reusable; 83 }; 84 85 video_memory: video { 86 size = <0x04000000>; 87 alignment = <0x01000000>; 88 compatible = "shared-dma-pool"; 89 no-map; 90 }; 91 }; 92 93 ahb { 94 compatible = "simple-bus"; 95 #address-cells = <1>; 96 #size-cells = <1>; 97 device_type = "soc"; 98 ranges; 99 100 gic: interrupt-controller@40461000 { 101 compatible = "arm,cortex-a7-gic"; 102 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 103 #interrupt-cells = <3>; 104 interrupt-controller; 105 interrupt-parent = <&gic>; 106 reg = <0x40461000 0x1000>, 107 <0x40462000 0x1000>, 108 <0x40464000 0x2000>, 109 <0x40466000 0x2000>; 110 }; 111 112 ahbc: ahbc@1e600000 { 113 compatible = "aspeed,aspeed-ahbc"; 114 reg = < 0x1e600000 0x100>; 115 }; 116 117 fmc: flash-controller@1e620000 { 118 reg = <0x1e620000 0xc4 119 0x20000000 0x10000000>; 120 #address-cells = <1>; 121 #size-cells = <0>; 122 compatible = "aspeed,ast2600-fmc"; 123 status = "disabled"; 124 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 125 clocks = <&scu ASPEED_CLK_AHB>; 126 num-cs = <3>; 127 flash@0 { 128 reg = < 0 >; 129 compatible = "jedec,spi-nor"; 130 status = "disabled"; 131 }; 132 flash@1 { 133 reg = < 1 >; 134 compatible = "jedec,spi-nor"; 135 status = "disabled"; 136 }; 137 flash@2 { 138 reg = < 2 >; 139 compatible = "jedec,spi-nor"; 140 status = "disabled"; 141 }; 142 }; 143 144 spi1: flash-controller@1e630000 { 145 reg = <0x1e630000 0xc4 146 0x30000000 0x10000000>; 147 #address-cells = <1>; 148 #size-cells = <0>; 149 compatible = "aspeed,ast2600-spi"; 150 clocks = <&scu ASPEED_CLK_AHB>; 151 num-cs = <2>; 152 status = "disabled"; 153 flash@0 { 154 reg = < 0 >; 155 compatible = "jedec,spi-nor"; 156 status = "disabled"; 157 }; 158 flash@1 { 159 reg = < 1 >; 160 compatible = "jedec,spi-nor"; 161 status = "disabled"; 162 }; 163 }; 164 165 spi2: flash-controller@1e631000 { 166 reg = <0x1e631000 0xc4 167 0x50000000 0x10000000>; 168 #address-cells = <1>; 169 #size-cells = <0>; 170 compatible = "aspeed,ast2600-spi"; 171 clocks = <&scu ASPEED_CLK_AHB>; 172 num-cs = <3>; 173 status = "disabled"; 174 flash@0 { 175 reg = < 0 >; 176 compatible = "jedec,spi-nor"; 177 status = "disabled"; 178 }; 179 flash@1 { 180 reg = < 1 >; 181 compatible = "jedec,spi-nor"; 182 status = "disabled"; 183 }; 184 flash@2 { 185 reg = < 2 >; 186 compatible = "jedec,spi-nor"; 187 status = "disabled"; 188 }; 189 }; 190 191 edac: sdram@1e6e0000 { 192 compatible = "aspeed,ast2600-sdram-edac"; 193 reg = <0x1e6e0000 0x174>; 194 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 195 }; 196 197 mdio: ethernet@1e650000 { 198 compatible = "aspeed,aspeed-mdio"; 199 reg = <0x1e650000 0x40>; 200 resets = <&rst ASPEED_RESET_MII>; 201 status = "disabled"; 202 }; 203 204 mac0: ftgmac@1e660000 { 205 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 206 reg = <0x1e660000 0x180>, <0x1e650000 0x4>; 207 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 208 clocks = <&scu ASPEED_CLK_GATE_MAC1CLK>; 209 status = "disabled"; 210 }; 211 212 mac1: ftgmac@1e680000 { 213 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 214 reg = <0x1e680000 0x180>, <0x1e650008 0x4>; 215 #address-cells = <1>; 216 #size-cells = <0>; 217 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 218 clocks = <&scu ASPEED_CLK_GATE_MAC2CLK>; 219 status = "disabled"; 220 }; 221 222 mac2: ftgmac@1e670000 { 223 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 224 reg = <0x1e670000 0x180>, <0x1e650010 0x4>; 225 #address-cells = <1>; 226 #size-cells = <0>; 227 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 228 clocks = <&scu ASPEED_CLK_GATE_MAC3CLK>; 229 status = "disabled"; 230 }; 231 232 mac3: ftgmac@1e690000 { 233 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 234 reg = <0x1e690000 0x180>, <0x1e650018 0x4>; 235 #address-cells = <1>; 236 #size-cells = <0>; 237 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 238 clocks = <&scu ASPEED_CLK_GATE_MAC4CLK>; 239 status = "disabled"; 240 }; 241 242 vhub: usb-vhub@1e6a0000 { 243 compatible = "aspeed,ast2600-usb-vhub"; 244 reg = <0x1e6a0000 0x350>; 245 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 246 clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>; 247 resets = <&rst ASPEED_RESET_EHCI_P1>; 248 pinctrl-names = "default"; 249 pinctrl-0 = <&pinctrl_usb2ad_default>; 250 status = "disabled"; 251 }; 252 253 ehci0: usb@1e6a1000 { 254 compatible = "aspeed,aspeed-ehci", "usb-ehci"; 255 reg = <0x1e6a1000 0x100>; 256 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 257 clocks = <&scu ASPEED_CLK_GATE_USBPORT1CLK>; 258 pinctrl-names = "default"; 259 pinctrl-0 = <&pinctrl_usb2ah_default>; 260 status = "disabled"; 261 }; 262 263 ehci1: usb@1e6a3000 { 264 compatible = "aspeed,aspeed-ehci", "usb-ehci"; 265 reg = <0x1e6a3000 0x100>; 266 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 267 clocks = <&scu ASPEED_CLK_GATE_USBPORT2CLK>; 268 pinctrl-names = "default"; 269 pinctrl-0 = <&pinctrl_usb2bh_default>; 270 status = "disabled"; 271 }; 272 273 apb { 274 compatible = "simple-bus"; 275 #address-cells = <1>; 276 #size-cells = <1>; 277 ranges; 278 u-boot,dm-pre-reloc; 279 280 syscon: syscon@1e6e2000 { 281 compatible = "aspeed,g6-scu", "syscon", "simple-mfd"; 282 reg = <0x1e6e2000 0x1000>; 283 #address-cells = <1>; 284 #size-cells = <1>; 285 #clock-cells = <1>; 286 #reset-cells = <1>; 287 ranges = <0 0x1e6e2000 0x1000>; 288 u-boot,dm-pre-reloc; 289 290 pinctrl: pinctrl { 291 compatible = "aspeed,g6-pinctrl"; 292 aspeed,external-nodes = <&gfx &lhc>; 293 u-boot,dm-pre-reloc; 294 }; 295 296 vga_scratch: scratch { 297 compatible = "aspeed,bmc-misc"; 298 }; 299 300 scu_ic0: interrupt-controller@0 { 301 #interrupt-cells = <1>; 302 compatible = "aspeed,ast2600-scu-ic"; 303 reg = <0x560 0x10>; 304 interrupt-parent = <&gic>; 305 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 306 interrupt-controller; 307 }; 308 309 scu_ic1: interrupt-controller@1 { 310 #interrupt-cells = <1>; 311 compatible = "aspeed,ast2600-scu-ic"; 312 reg = <0x570 0x10>; 313 interrupt-parent = <&gic>; 314 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 315 interrupt-controller; 316 }; 317 318 }; 319 320 hace: hace@1e6d0000 { 321 compatible = "aspeed,ast2600-hace"; 322 reg = <0x1e6d0000 0x200>; 323 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 324 clocks = <&scu ASPEED_CLK_GATE_YCLK>; 325 clock-names = "yclk"; 326 status = "disabled"; 327 }; 328 329 acry: acry@1e6fa000 { 330 compatible = "aspeed,ast2600-acry"; 331 reg = <0x1e6fa000 0x1000>, 332 <0x1e710000 0x20000>; 333 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 334 clocks = <&scu ASPEED_CLK_GATE_RSAECCCLK>; 335 clock-names = "rsaeccclk"; 336 status = "disabled"; 337 }; 338 339 smp-memram@0 { 340 compatible = "aspeed,ast2600-smpmem", "syscon"; 341 reg = <0x1e6e2180 0x40>; 342 }; 343 344 gfx: display@1e6e6000 { 345 compatible = "aspeed,ast2500-gfx", "syscon"; 346 reg = <0x1e6e6000 0x1000>; 347 reg-io-width = <4>; 348 }; 349 350 sdhci: sdhci@1e740000 { 351 #interrupt-cells = <1>; 352 compatible = "aspeed,aspeed-sdhci-irq", "simple-mfd"; 353 reg = <0x1e740000 0x1000>; 354 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 355 interrupt-controller; 356 clocks = <&scu ASPEED_CLK_GATE_SDCLK>, <&scu ASPEED_CLK_GATE_SDEXTCLK>; 357 clock-names = "ctrlclk", "extclk"; 358 #address-cells = <1>; 359 #size-cells = <1>; 360 ranges = <0x0 0x1e740000 0x1000>; 361 362 sdhci_slot0: sdhci_slot0@100 { 363 compatible = "aspeed,sdhci-ast2600"; 364 reg = <0x100 0x100>; 365 interrupts = <0>; 366 interrupt-parent = <&sdhci>; 367 sdhci,auto-cmd12; 368 clocks = <&scu ASPEED_CLK_SDIO>; 369 status = "disabled"; 370 }; 371 372 sdhci_slot1: sdhci_slot1@200 { 373 compatible = "aspeed,sdhci-ast2600"; 374 reg = <0x200 0x100>; 375 interrupts = <1>; 376 interrupt-parent = <&sdhci>; 377 sdhci,auto-cmd12; 378 clocks = <&scu ASPEED_CLK_SDIO>; 379 status = "disabled"; 380 }; 381 }; 382 383 emmc: emmc@1e750000 { 384 #interrupt-cells = <1>; 385 compatible = "aspeed,aspeed-emmc-irq", "simple-mfd"; 386 reg = <0x1e750000 0x1000>; 387 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 388 interrupt-controller; 389 clocks = <&scu ASPEED_CLK_GATE_EMMCCLK>, <&scu ASPEED_CLK_GATE_EMMCEXTCLK>; 390 clock-names = "ctrlclk", "extclk"; 391 #address-cells = <1>; 392 #size-cells = <1>; 393 ranges = <0x0 0x1e750000 0x1000>; 394 395 emmc_slot0: emmc_slot0@100 { 396 compatible = "aspeed,emmc-ast2600"; 397 reg = <0x100 0x100>; 398 interrupts = <0>; 399 interrupt-parent = <&emmc>; 400 clocks = <&scu ASPEED_CLK_EMMC>; 401 status = "disabled"; 402 }; 403 }; 404 405 pcie_phy0: phy@1e6ed000 { 406 compatible = "aspeed,ast2600-pcie_phy"; 407 reg = <0x1e6ed000 0x100>; 408 resets = <&rst ASPEED_RESET_PCIE_DEV_O>; 409 pinctrl-names = "default"; 410 pinctrl-0 = <&pinctrl_pcie0rc_default>; 411 status = "disabled"; 412 }; 413 414 pcie_phy1: phy@1e6ed200 { 415 compatible = "aspeed,ast2600-pcie_phy"; 416 reg = <0x1e6ed200 0x100>; 417 resets = <&rst ASPEED_RESET_PCIE_RC_O>; 418 pinctrl-names = "default"; 419 pinctrl-0 = <&pinctrl_pcie1rc_default>; 420 status = "disabled"; 421 }; 422 423 pcie_bridge: pcie@1e770000 { 424 compatible = "aspeed,ast2600-pcie"; 425 #address-cells = <3>; 426 #size-cells = <2>; 427 reg = <0x1e770000 0x100>; 428 ranges = <0x81000000 0x0 0x0 0x0 0x0 0x10000 /* downstream I/O */ 429 0x82000000 0x0 0x60000000 0x60000000 0x0 0x20000000>; /* non-prefetchable memory */ 430 device_type = "pci"; 431 bus-range = <0x00 0xff>; 432 resets = <&rst ASPEED_RESET_H2X>, <&rst ASPEED_RESET_PCIE_DEV_O>, <&rst ASPEED_RESET_PCIE_RC_O>; 433 slot0-handle = <&pcie_phy0>; 434 slot1-handle = <&pcie_phy1>; 435 status = "disabled"; 436 }; 437 438 gpio0: gpio@1e780000 { 439 compatible = "aspeed,ast2600-gpio"; 440 reg = <0x1e780000 0x400>; 441 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 442 #gpio-cells = <2>; 443 gpio-controller; 444 interrupt-controller; 445 gpio-ranges = <&pinctrl 0 0 208>; 446 ngpios = <208>; 447 }; 448 449 gpio1: gpio@1e780800 { 450 compatible = "aspeed,ast2600-gpio"; 451 reg = <0x1e780800 0x800>; 452 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 453 #gpio-cells = <2>; 454 gpio-controller; 455 interrupt-controller; 456 gpio-ranges = <&pinctrl 0 208 36>; 457 ngpios = <36>; 458 }; 459 460 uart1: serial@1e783000 { 461 compatible = "ns16550a"; 462 reg = <0x1e783000 0x20>; 463 reg-shift = <2>; 464 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 465 clocks = <&scu ASPEED_CLK_GATE_UART1CLK>; 466 clock-frequency = <1846154>; 467 no-loopback-test; 468 u-boot,dm-pre-reloc; 469 pinctrl-names = "default"; 470 pinctrl-0 = <&pinctrl_txd1_default &pinctrl_rxd1_default>; 471 status = "disabled"; 472 }; 473 474 uart5: serial@1e784000 { 475 compatible = "ns16550a"; 476 reg = <0x1e784000 0x1000>; 477 reg-shift = <2>; 478 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 479 clocks = <&scu ASPEED_CLK_GATE_UART5CLK>; 480 clock-frequency = <1846154>; 481 no-loopback-test; 482 u-boot,dm-pre-reloc; 483 status = "disabled"; 484 }; 485 486 wdt1: watchdog@1e785000 { 487 compatible = "aspeed,ast2600-wdt"; 488 reg = <0x1e785000 0x40>; 489 }; 490 491 wdt2: watchdog@1e785040 { 492 compatible = "aspeed,ast2600-wdt"; 493 reg = <0x1e785040 0x40>; 494 }; 495 496 wdt3: watchdog@1e785080 { 497 compatible = "aspeed,ast2600-wdt"; 498 reg = <0x1e785080 0x40>; 499 }; 500 501 wdt4: watchdog@1e7850C0 { 502 compatible = "aspeed,ast2600-wdt"; 503 reg = <0x1e7850C0 0x40>; 504 }; 505 506 lpc: lpc@1e789000 { 507 compatible = "aspeed,ast-lpc", "simple-mfd", "syscon"; 508 reg = <0x1e789000 0x200>; 509 510 #address-cells = <1>; 511 #size-cells = <1>; 512 ranges = <0x0 0x1e789000 0x1000>; 513 514 lpc_bmc: lpc-bmc@0 { 515 compatible = "aspeed,ast2600-lpc-bmc", "simple-mfd", "syscon"; 516 reg = <0x0 0x80>; 517 reg-io-width = <4>; 518 #address-cells = <1>; 519 #size-cells = <1>; 520 ranges = <0x0 0x0 0x80>; 521 522 kcs1: kcs1@0 { 523 compatible = "aspeed,ast2600-kcs-bmc"; 524 reg = <0x0 0x80>; 525 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 526 kcs_chan = <1>; 527 kcs_addr = <0xCA0>; 528 status = "disabled"; 529 }; 530 531 kcs2: kcs2@0 { 532 compatible = "aspeed,ast2600-kcs-bmc"; 533 reg = <0x0 0x80>; 534 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 535 kcs_chan = <2>; 536 kcs_addr = <0xCA8>; 537 status = "disabled"; 538 }; 539 540 kcs3: kcs3@0 { 541 compatible = "aspeed,ast2600-kcs-bmc"; 542 reg = <0x0 0x80>; 543 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 544 kcs_chan = <3>; 545 kcs_addr = <0xCA2>; 546 }; 547 548 kcs4: kcs4@0 { 549 compatible = "aspeed,ast2600-kcs-bmc"; 550 reg = <0x0 0x120>; 551 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 552 kcs_chan = <4>; 553 kcs_addr = <0xCA4>; 554 status = "disabled"; 555 }; 556 557 }; 558 559 lpc_host: lpc-host@80 { 560 compatible = "aspeed,ast2600-lpc-host", "simple-mfd", "syscon"; 561 reg = <0x80 0x1e0>; 562 reg-io-width = <4>; 563 564 #address-cells = <1>; 565 #size-cells = <1>; 566 ranges = <0x0 0x80 0x1e0>; 567 568 lpc_ctrl: lpc-ctrl@0 { 569 compatible = "aspeed,ast2600-lpc-ctrl"; 570 reg = <0x0 0x80>; 571 status = "disabled"; 572 }; 573 574 lpc_snoop: lpc-snoop@0 { 575 compatible = "aspeed,ast2600-lpc-snoop"; 576 reg = <0x0 0x80>; 577 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 578 snoop-ports = <0x80>; 579 status = "disabled"; 580 }; 581 582 lhc: lhc@20 { 583 compatible = "aspeed,ast2600-lhc"; 584 reg = <0x20 0x24 0x48 0x8>; 585 }; 586 587 lpc_reset: reset-controller@18 { 588 compatible = "aspeed,ast2600-lpc-reset"; 589 reg = <0x18 0x4>; 590 #reset-cells = <1>; 591 status = "disabled"; 592 }; 593 594 ibt: ibt@c0 { 595 compatible = "aspeed,ast2600-ibt-bmc"; 596 reg = <0xc0 0x18>; 597 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 598 status = "disabled"; 599 }; 600 601 sio_regs: regs { 602 compatible = "aspeed,bmc-misc"; 603 }; 604 605 mbox: mbox@180 { 606 compatible = "aspeed,ast2600-mbox"; 607 reg = <0x180 0x5c>; 608 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 609 #mbox-cells = <1>; 610 status = "disabled"; 611 }; 612 }; 613 }; 614 615 uart2: serial@1e78d000 { 616 compatible = "ns16550a"; 617 reg = <0x1e78d000 0x20>; 618 reg-shift = <2>; 619 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 620 clocks = <&scu ASPEED_CLK_GATE_UART2CLK>; 621 clock-frequency = <1846154>; 622 no-loopback-test; 623 pinctrl-names = "default"; 624 pinctrl-0 = <&pinctrl_txd2_default &pinctrl_rxd2_default>; 625 u-boot,dm-pre-reloc; 626 status = "disabled"; 627 }; 628 629 uart3: serial@1e78e000 { 630 compatible = "ns16550a"; 631 reg = <0x1e78e000 0x20>; 632 reg-shift = <2>; 633 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 634 clocks = <&scu ASPEED_CLK_GATE_UART3CLK>; 635 clock-frequency = <1846154>; 636 no-loopback-test; 637 pinctrl-names = "default"; 638 pinctrl-0 = <&pinctrl_txd3_default &pinctrl_rxd3_default>; 639 u-boot,dm-pre-reloc; 640 status = "disabled"; 641 }; 642 643 uart4: serial@1e78f000 { 644 compatible = "ns16550a"; 645 reg = <0x1e78f000 0x20>; 646 reg-shift = <2>; 647 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 648 clocks = <&scu ASPEED_CLK_GATE_UART4CLK>; 649 clock-frequency = <1846154>; 650 no-loopback-test; 651 u-boot,dm-pre-reloc; 652 pinctrl-names = "default"; 653 pinctrl-0 = <&pinctrl_txd4_default &pinctrl_rxd4_default>; 654 status = "disabled"; 655 }; 656 657 i2c: bus@1e78a000 { 658 compatible = "simple-bus"; 659 #address-cells = <1>; 660 #size-cells = <1>; 661 ranges = <0 0x1e78a000 0x1000>; 662 }; 663 664 fsim0: fsi@1e79b000 { 665 compatible = "aspeed,ast2600-fsi-master", "fsi-master"; 666 reg = <0x1e79b000 0x94>; 667 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 668 pinctrl-names = "default"; 669 pinctrl-0 = <&pinctrl_fsi1_default>; 670 clocks = <&scu ASPEED_CLK_GATE_FSICLK>; 671 status = "disabled"; 672 }; 673 674 fsim1: fsi@1e79b100 { 675 compatible = "aspeed,ast2600-fsi-master", "fsi-master"; 676 reg = <0x1e79b100 0x94>; 677 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 678 pinctrl-names = "default"; 679 pinctrl-0 = <&pinctrl_fsi2_default>; 680 clocks = <&scu ASPEED_CLK_GATE_FSICLK>; 681 status = "disabled"; 682 }; 683 684 uart6: serial@1e790000 { 685 compatible = "ns16550a"; 686 reg = <0x1e790000 0x20>; 687 reg-shift = <2>; 688 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 689 clocks = <&scu ASPEED_CLK_GATE_UART6CLK>; 690 clock-frequency = <1846154>; 691 no-loopback-test; 692 status = "disabled"; 693 }; 694 695 uart7: serial@1e790100 { 696 compatible = "ns16550a"; 697 reg = <0x1e790100 0x20>; 698 reg-shift = <2>; 699 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 700 clocks = <&scu ASPEED_CLK_GATE_UART7CLK>; 701 clock-frequency = <1846154>; 702 no-loopback-test; 703 status = "disabled"; 704 }; 705 706 uart8: serial@1e790200 { 707 compatible = "ns16550a"; 708 reg = <0x1e790200 0x20>; 709 reg-shift = <2>; 710 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 711 clocks = <&scu ASPEED_CLK_GATE_UART8CLK>; 712 clock-frequency = <1846154>; 713 no-loopback-test; 714 status = "disabled"; 715 }; 716 717 uart9: serial@1e790300 { 718 compatible = "ns16550a"; 719 reg = <0x1e790300 0x20>; 720 reg-shift = <2>; 721 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 722 clocks = <&scu ASPEED_CLK_GATE_UART9CLK>; 723 clock-frequency = <1846154>; 724 no-loopback-test; 725 status = "disabled"; 726 }; 727 728 uart10: serial@1e790400 { 729 compatible = "ns16550a"; 730 reg = <0x1e790400 0x20>; 731 reg-shift = <2>; 732 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 733 clocks = <&scu ASPEED_CLK_GATE_UART10CLK>; 734 clock-frequency = <1846154>; 735 no-loopback-test; 736 status = "disabled"; 737 }; 738 739 uart11: serial@1e790500 { 740 compatible = "ns16550a"; 741 reg = <0x1e790400 0x20>; 742 reg-shift = <2>; 743 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 744 clocks = <&scu ASPEED_CLK_GATE_UART11CLK>; 745 clock-frequency = <1846154>; 746 no-loopback-test; 747 status = "disabled"; 748 }; 749 750 uart12: serial@1e790600 { 751 compatible = "ns16550a"; 752 reg = <0x1e790600 0x20>; 753 reg-shift = <2>; 754 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 755 clocks = <&scu ASPEED_CLK_GATE_UART12CLK>; 756 clock-frequency = <1846154>; 757 no-loopback-test; 758 status = "disabled"; 759 }; 760 761 uart13: serial@1e790700 { 762 compatible = "ns16550a"; 763 reg = <0x1e790700 0x20>; 764 reg-shift = <2>; 765 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 766 clocks = <&scu ASPEED_CLK_GATE_UART13CLK>; 767 clock-frequency = <1846154>; 768 no-loopback-test; 769 status = "disabled"; 770 }; 771 772 display_port: dp@1e6eb000 { 773 compatible = "aspeed,ast2600-displayport"; 774 reg = <0x1e6eb000 0x200>; 775 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 776 resets = <&rst ASPEED_RESET_DP>, <&rst ASPEED_RESET_DP_MCU>; 777 status = "disabled"; 778 }; 779 780 }; 781 782 }; 783 784}; 785 786&i2c { 787 i2cglobal: i2cg@00 { 788 compatible = "aspeed,ast2600-i2c-global"; 789 reg = <0x0 0x40>; 790 resets = <&rst ASPEED_RESET_I2C>; 791 }; 792 793 i2c0: i2c@80 { 794 #address-cells = <1>; 795 #size-cells = <0>; 796 #interrupt-cells = <1>; 797 798 reg = <0x80 0x80 0xC00 0x20>; 799 compatible = "aspeed,ast2600-i2c"; 800 bus-frequency = <100000>; 801 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 802 clocks = <&scu ASPEED_CLK_APB2>; 803 status = "disabled"; 804 }; 805 806 i2c1: i2c@100 { 807 #address-cells = <1>; 808 #size-cells = <0>; 809 #interrupt-cells = <1>; 810 811 reg = <0x100 0x80 0xC20 0x20>; 812 compatible = "aspeed,ast2600-i2c"; 813 bus-frequency = <100000>; 814 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 815 clocks = <&scu ASPEED_CLK_APB2>; 816 status = "disabled"; 817 }; 818 819 i2c2: i2c@180 { 820 #address-cells = <1>; 821 #size-cells = <0>; 822 #interrupt-cells = <1>; 823 824 reg = <0x180 0x80 0xC40 0x20>; 825 compatible = "aspeed,ast2600-i2c"; 826 bus-frequency = <100000>; 827 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 828 clocks = <&scu ASPEED_CLK_APB2>; 829 }; 830 831 i2c3: i2c@200 { 832 #address-cells = <1>; 833 #size-cells = <0>; 834 #interrupt-cells = <1>; 835 836 reg = <0x200 0x40 0xC60 0x20>; 837 compatible = "aspeed,ast2600-i2c"; 838 bus-frequency = <100000>; 839 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 840 clocks = <&scu ASPEED_CLK_APB2>; 841 }; 842 843 i2c4: i2c@280 { 844 #address-cells = <1>; 845 #size-cells = <0>; 846 #interrupt-cells = <1>; 847 848 reg = <0x280 0x80 0xC80 0x20>; 849 compatible = "aspeed,ast2600-i2c"; 850 bus-frequency = <100000>; 851 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 852 clocks = <&scu ASPEED_CLK_APB2>; 853 }; 854 855 i2c5: i2c@300 { 856 #address-cells = <1>; 857 #size-cells = <0>; 858 #interrupt-cells = <1>; 859 860 reg = <0x300 0x40 0xCA0 0x20>; 861 compatible = "aspeed,ast2600-i2c"; 862 bus-frequency = <100000>; 863 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 864 clocks = <&scu ASPEED_CLK_APB2>; 865 }; 866 867 i2c6: i2c@380 { 868 #address-cells = <1>; 869 #size-cells = <0>; 870 #interrupt-cells = <1>; 871 872 reg = <0x380 0x80 0xCC0 0x20>; 873 compatible = "aspeed,ast2600-i2c"; 874 bus-frequency = <100000>; 875 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 876 clocks = <&scu ASPEED_CLK_APB2>; 877 }; 878 879 i2c7: i2c@400 { 880 #address-cells = <1>; 881 #size-cells = <0>; 882 #interrupt-cells = <1>; 883 884 reg = <0x400 0x80 0xCE0 0x20>; 885 compatible = "aspeed,ast2600-i2c"; 886 bus-frequency = <100000>; 887 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 888 clocks = <&scu ASPEED_CLK_APB2>; 889 }; 890 891 i2c8: i2c@480 { 892 #address-cells = <1>; 893 #size-cells = <0>; 894 #interrupt-cells = <1>; 895 896 reg = <0x480 0x80 0xD00 0x20>; 897 compatible = "aspeed,ast2600-i2c"; 898 bus-frequency = <100000>; 899 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 900 clocks = <&scu ASPEED_CLK_APB2>; 901 }; 902 903 i2c9: i2c@500 { 904 #address-cells = <1>; 905 #size-cells = <0>; 906 #interrupt-cells = <1>; 907 908 reg = <0x500 0x80 0xD20 0x20>; 909 compatible = "aspeed,ast2600-i2c"; 910 bus-frequency = <100000>; 911 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 912 clocks = <&scu ASPEED_CLK_APB2>; 913 status = "disabled"; 914 }; 915 916 i2c10: i2c@580 { 917 #address-cells = <1>; 918 #size-cells = <0>; 919 #interrupt-cells = <1>; 920 921 reg = <0x580 0x80 0xD40 0x20>; 922 compatible = "aspeed,ast2600-i2c"; 923 bus-frequency = <100000>; 924 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 925 clocks = <&scu ASPEED_CLK_APB2>; 926 status = "disabled"; 927 }; 928 929 i2c11: i2c@600 { 930 #address-cells = <1>; 931 #size-cells = <0>; 932 #interrupt-cells = <1>; 933 934 reg = <0x600 0x80 0xD60 0x20>; 935 compatible = "aspeed,ast2600-i2c"; 936 bus-frequency = <100000>; 937 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 938 clocks = <&scu ASPEED_CLK_APB2>; 939 status = "disabled"; 940 }; 941 942 i2c12: i2c@680 { 943 #address-cells = <1>; 944 #size-cells = <0>; 945 #interrupt-cells = <1>; 946 947 reg = <0x680 0x80 0xD80 0x20>; 948 compatible = "aspeed,ast2600-i2c"; 949 bus-frequency = <100000>; 950 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 951 clocks = <&scu ASPEED_CLK_APB2>; 952 status = "disabled"; 953 }; 954 955 i2c13: i2c@700 { 956 #address-cells = <1>; 957 #size-cells = <0>; 958 #interrupt-cells = <1>; 959 960 reg = <0x700 0x80 0xDA0 0x20>; 961 compatible = "aspeed,ast2600-i2c"; 962 bus-frequency = <100000>; 963 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 964 clocks = <&scu ASPEED_CLK_APB2>; 965 status = "disabled"; 966 }; 967 968 i2c14: i2c@780 { 969 #address-cells = <1>; 970 #size-cells = <0>; 971 #interrupt-cells = <1>; 972 973 reg = <0x780 0x80 0xDC0 0x20>; 974 compatible = "aspeed,ast2600-i2c"; 975 bus-frequency = <100000>; 976 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 977 clocks = <&scu ASPEED_CLK_APB2>; 978 status = "disabled"; 979 }; 980 981 i2c15: i2c@800 { 982 #address-cells = <1>; 983 #size-cells = <0>; 984 #interrupt-cells = <1>; 985 986 reg = <0x800 0x80 0xDE0 0x20>; 987 compatible = "aspeed,ast2600-i2c"; 988 bus-frequency = <100000>; 989 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 990 clocks = <&scu ASPEED_CLK_APB2>; 991 status = "disabled"; 992 }; 993 994}; 995 996&pinctrl { 997 u-boot,dm-pre-reloc; 998 999 pinctrl_fmcquad_default: fmcquad_default { 1000 function = "FMCQUAD"; 1001 groups = "FMCQUAD"; 1002 }; 1003 1004 pinctrl_spi1_default: spi1_default { 1005 function = "SPI1"; 1006 groups = "SPI1"; 1007 }; 1008 1009 pinctrl_spi1abr_default: spi1abr_default { 1010 function = "SPI1ABR"; 1011 groups = "SPI1ABR"; 1012 }; 1013 1014 pinctrl_spi1cs1_default: spi1cs1_default { 1015 function = "SPI1CS1"; 1016 groups = "SPI1CS1"; 1017 }; 1018 1019 pinctrl_spi1wp_default: spi1wp_default { 1020 function = "SPI1WP"; 1021 groups = "SPI1WP"; 1022 }; 1023 1024 pinctrl_spi1quad_default: spi1quad_default { 1025 function = "SPI1QUAD"; 1026 groups = "SPI1QUAD"; 1027 }; 1028 1029 pinctrl_spi2_default: spi2_default { 1030 function = "SPI2"; 1031 groups = "SPI2"; 1032 }; 1033 1034 pinctrl_spi2cs1_default: spi2cs1_default { 1035 function = "SPI2CS1"; 1036 groups = "SPI2CS1"; 1037 }; 1038 1039 pinctrl_spi2cs2_default: spi2cs2_default { 1040 function = "SPI2CS2"; 1041 groups = "SPI2CS2"; 1042 }; 1043 1044 pinctrl_spi2quad_default: spi2quad_default { 1045 function = "SPI2QUAD"; 1046 groups = "SPI2QUAD"; 1047 }; 1048 1049 pinctrl_acpi_default: acpi_default { 1050 function = "ACPI"; 1051 groups = "ACPI"; 1052 }; 1053 1054 pinctrl_adc0_default: adc0_default { 1055 function = "ADC0"; 1056 groups = "ADC0"; 1057 }; 1058 1059 pinctrl_adc1_default: adc1_default { 1060 function = "ADC1"; 1061 groups = "ADC1"; 1062 }; 1063 1064 pinctrl_adc10_default: adc10_default { 1065 function = "ADC10"; 1066 groups = "ADC10"; 1067 }; 1068 1069 pinctrl_adc11_default: adc11_default { 1070 function = "ADC11"; 1071 groups = "ADC11"; 1072 }; 1073 1074 pinctrl_adc12_default: adc12_default { 1075 function = "ADC12"; 1076 groups = "ADC12"; 1077 }; 1078 1079 pinctrl_adc13_default: adc13_default { 1080 function = "ADC13"; 1081 groups = "ADC13"; 1082 }; 1083 1084 pinctrl_adc14_default: adc14_default { 1085 function = "ADC14"; 1086 groups = "ADC14"; 1087 }; 1088 1089 pinctrl_adc15_default: adc15_default { 1090 function = "ADC15"; 1091 groups = "ADC15"; 1092 }; 1093 1094 pinctrl_adc2_default: adc2_default { 1095 function = "ADC2"; 1096 groups = "ADC2"; 1097 }; 1098 1099 pinctrl_adc3_default: adc3_default { 1100 function = "ADC3"; 1101 groups = "ADC3"; 1102 }; 1103 1104 pinctrl_adc4_default: adc4_default { 1105 function = "ADC4"; 1106 groups = "ADC4"; 1107 }; 1108 1109 pinctrl_adc5_default: adc5_default { 1110 function = "ADC5"; 1111 groups = "ADC5"; 1112 }; 1113 1114 pinctrl_adc6_default: adc6_default { 1115 function = "ADC6"; 1116 groups = "ADC6"; 1117 }; 1118 1119 pinctrl_adc7_default: adc7_default { 1120 function = "ADC7"; 1121 groups = "ADC7"; 1122 }; 1123 1124 pinctrl_adc8_default: adc8_default { 1125 function = "ADC8"; 1126 groups = "ADC8"; 1127 }; 1128 1129 pinctrl_adc9_default: adc9_default { 1130 function = "ADC9"; 1131 groups = "ADC9"; 1132 }; 1133 1134 pinctrl_bmcint_default: bmcint_default { 1135 function = "BMCINT"; 1136 groups = "BMCINT"; 1137 }; 1138 1139 pinctrl_ddcclk_default: ddcclk_default { 1140 function = "DDCCLK"; 1141 groups = "DDCCLK"; 1142 }; 1143 1144 pinctrl_ddcdat_default: ddcdat_default { 1145 function = "DDCDAT"; 1146 groups = "DDCDAT"; 1147 }; 1148 1149 pinctrl_espi_default: espi_default { 1150 function = "ESPI"; 1151 groups = "ESPI"; 1152 }; 1153 1154 pinctrl_fsi1_default: fsi1_default { 1155 function = "FSI1"; 1156 groups = "FSI1"; 1157 }; 1158 1159 pinctrl_fsi2_default: fsi2_default { 1160 function = "FSI2"; 1161 groups = "FSI2"; 1162 }; 1163 1164 pinctrl_fwspics1_default: fwspics1_default { 1165 function = "FWSPICS1"; 1166 groups = "FWSPICS1"; 1167 }; 1168 1169 pinctrl_fwspics2_default: fwspics2_default { 1170 function = "FWSPICS2"; 1171 groups = "FWSPICS2"; 1172 }; 1173 1174 pinctrl_gpid0_default: gpid0_default { 1175 function = "GPID0"; 1176 groups = "GPID0"; 1177 }; 1178 1179 pinctrl_gpid2_default: gpid2_default { 1180 function = "GPID2"; 1181 groups = "GPID2"; 1182 }; 1183 1184 pinctrl_gpid4_default: gpid4_default { 1185 function = "GPID4"; 1186 groups = "GPID4"; 1187 }; 1188 1189 pinctrl_gpid6_default: gpid6_default { 1190 function = "GPID6"; 1191 groups = "GPID6"; 1192 }; 1193 1194 pinctrl_gpie0_default: gpie0_default { 1195 function = "GPIE0"; 1196 groups = "GPIE0"; 1197 }; 1198 1199 pinctrl_gpie2_default: gpie2_default { 1200 function = "GPIE2"; 1201 groups = "GPIE2"; 1202 }; 1203 1204 pinctrl_gpie4_default: gpie4_default { 1205 function = "GPIE4"; 1206 groups = "GPIE4"; 1207 }; 1208 1209 pinctrl_gpie6_default: gpie6_default { 1210 function = "GPIE6"; 1211 groups = "GPIE6"; 1212 }; 1213 1214 pinctrl_i2c1_default: i2c1_default { 1215 function = "I2C1"; 1216 groups = "I2C1"; 1217 }; 1218 pinctrl_i2c2_default: i2c2_default { 1219 function = "I2C2"; 1220 groups = "I2C2"; 1221 }; 1222 1223 pinctrl_i2c3_default: i2c3_default { 1224 function = "I2C3"; 1225 groups = "I2C3"; 1226 }; 1227 1228 pinctrl_i2c4_default: i2c4_default { 1229 function = "I2C4"; 1230 groups = "I2C4"; 1231 }; 1232 1233 pinctrl_i2c5_default: i2c5_default { 1234 function = "I2C5"; 1235 groups = "I2C5"; 1236 }; 1237 1238 pinctrl_i2c6_default: i2c6_default { 1239 function = "I2C6"; 1240 groups = "I2C6"; 1241 }; 1242 1243 pinctrl_i2c7_default: i2c7_default { 1244 function = "I2C7"; 1245 groups = "I2C7"; 1246 }; 1247 1248 pinctrl_i2c8_default: i2c8_default { 1249 function = "I2C8"; 1250 groups = "I2C8"; 1251 }; 1252 1253 pinctrl_i2c9_default: i2c9_default { 1254 function = "I2C9"; 1255 groups = "I2C9"; 1256 }; 1257 1258 pinctrl_i2c10_default: i2c10_default { 1259 function = "I2C10"; 1260 groups = "I2C10"; 1261 }; 1262 1263 pinctrl_i2c11_default: i2c11_default { 1264 function = "I2C11"; 1265 groups = "I2C11"; 1266 }; 1267 1268 pinctrl_i2c12_default: i2c12_default { 1269 function = "I2C12"; 1270 groups = "I2C12"; 1271 }; 1272 1273 pinctrl_i2c13_default: i2c13_default { 1274 function = "I2C13"; 1275 groups = "I2C13"; 1276 }; 1277 1278 pinctrl_i2c14_default: i2c14_default { 1279 function = "I2C14"; 1280 groups = "I2C14"; 1281 }; 1282 1283 pinctrl_i2c15_default: i2c15_default { 1284 function = "I2C15"; 1285 groups = "I2C15"; 1286 }; 1287 1288 pinctrl_i2c16_default: i2c16_default { 1289 function = "I2C16"; 1290 groups = "I2C16"; 1291 }; 1292 1293 pinctrl_si2c1_default: si2c1_default { 1294 function = "SI2C1"; 1295 groups = "SI2C1"; 1296 }; 1297 1298 pinctrl_si2c2_default: si2c2_default { 1299 function = "SI2C2"; 1300 groups = "SI2C2"; 1301 }; 1302 1303 pinctrl_si2c3_default: si2c3_default { 1304 function = "SI2C3"; 1305 groups = "SI2C3"; 1306 }; 1307 1308 pinctrl_si2c4_default: si2c4_default { 1309 function = "SI2C4"; 1310 groups = "SI2C4"; 1311 }; 1312 1313 pinctrl_si2c5_default: si2c5_default { 1314 function = "SI2C5"; 1315 groups = "SI2C5"; 1316 }; 1317 1318 pinctrl_si2c6_default: si2c6_default { 1319 function = "SI2C6"; 1320 groups = "SI2C6"; 1321 }; 1322 1323 pinctrl_si2c7_default: si2c7_default { 1324 function = "SI2C7"; 1325 groups = "SI2C7"; 1326 }; 1327 1328 pinctrl_si2c8_default: si2c8_default { 1329 function = "SI2C8"; 1330 groups = "SI2C8"; 1331 }; 1332 1333 pinctrl_si2c9_default: si2c9_default { 1334 function = "SI2C9"; 1335 groups = "SI2C9"; 1336 }; 1337 1338 pinctrl_si2c10_default: si2c10_default { 1339 function = "SI2C10"; 1340 groups = "SI2C10"; 1341 }; 1342 1343 pinctrl_lad0_default: lad0_default { 1344 function = "LAD0"; 1345 groups = "LAD0"; 1346 }; 1347 1348 pinctrl_lad1_default: lad1_default { 1349 function = "LAD1"; 1350 groups = "LAD1"; 1351 }; 1352 1353 pinctrl_lad2_default: lad2_default { 1354 function = "LAD2"; 1355 groups = "LAD2"; 1356 }; 1357 1358 pinctrl_lad3_default: lad3_default { 1359 function = "LAD3"; 1360 groups = "LAD3"; 1361 }; 1362 1363 pinctrl_lclk_default: lclk_default { 1364 function = "LCLK"; 1365 groups = "LCLK"; 1366 }; 1367 1368 pinctrl_lframe_default: lframe_default { 1369 function = "LFRAME"; 1370 groups = "LFRAME"; 1371 }; 1372 1373 pinctrl_lpchc_default: lpchc_default { 1374 function = "LPCHC"; 1375 groups = "LPCHC"; 1376 }; 1377 1378 pinctrl_lpcpd_default: lpcpd_default { 1379 function = "LPCPD"; 1380 groups = "LPCPD"; 1381 }; 1382 1383 pinctrl_lpcplus_default: lpcplus_default { 1384 function = "LPCPLUS"; 1385 groups = "LPCPLUS"; 1386 }; 1387 1388 pinctrl_lpcpme_default: lpcpme_default { 1389 function = "LPCPME"; 1390 groups = "LPCPME"; 1391 }; 1392 1393 pinctrl_lpcrst_default: lpcrst_default { 1394 function = "LPCRST"; 1395 groups = "LPCRST"; 1396 }; 1397 1398 pinctrl_lpcsmi_default: lpcsmi_default { 1399 function = "LPCSMI"; 1400 groups = "LPCSMI"; 1401 }; 1402 1403 pinctrl_lsirq_default: lsirq_default { 1404 function = "LSIRQ"; 1405 groups = "LSIRQ"; 1406 }; 1407 1408 pinctrl_mac1link_default: mac1link_default { 1409 function = "MAC1LINK"; 1410 groups = "MAC1LINK"; 1411 }; 1412 1413 pinctrl_mac2link_default: mac2link_default { 1414 function = "MAC2LINK"; 1415 groups = "MAC2LINK"; 1416 }; 1417 1418 pinctrl_mac3link_default: mac3link_default { 1419 function = "MAC3LINK"; 1420 groups = "MAC3LINK"; 1421 }; 1422 1423 pinctrl_mac4link_default: mac4link_default { 1424 function = "MAC4LINK"; 1425 groups = "MAC4LINK"; 1426 }; 1427 1428 pinctrl_mdio1_default: mdio1_default { 1429 function = "MDIO1"; 1430 groups = "MDIO1"; 1431 }; 1432 1433 pinctrl_mdio2_default: mdio2_default { 1434 function = "MDIO2"; 1435 groups = "MDIO2"; 1436 }; 1437 1438 pinctrl_mdio3_default: mdio3_default { 1439 function = "MDIO3"; 1440 groups = "MDIO3"; 1441 }; 1442 1443 pinctrl_mdio4_default: mdio4_default { 1444 function = "MDIO4"; 1445 groups = "MDIO4"; 1446 }; 1447 1448 pinctrl_rmii1_default: rmii1_default { 1449 function = "RMII1"; 1450 groups = "RMII1"; 1451 }; 1452 1453 pinctrl_rmii2_default: rmii2_default { 1454 function = "RMII2"; 1455 groups = "RMII2"; 1456 }; 1457 1458 pinctrl_rmii3_default: rmii3_default { 1459 function = "RMII3"; 1460 groups = "RMII3"; 1461 }; 1462 1463 pinctrl_rmii4_default: rmii4_default { 1464 function = "RMII4"; 1465 groups = "RMII4"; 1466 }; 1467 1468 pinctrl_rmii1rclk_default: rmii1rclk_default { 1469 function = "RMII1RCLK"; 1470 groups = "RMII1RCLK"; 1471 }; 1472 1473 pinctrl_rmii2rclk_default: rmii2rclk_default { 1474 function = "RMII2RCLK"; 1475 groups = "RMII2RCLK"; 1476 }; 1477 1478 pinctrl_rmii3rclk_default: rmii3rclk_default { 1479 function = "RMII3RCLK"; 1480 groups = "RMII3RCLK"; 1481 }; 1482 1483 pinctrl_rmii4rclk_default: rmii4rclk_default { 1484 function = "RMII4RCLK"; 1485 groups = "RMII4RCLK"; 1486 }; 1487 1488 pinctrl_ncts1_default: ncts1_default { 1489 function = "NCTS1"; 1490 groups = "NCTS1"; 1491 }; 1492 1493 pinctrl_ncts2_default: ncts2_default { 1494 function = "NCTS2"; 1495 groups = "NCTS2"; 1496 }; 1497 1498 pinctrl_ncts3_default: ncts3_default { 1499 function = "NCTS3"; 1500 groups = "NCTS3"; 1501 }; 1502 1503 pinctrl_ncts4_default: ncts4_default { 1504 function = "NCTS4"; 1505 groups = "NCTS4"; 1506 }; 1507 1508 pinctrl_ndcd1_default: ndcd1_default { 1509 function = "NDCD1"; 1510 groups = "NDCD1"; 1511 }; 1512 1513 pinctrl_ndcd2_default: ndcd2_default { 1514 function = "NDCD2"; 1515 groups = "NDCD2"; 1516 }; 1517 1518 pinctrl_ndcd3_default: ndcd3_default { 1519 function = "NDCD3"; 1520 groups = "NDCD3"; 1521 }; 1522 1523 pinctrl_ndcd4_default: ndcd4_default { 1524 function = "NDCD4"; 1525 groups = "NDCD4"; 1526 }; 1527 1528 pinctrl_ndsr1_default: ndsr1_default { 1529 function = "NDSR1"; 1530 groups = "NDSR1"; 1531 }; 1532 1533 pinctrl_ndsr2_default: ndsr2_default { 1534 function = "NDSR2"; 1535 groups = "NDSR2"; 1536 }; 1537 1538 pinctrl_ndsr3_default: ndsr3_default { 1539 function = "NDSR3"; 1540 groups = "NDSR3"; 1541 }; 1542 1543 pinctrl_ndsr4_default: ndsr4_default { 1544 function = "NDSR4"; 1545 groups = "NDSR4"; 1546 }; 1547 1548 pinctrl_ndtr1_default: ndtr1_default { 1549 function = "NDTR1"; 1550 groups = "NDTR1"; 1551 }; 1552 1553 pinctrl_ndtr2_default: ndtr2_default { 1554 function = "NDTR2"; 1555 groups = "NDTR2"; 1556 }; 1557 1558 pinctrl_ndtr3_default: ndtr3_default { 1559 function = "NDTR3"; 1560 groups = "NDTR3"; 1561 }; 1562 1563 pinctrl_ndtr4_default: ndtr4_default { 1564 function = "NDTR4"; 1565 groups = "NDTR4"; 1566 }; 1567 1568 pinctrl_nri1_default: nri1_default { 1569 function = "NRI1"; 1570 groups = "NRI1"; 1571 }; 1572 1573 pinctrl_nri2_default: nri2_default { 1574 function = "NRI2"; 1575 groups = "NRI2"; 1576 }; 1577 1578 pinctrl_nri3_default: nri3_default { 1579 function = "NRI3"; 1580 groups = "NRI3"; 1581 }; 1582 1583 pinctrl_nri4_default: nri4_default { 1584 function = "NRI4"; 1585 groups = "NRI4"; 1586 }; 1587 1588 pinctrl_nrts1_default: nrts1_default { 1589 function = "NRTS1"; 1590 groups = "NRTS1"; 1591 }; 1592 1593 pinctrl_nrts2_default: nrts2_default { 1594 function = "NRTS2"; 1595 groups = "NRTS2"; 1596 }; 1597 1598 pinctrl_nrts3_default: nrts3_default { 1599 function = "NRTS3"; 1600 groups = "NRTS3"; 1601 }; 1602 1603 pinctrl_nrts4_default: nrts4_default { 1604 function = "NRTS4"; 1605 groups = "NRTS4"; 1606 }; 1607 1608 pinctrl_oscclk_default: oscclk_default { 1609 function = "OSCCLK"; 1610 groups = "OSCCLK"; 1611 }; 1612 1613 pinctrl_pewake_default: pewake_default { 1614 function = "PEWAKE"; 1615 groups = "PEWAKE"; 1616 }; 1617 1618 pinctrl_pnor_default: pnor_default { 1619 function = "PNOR"; 1620 groups = "PNOR"; 1621 }; 1622 1623 pinctrl_pwm0_default: pwm0_default { 1624 function = "PWM0"; 1625 groups = "PWM0"; 1626 }; 1627 1628 pinctrl_pwm1_default: pwm1_default { 1629 function = "PWM1"; 1630 groups = "PWM1"; 1631 }; 1632 1633 pinctrl_pwm2_default: pwm2_default { 1634 function = "PWM2"; 1635 groups = "PWM2"; 1636 }; 1637 1638 pinctrl_pwm3_default: pwm3_default { 1639 function = "PWM3"; 1640 groups = "PWM3"; 1641 }; 1642 1643 pinctrl_pwm4_default: pwm4_default { 1644 function = "PWM4"; 1645 groups = "PWM4"; 1646 }; 1647 1648 pinctrl_pwm5_default: pwm5_default { 1649 function = "PWM5"; 1650 groups = "PWM5"; 1651 }; 1652 1653 pinctrl_pwm6_default: pwm6_default { 1654 function = "PWM6"; 1655 groups = "PWM6"; 1656 }; 1657 1658 pinctrl_pwm7_default: pwm7_default { 1659 function = "PWM7"; 1660 groups = "PWM7"; 1661 }; 1662 1663 pinctrl_rgmii1_default: rgmii1_default { 1664 function = "RGMII1"; 1665 groups = "RGMII1"; 1666 }; 1667 1668 pinctrl_rgmii2_default: rgmii2_default { 1669 function = "RGMII2"; 1670 groups = "RGMII2"; 1671 }; 1672 1673 pinctrl_rgmii3_default: rgmii3_default { 1674 function = "RGMII3"; 1675 groups = "RGMII3"; 1676 }; 1677 1678 pinctrl_rgmii4_default: rgmii4_default { 1679 function = "RGMII4"; 1680 groups = "RGMII4"; 1681 }; 1682 1683 pinctrl_rmii1_default: rmii1_default { 1684 function = "RMII1"; 1685 groups = "RMII1"; 1686 }; 1687 1688 pinctrl_rmii2_default: rmii2_default { 1689 function = "RMII2"; 1690 groups = "RMII2"; 1691 }; 1692 1693 pinctrl_rxd1_default: rxd1_default { 1694 function = "RXD1"; 1695 groups = "RXD1"; 1696 u-boot,dm-pre-reloc; 1697 }; 1698 1699 pinctrl_rxd2_default: rxd2_default { 1700 function = "RXD2"; 1701 groups = "RXD2"; 1702 u-boot,dm-pre-reloc; 1703 }; 1704 1705 pinctrl_rxd3_default: rxd3_default { 1706 function = "RXD3"; 1707 groups = "RXD3"; 1708 u-boot,dm-pre-reloc; 1709 }; 1710 1711 pinctrl_rxd4_default: rxd4_default { 1712 function = "RXD4"; 1713 groups = "RXD4"; 1714 u-boot,dm-pre-reloc; 1715 }; 1716 1717 pinctrl_salt1_default: salt1_default { 1718 function = "SALT1"; 1719 groups = "SALT1"; 1720 }; 1721 1722 pinctrl_salt10_default: salt10_default { 1723 function = "SALT10"; 1724 groups = "SALT10"; 1725 }; 1726 1727 pinctrl_salt11_default: salt11_default { 1728 function = "SALT11"; 1729 groups = "SALT11"; 1730 }; 1731 1732 pinctrl_salt12_default: salt12_default { 1733 function = "SALT12"; 1734 groups = "SALT12"; 1735 }; 1736 1737 pinctrl_salt13_default: salt13_default { 1738 function = "SALT13"; 1739 groups = "SALT13"; 1740 }; 1741 1742 pinctrl_salt14_default: salt14_default { 1743 function = "SALT14"; 1744 groups = "SALT14"; 1745 }; 1746 1747 pinctrl_salt2_default: salt2_default { 1748 function = "SALT2"; 1749 groups = "SALT2"; 1750 }; 1751 1752 pinctrl_salt3_default: salt3_default { 1753 function = "SALT3"; 1754 groups = "SALT3"; 1755 }; 1756 1757 pinctrl_salt4_default: salt4_default { 1758 function = "SALT4"; 1759 groups = "SALT4"; 1760 }; 1761 1762 pinctrl_salt5_default: salt5_default { 1763 function = "SALT5"; 1764 groups = "SALT5"; 1765 }; 1766 1767 pinctrl_salt6_default: salt6_default { 1768 function = "SALT6"; 1769 groups = "SALT6"; 1770 }; 1771 1772 pinctrl_salt7_default: salt7_default { 1773 function = "SALT7"; 1774 groups = "SALT7"; 1775 }; 1776 1777 pinctrl_salt8_default: salt8_default { 1778 function = "SALT8"; 1779 groups = "SALT8"; 1780 }; 1781 1782 pinctrl_salt9_default: salt9_default { 1783 function = "SALT9"; 1784 groups = "SALT9"; 1785 }; 1786 1787 pinctrl_scl1_default: scl1_default { 1788 function = "SCL1"; 1789 groups = "SCL1"; 1790 }; 1791 1792 pinctrl_scl2_default: scl2_default { 1793 function = "SCL2"; 1794 groups = "SCL2"; 1795 }; 1796 1797 pinctrl_sd1_default: sd1_default { 1798 function = "SD1"; 1799 groups = "SD1"; 1800 }; 1801 1802 pinctrl_sd2_default: sd2_default { 1803 function = "SD2"; 1804 groups = "SD2"; 1805 }; 1806 1807 pinctrl_emmc_default: emmc_default { 1808 function = "EMMC"; 1809 groups = "EMMC"; 1810 }; 1811 1812 pinctrl_emmcg8_default: emmcg8_default { 1813 function = "EMMCG8"; 1814 groups = "EMMCG8"; 1815 }; 1816 1817 pinctrl_sda1_default: sda1_default { 1818 function = "SDA1"; 1819 groups = "SDA1"; 1820 }; 1821 1822 pinctrl_sda2_default: sda2_default { 1823 function = "SDA2"; 1824 groups = "SDA2"; 1825 }; 1826 1827 pinctrl_sgps1_default: sgps1_default { 1828 function = "SGPS1"; 1829 groups = "SGPS1"; 1830 }; 1831 1832 pinctrl_sgps2_default: sgps2_default { 1833 function = "SGPS2"; 1834 groups = "SGPS2"; 1835 }; 1836 1837 pinctrl_sioonctrl_default: sioonctrl_default { 1838 function = "SIOONCTRL"; 1839 groups = "SIOONCTRL"; 1840 }; 1841 1842 pinctrl_siopbi_default: siopbi_default { 1843 function = "SIOPBI"; 1844 groups = "SIOPBI"; 1845 }; 1846 1847 pinctrl_siopbo_default: siopbo_default { 1848 function = "SIOPBO"; 1849 groups = "SIOPBO"; 1850 }; 1851 1852 pinctrl_siopwreq_default: siopwreq_default { 1853 function = "SIOPWREQ"; 1854 groups = "SIOPWREQ"; 1855 }; 1856 1857 pinctrl_siopwrgd_default: siopwrgd_default { 1858 function = "SIOPWRGD"; 1859 groups = "SIOPWRGD"; 1860 }; 1861 1862 pinctrl_sios3_default: sios3_default { 1863 function = "SIOS3"; 1864 groups = "SIOS3"; 1865 }; 1866 1867 pinctrl_sios5_default: sios5_default { 1868 function = "SIOS5"; 1869 groups = "SIOS5"; 1870 }; 1871 1872 pinctrl_siosci_default: siosci_default { 1873 function = "SIOSCI"; 1874 groups = "SIOSCI"; 1875 }; 1876 1877 pinctrl_spi1_default: spi1_default { 1878 function = "SPI1"; 1879 groups = "SPI1"; 1880 }; 1881 1882 pinctrl_spi1cs1_default: spi1cs1_default { 1883 function = "SPI1CS1"; 1884 groups = "SPI1CS1"; 1885 }; 1886 1887 pinctrl_spi1debug_default: spi1debug_default { 1888 function = "SPI1DEBUG"; 1889 groups = "SPI1DEBUG"; 1890 }; 1891 1892 pinctrl_spi1passthru_default: spi1passthru_default { 1893 function = "SPI1PASSTHRU"; 1894 groups = "SPI1PASSTHRU"; 1895 }; 1896 1897 pinctrl_spi2ck_default: spi2ck_default { 1898 function = "SPI2CK"; 1899 groups = "SPI2CK"; 1900 }; 1901 1902 pinctrl_spi2cs0_default: spi2cs0_default { 1903 function = "SPI2CS0"; 1904 groups = "SPI2CS0"; 1905 }; 1906 1907 pinctrl_spi2cs1_default: spi2cs1_default { 1908 function = "SPI2CS1"; 1909 groups = "SPI2CS1"; 1910 }; 1911 1912 pinctrl_spi2miso_default: spi2miso_default { 1913 function = "SPI2MISO"; 1914 groups = "SPI2MISO"; 1915 }; 1916 1917 pinctrl_spi2mosi_default: spi2mosi_default { 1918 function = "SPI2MOSI"; 1919 groups = "SPI2MOSI"; 1920 }; 1921 1922 pinctrl_timer3_default: timer3_default { 1923 function = "TIMER3"; 1924 groups = "TIMER3"; 1925 }; 1926 1927 pinctrl_timer4_default: timer4_default { 1928 function = "TIMER4"; 1929 groups = "TIMER4"; 1930 }; 1931 1932 pinctrl_timer5_default: timer5_default { 1933 function = "TIMER5"; 1934 groups = "TIMER5"; 1935 }; 1936 1937 pinctrl_timer6_default: timer6_default { 1938 function = "TIMER6"; 1939 groups = "TIMER6"; 1940 }; 1941 1942 pinctrl_timer7_default: timer7_default { 1943 function = "TIMER7"; 1944 groups = "TIMER7"; 1945 }; 1946 1947 pinctrl_timer8_default: timer8_default { 1948 function = "TIMER8"; 1949 groups = "TIMER8"; 1950 }; 1951 1952 pinctrl_txd1_default: txd1_default { 1953 function = "TXD1"; 1954 groups = "TXD1"; 1955 u-boot,dm-pre-reloc; 1956 }; 1957 1958 pinctrl_txd2_default: txd2_default { 1959 function = "TXD2"; 1960 groups = "TXD2"; 1961 u-boot,dm-pre-reloc; 1962 }; 1963 1964 pinctrl_txd3_default: txd3_default { 1965 function = "TXD3"; 1966 groups = "TXD3"; 1967 u-boot,dm-pre-reloc; 1968 }; 1969 1970 pinctrl_txd4_default: txd4_default { 1971 function = "TXD4"; 1972 groups = "TXD4"; 1973 u-boot,dm-pre-reloc; 1974 }; 1975 1976 pinctrl_uart6_default: uart6_default { 1977 function = "UART6"; 1978 groups = "UART6"; 1979 }; 1980 1981 pinctrl_usbcki_default: usbcki_default { 1982 function = "USBCKI"; 1983 groups = "USBCKI"; 1984 }; 1985 1986 pinctrl_usb2ad_default: usb2ad_default { 1987 function = "USB2AD"; 1988 groups = "USB2AD"; 1989 }; 1990 1991 pinctrl_usb2ah_default: usb2ah_default { 1992 function = "USB2AH"; 1993 groups = "USB2AH"; 1994 }; 1995 1996 pinctrl_usb11bhid_default: usb11bhid_default { 1997 function = "USB11BHID"; 1998 groups = "USB11BHID"; 1999 }; 2000 2001 pinctrl_usb2bh_default: usb2bh_default { 2002 function = "USB2BH"; 2003 groups = "USB2BH"; 2004 }; 2005 2006 pinctrl_vgabiosrom_default: vgabiosrom_default { 2007 function = "VGABIOSROM"; 2008 groups = "VGABIOSROM"; 2009 }; 2010 2011 pinctrl_vgahs_default: vgahs_default { 2012 function = "VGAHS"; 2013 groups = "VGAHS"; 2014 }; 2015 2016 pinctrl_vgavs_default: vgavs_default { 2017 function = "VGAVS"; 2018 groups = "VGAVS"; 2019 }; 2020 2021 pinctrl_vpi24_default: vpi24_default { 2022 function = "VPI24"; 2023 groups = "VPI24"; 2024 }; 2025 2026 pinctrl_vpo_default: vpo_default { 2027 function = "VPO"; 2028 groups = "VPO"; 2029 }; 2030 2031 pinctrl_wdtrst1_default: wdtrst1_default { 2032 function = "WDTRST1"; 2033 groups = "WDTRST1"; 2034 }; 2035 2036 pinctrl_wdtrst2_default: wdtrst2_default { 2037 function = "WDTRST2"; 2038 groups = "WDTRST2"; 2039 }; 2040 2041 pinctrl_pcie0rc_default: pcie0rc_default { 2042 function = "PCIE0RC"; 2043 groups = "PCIE0RC"; 2044 }; 2045 2046 pinctrl_pcie1rc_default: pcie1rc_default { 2047 function = "PCIE1RC"; 2048 groups = "PCIE1RC"; 2049 }; 2050}; 2051