1// SPDX-License-Identifier: GPL-2.0+ 2#include <dt-bindings/interrupt-controller/arm-gic.h> 3#include "skeleton.dtsi" 4 5/ { 6 model = "Aspeed BMC"; 7 compatible = "aspeed,ast2600"; 8 #address-cells = <1>; 9 #size-cells = <1>; 10 interrupt-parent = <&gic>; 11 12 aliases { 13 i2c0 = &i2c0; 14 i2c1 = &i2c1; 15 i2c2 = &i2c2; 16 i2c3 = &i2c3; 17 i2c4 = &i2c4; 18 i2c5 = &i2c5; 19 i2c6 = &i2c6; 20 i2c7 = &i2c7; 21 i2c8 = &i2c8; 22 i2c9 = &i2c9; 23 i2c10 = &i2c10; 24 i2c11 = &i2c11; 25 i2c12 = &i2c12; 26 i2c13 = &i2c13; 27 i2c14 = &i2c14; 28 i2c15 = &i2c15; 29 serial0 = &uart1; 30 serial1 = &uart2; 31 serial2 = &uart3; 32 serial3 = &uart4; 33 serial4 = &uart5; 34 serial5 = &uart6; 35 serial6 = &uart7; 36 serial7 = &uart8; 37 serial8 = &uart9; 38 serial9 = &uart10; 39 serial10 = &uart11; 40 serial11 = &uart12; 41 serial12 = &uart13; 42 }; 43 44 cpus { 45 #address-cells = <1>; 46 #size-cells = <0>; 47 enable-method = "aspeed,ast2600-smp"; 48 49 cpu@0 { 50 compatible = "arm,cortex-a7"; 51 device_type = "cpu"; 52 reg = <0>; 53 clock-frequency = <48000000>; 54 }; 55 56 cpu@1 { 57 compatible = "arm,cortex-a7"; 58 device_type = "cpu"; 59 reg = <1>; 60 clock-frequency = <48000000>; 61 }; 62 63 }; 64 65 timer { 66 compatible = "arm,armv7-timer"; 67 interrupt-parent = <&gic>; 68 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 69 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 70 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 71 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 72 clock-frequency = <25000000>; 73 }; 74 75 memory@80000000 { 76 device_type = "memory"; 77 reg = <0x80000000 0>; 78 }; 79 80 reserved-memory { 81 #address-cells = <1>; 82 #size-cells = <1>; 83 ranges; 84 85 gfx_memory: framebuffer { 86 size = <0x01000000>; 87 alignment = <0x01000000>; 88 compatible = "shared-dma-pool"; 89 reusable; 90 }; 91 92 video_memory: video { 93 size = <0x04000000>; 94 alignment = <0x01000000>; 95 compatible = "shared-dma-pool"; 96 no-map; 97 }; 98 }; 99 100 ahb { 101 compatible = "simple-bus"; 102 #address-cells = <1>; 103 #size-cells = <1>; 104 device_type = "soc"; 105 ranges; 106 107 gic: interrupt-controller@40461000 { 108 compatible = "arm,cortex-a7-gic"; 109 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 110 #interrupt-cells = <3>; 111 interrupt-controller; 112 interrupt-parent = <&gic>; 113 reg = <0x40461000 0x1000>, 114 <0x40462000 0x1000>, 115 <0x40464000 0x2000>, 116 <0x40466000 0x2000>; 117 }; 118 119 fmc: flash-controller@1e620000 { 120 reg = < 0x1e620000 0xc4 121 0x20000000 0x10000000 >; 122 #address-cells = <1>; 123 #size-cells = <0>; 124 compatible = "aspeed,ast2500-fmc"; 125 status = "disabled"; 126 interrupts = <19>; 127 flash@0 { 128 reg = < 0 >; 129 compatible = "jedec,spi-nor"; 130 status = "disabled"; 131 }; 132 flash@1 { 133 reg = < 1 >; 134 compatible = "jedec,spi-nor"; 135 status = "disabled"; 136 }; 137 flash@2 { 138 reg = < 2 >; 139 compatible = "jedec,spi-nor"; 140 status = "disabled"; 141 }; 142 }; 143 144 spi1: flash-controller@1e630000 { 145 reg = < 0x1e630000 0xc4 146 0x30000000 0x08000000 >; 147 #address-cells = <1>; 148 #size-cells = <0>; 149 compatible = "aspeed,ast2500-spi"; 150 status = "disabled"; 151 flash@0 { 152 reg = < 0 >; 153 compatible = "jedec,spi-nor"; 154 status = "disabled"; 155 }; 156 flash@1 { 157 reg = < 1 >; 158 compatible = "jedec,spi-nor"; 159 status = "disabled"; 160 }; 161 }; 162 163 spi2: flash-controller@1e631000 { 164 reg = < 0x1e631000 0xc4 165 0x38000000 0x08000000 >; 166 #address-cells = <1>; 167 #size-cells = <0>; 168 compatible = "aspeed,ast2500-spi"; 169 status = "disabled"; 170 flash@0 { 171 reg = < 0 >; 172 compatible = "jedec,spi-nor"; 173 status = "disabled"; 174 }; 175 flash@1 { 176 reg = < 1 >; 177 compatible = "jedec,spi-nor"; 178 status = "disabled"; 179 }; 180 }; 181 182 edac: sdram@1e6e0000 { 183 compatible = "aspeed,ast2600-sdram-edac"; 184 reg = <0x1e6e0000 0x174>; 185 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 186 }; 187 188 mdio: ethernet@1e650000 { 189 compatible = "aspeed,aspeed-mdio"; 190 reg = <0x1e650000 0x40>; 191 }; 192 193 mac0: ethernet@1e660000 { 194 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 195 reg = <0x1e660000 0x180>; 196#if 0 197, <0x1e650000 0x4>; 198#endif 199 interrupts = <2>; 200 status = "disabled"; 201 }; 202 203 mac2: ftgmac@1e670000 { 204 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 205 reg = <0x1e670000 0x180>; 206#if 0 207, <0x1e650010 0x4>; 208#endif 209 #address-cells = <1>; 210 #size-cells = <0>; 211 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 212#if 0 213 phy-handle = <&phy0>; 214#endif 215 status = "disabled"; 216 }; 217 218 mac1: ftgmac@1e680000 { 219 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 220 reg = <0x1e680000 0x180>, <0x1e650008 0x4>; 221 #address-cells = <1>; 222 #size-cells = <0>; 223 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 224#if 0 225 phy-handle = <&phy0>; 226#endif 227 status = "disabled"; 228 }; 229 230 mac3: ftgmac@1e690000 { 231 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 232 reg = <0x1e690000 0x180>, <0x1e650018 0x4>; 233 #address-cells = <1>; 234 #size-cells = <0>; 235 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 236#if 0 237 phy-handle = <&phy0>; 238#endif 239 status = "disabled"; 240 }; 241 242 243 apb { 244 compatible = "simple-bus"; 245 #address-cells = <1>; 246 #size-cells = <1>; 247 ranges; 248 249 syscon: syscon@1e6e2000 { 250 compatible = "aspeed,aspeed-scu", "aspeed,g6-scu", "syscon", "simple-mfd"; 251 reg = <0x1e6e2000 0x1000>; 252 #address-cells = <1>; 253 #size-cells = <1>; 254 #clock-cells = <1>; 255 #reset-cells = <1>; 256 ranges = <0 0x1e6e2000 0x1000>; 257 258 pinctrl: pinctrl { 259 compatible = "aspeed,g6-pinctrl"; 260 aspeed,external-nodes = <&gfx &lhc>; 261 262 }; 263 264 vga_scratch: scratch { 265 compatible = "aspeed,bmc-misc"; 266 }; 267 268 scu_ic0: interrupt-controller@0 { 269 #interrupt-cells = <1>; 270 compatible = "aspeed,ast2600-scu-ic"; 271 reg = <0x560 0x10>; 272 interrupt-parent = <&gic>; 273 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 274 interrupt-controller; 275 }; 276 277 scu_ic1: interrupt-controller@1 { 278 #interrupt-cells = <1>; 279 compatible = "aspeed,ast2600-scu-ic"; 280 reg = <0x570 0x10>; 281 interrupt-parent = <&gic>; 282 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 283 interrupt-controller; 284 }; 285 286 }; 287 288 smp-memram@0 { 289 compatible = "aspeed,ast2600-smpmem", "syscon"; 290 reg = <0x1e6e2180 0x40>; 291 }; 292 293 gfx: display@1e6e6000 { 294 compatible = "aspeed,ast2500-gfx", "syscon"; 295 reg = <0x1e6e6000 0x1000>; 296 reg-io-width = <4>; 297 }; 298 299 uart1: serial@1e783000 { 300 compatible = "ns16550a"; 301 reg = <0x1e783000 0x20>; 302 reg-shift = <2>; 303 no-loopback-test; 304 status = "disabled"; 305 }; 306 307 uart5: serial@1e784000 { 308 compatible = "ns16550a"; 309 reg = <0x1e784000 0x1000>; 310 reg-shift = <2>; 311 clock-frequency = <1846154>; 312 no-loopback-test; 313 }; 314 315 wdt1: watchdog@1e785000 { 316 compatible = "aspeed,ast2600-wdt"; 317 reg = <0x1e785000 0x40>; 318 }; 319 320 wdt2: watchdog@1e785040 { 321 compatible = "aspeed,ast2600-wdt"; 322 reg = <0x1e785040 0x40>; 323 }; 324 325 wdt3: watchdog@1e785080 { 326 compatible = "aspeed,ast2600-wdt"; 327 reg = <0x1e785080 0x40>; 328 }; 329 330 wdt4: watchdog@1e7850C0 { 331 compatible = "aspeed,ast2600-wdt"; 332 reg = <0x1e7850C0 0x40>; 333 }; 334 335 lpc: lpc@1e789000 { 336 compatible = "aspeed,ast-lpc", "simple-mfd", "syscon"; 337 reg = <0x1e789000 0x200>; 338 339 #address-cells = <1>; 340 #size-cells = <1>; 341 ranges = <0x0 0x1e789000 0x1000>; 342 343 lpc_bmc: lpc-bmc@0 { 344 compatible = "aspeed,ast2600-lpc-bmc", "simple-mfd", "syscon"; 345 reg = <0x0 0x80>; 346 reg-io-width = <4>; 347 #address-cells = <1>; 348 #size-cells = <1>; 349 ranges = <0x0 0x0 0x80>; 350 351 kcs1: kcs1@0 { 352 compatible = "aspeed,ast2600-kcs-bmc"; 353 reg = <0x0 0x80>; 354 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 355 kcs_chan = <1>; 356 kcs_addr = <0xCA0>; 357 status = "disabled"; 358 }; 359 360 kcs2: kcs2@0 { 361 compatible = "aspeed,ast2600-kcs-bmc"; 362 reg = <0x0 0x80>; 363 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 364 kcs_chan = <2>; 365 kcs_addr = <0xCA8>; 366 status = "disabled"; 367 }; 368 369 kcs3: kcs3@0 { 370 compatible = "aspeed,ast2600-kcs-bmc"; 371 reg = <0x0 0x80>; 372 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 373 kcs_chan = <3>; 374 kcs_addr = <0xCA2>; 375 }; 376 377 kcs4: kcs4@0 { 378 compatible = "aspeed,ast2600-kcs-bmc"; 379 reg = <0x0 0x120>; 380 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 381 kcs_chan = <4>; 382 kcs_addr = <0xCA4>; 383 status = "disabled"; 384 }; 385 386 }; 387 388 lpc_host: lpc-host@80 { 389 compatible = "aspeed,ast2600-lpc-host", "simple-mfd", "syscon"; 390 reg = <0x80 0x1e0>; 391 reg-io-width = <4>; 392 393 #address-cells = <1>; 394 #size-cells = <1>; 395 ranges = <0x0 0x80 0x1e0>; 396 397 lpc_ctrl: lpc-ctrl@0 { 398 compatible = "aspeed,ast2600-lpc-ctrl"; 399 reg = <0x0 0x80>; 400 status = "disabled"; 401 }; 402 403 lpc_snoop: lpc-snoop@0 { 404 compatible = "aspeed,ast2600-lpc-snoop"; 405 reg = <0x0 0x80>; 406 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 407 snoop-ports = <0x80>; 408 status = "disabled"; 409 }; 410 411 lhc: lhc@20 { 412 compatible = "aspeed,ast2600-lhc"; 413 reg = <0x20 0x24 0x48 0x8>; 414 }; 415 416 lpc_reset: reset-controller@18 { 417 compatible = "aspeed,ast2600-lpc-reset"; 418 reg = <0x18 0x4>; 419 #reset-cells = <1>; 420 status = "disabled"; 421 }; 422 423 ibt: ibt@c0 { 424 compatible = "aspeed,ast2600-ibt-bmc"; 425 reg = <0xc0 0x18>; 426 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 427 status = "disabled"; 428 }; 429 430 sio_regs: regs { 431 compatible = "aspeed,bmc-misc"; 432 }; 433 434 mbox: mbox@180 { 435 compatible = "aspeed,ast2600-mbox"; 436 reg = <0x180 0x5c>; 437 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 438 #mbox-cells = <1>; 439 status = "disabled"; 440 }; 441 }; 442 }; 443 444 uart2: serial@1e78d000 { 445 compatible = "ns16550a"; 446 reg = <0x1e78d000 0x20>; 447 reg-shift = <2>; 448 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 449 no-loopback-test; 450 status = "disabled"; 451 }; 452 453 uart3: serial@1e78e000 { 454 compatible = "ns16550a"; 455 reg = <0x1e78e000 0x20>; 456 reg-shift = <2>; 457 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 458 no-loopback-test; 459 status = "disabled"; 460 }; 461 462 uart4: serial@1e78f000 { 463 compatible = "ns16550a"; 464 reg = <0x1e78f000 0x20>; 465 reg-shift = <2>; 466 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 467 no-loopback-test; 468 status = "disabled"; 469 }; 470 471 i2c: bus@1e78a000 { 472 compatible = "simple-bus"; 473 #address-cells = <1>; 474 #size-cells = <1>; 475 ranges = <0 0x1e78a000 0x1000>; 476 }; 477 478 uart6: serial@1e790000 { 479 compatible = "ns16550a"; 480 reg = <0x1e790000 0x20>; 481 reg-shift = <2>; 482 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 483 no-loopback-test; 484 status = "disabled"; 485 }; 486 487 uart7: serial@1e790100 { 488 compatible = "ns16550a"; 489 reg = <0x1e790100 0x20>; 490 reg-shift = <2>; 491 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 492 no-loopback-test; 493 status = "disabled"; 494 }; 495 496 uart8: serial@1e790200 { 497 compatible = "ns16550a"; 498 reg = <0x1e790200 0x20>; 499 reg-shift = <2>; 500 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 501 no-loopback-test; 502 status = "disabled"; 503 }; 504 505 uart9: serial@1e790300 { 506 compatible = "ns16550a"; 507 reg = <0x1e790300 0x20>; 508 reg-shift = <2>; 509 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 510 no-loopback-test; 511 status = "disabled"; 512 }; 513 514 uart10: serial@1e790400 { 515 compatible = "ns16550a"; 516 reg = <0x1e790400 0x20>; 517 reg-shift = <2>; 518 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 519 no-loopback-test; 520 status = "disabled"; 521 }; 522 523 uart11: serial@1e790500 { 524 compatible = "ns16550a"; 525 reg = <0x1e790400 0x20>; 526 reg-shift = <2>; 527 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 528 no-loopback-test; 529 status = "disabled"; 530 }; 531 532 uart12: serial@1e790600 { 533 compatible = "ns16550a"; 534 reg = <0x1e790600 0x20>; 535 reg-shift = <2>; 536 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 537 no-loopback-test; 538 status = "disabled"; 539 }; 540 541 uart13: serial@1e790700 { 542 compatible = "ns16550a"; 543 reg = <0x1e790700 0x20>; 544 reg-shift = <2>; 545 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 546 no-loopback-test; 547 status = "disabled"; 548 }; 549 550 551 552 }; 553 554 }; 555 556}; 557 558&i2c { 559 i2cglobal: i2cg@00 { 560 compatible = "aspeed,ast2600-i2c-global", "syscon", "simple-mfd"; 561 reg = <0x0 0x40>; 562 563#if 0 564 new-mode; 565#endif 566 }; 567 568 i2c0: i2c@80 { 569 #address-cells = <1>; 570 #size-cells = <0>; 571 #interrupt-cells = <1>; 572 573 reg = <0x80 0x80 0xC00 0x20>; 574 compatible = "aspeed,ast2600-i2c-bus"; 575#if 0 576 compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 577 #compatible = "aspeed,ast2500-i2c-bus"; 578 #compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 579#endif 580 bus-frequency = <100000>; 581 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 582 }; 583 584 i2c1: i2c@100 { 585 #address-cells = <1>; 586 #size-cells = <0>; 587 #interrupt-cells = <1>; 588 589 reg = <0x100 0x80 0xC20 0x20>; 590 compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 591#if 0 592 #compatible = "aspeed,ast2500-i2c-bus"; 593 #compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 594#endif 595 bus-frequency = <100000>; 596 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 597 }; 598 599 i2c2: i2c@180 { 600 #address-cells = <1>; 601 #size-cells = <0>; 602 #interrupt-cells = <1>; 603 604 reg = <0x180 0x80 0xC40 0x20>; 605 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 606 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 607 bus-frequency = <100000>; 608 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 609 }; 610 611 i2c3: i2c@200 { 612 #address-cells = <1>; 613 #size-cells = <0>; 614 #interrupt-cells = <1>; 615 616 reg = <0x200 0x40 0xC60 0x20>; 617 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 618 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 619 bus-frequency = <100000>; 620 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 621 }; 622 623 i2c4: i2c@280 { 624 #address-cells = <1>; 625 #size-cells = <0>; 626 #interrupt-cells = <1>; 627 628 reg = <0x280 0x80 0xC80 0x20>; 629 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 630 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 631 bus-frequency = <100000>; 632 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 633 }; 634 635 i2c5: i2c@300 { 636 #address-cells = <1>; 637 #size-cells = <0>; 638 #interrupt-cells = <1>; 639 640 reg = <0x300 0x40 0xCA0 0x20>; 641 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 642 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 643 bus-frequency = <100000>; 644 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 645 }; 646 647 i2c6: i2c@380 { 648 #address-cells = <1>; 649 #size-cells = <0>; 650 #interrupt-cells = <1>; 651 652 reg = <0x380 0x80 0xCC0 0x20>; 653 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 654 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 655 bus-frequency = <100000>; 656 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 657 }; 658 659 i2c7: i2c@400 { 660 #address-cells = <1>; 661 #size-cells = <0>; 662 #interrupt-cells = <1>; 663 664 reg = <0x400 0x80 0xCE0 0x20>; 665 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 666 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 667 bus-frequency = <100000>; 668 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 669 }; 670 671 i2c8: i2c@480 { 672 #address-cells = <1>; 673 #size-cells = <0>; 674 #interrupt-cells = <1>; 675 676 reg = <0x480 0x80 0xD00 0x20>; 677 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 678 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 679 bus-frequency = <100000>; 680 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 681 }; 682 683 i2c9: i2c@500 { 684 #address-cells = <1>; 685 #size-cells = <0>; 686 #interrupt-cells = <1>; 687 688 reg = <0x500 0x80 0xD20 0x20>; 689 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 690 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 691 bus-frequency = <100000>; 692 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 693 status = "disabled"; 694 }; 695 696 i2c10: i2c@580 { 697 #address-cells = <1>; 698 #size-cells = <0>; 699 #interrupt-cells = <1>; 700 701 reg = <0x580 0x80 0xD40 0x20>; 702 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 703 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 704 bus-frequency = <100000>; 705 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 706 status = "disabled"; 707 }; 708 709 i2c11: i2c@600 { 710 #address-cells = <1>; 711 #size-cells = <0>; 712 #interrupt-cells = <1>; 713 714 reg = <0x600 0x80 0xD60 0x20>; 715 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 716 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 717 bus-frequency = <100000>; 718 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 719 status = "disabled"; 720 }; 721 722 i2c12: i2c@680 { 723 #address-cells = <1>; 724 #size-cells = <0>; 725 #interrupt-cells = <1>; 726 727 reg = <0x680 0x80 0xD80 0x20>; 728 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 729 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 730 bus-frequency = <100000>; 731 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 732 status = "disabled"; 733 }; 734 735 i2c13: i2c@700 { 736 #address-cells = <1>; 737 #size-cells = <0>; 738 #interrupt-cells = <1>; 739 740 reg = <0x700 0x80 0xDA0 0x20>; 741 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 742 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 743 bus-frequency = <100000>; 744 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 745 status = "disabled"; 746 }; 747 748 i2c14: i2c@780 { 749 #address-cells = <1>; 750 #size-cells = <0>; 751 #interrupt-cells = <1>; 752 753 reg = <0x780 0x80 0xDC0 0x20>; 754 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 755 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 756 bus-frequency = <100000>; 757 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 758 status = "disabled"; 759 }; 760 761 i2c15: i2c@800 { 762 #address-cells = <1>; 763 #size-cells = <0>; 764 #interrupt-cells = <1>; 765 766 reg = <0x800 0x80 0xDE0 0x20>; 767 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 768 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 769 bus-frequency = <100000>; 770 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 771 status = "disabled"; 772 }; 773 774}; 775 776&pinctrl { 777 pinctrl_acpi_default: acpi_default { 778 function = "ACPI"; 779 groups = "ACPI"; 780 }; 781 782 pinctrl_adc0_default: adc0_default { 783 function = "ADC0"; 784 groups = "ADC0"; 785 }; 786 787 pinctrl_adc1_default: adc1_default { 788 function = "ADC1"; 789 groups = "ADC1"; 790 }; 791 792 pinctrl_adc10_default: adc10_default { 793 function = "ADC10"; 794 groups = "ADC10"; 795 }; 796 797 pinctrl_adc11_default: adc11_default { 798 function = "ADC11"; 799 groups = "ADC11"; 800 }; 801 802 pinctrl_adc12_default: adc12_default { 803 function = "ADC12"; 804 groups = "ADC12"; 805 }; 806 807 pinctrl_adc13_default: adc13_default { 808 function = "ADC13"; 809 groups = "ADC13"; 810 }; 811 812 pinctrl_adc14_default: adc14_default { 813 function = "ADC14"; 814 groups = "ADC14"; 815 }; 816 817 pinctrl_adc15_default: adc15_default { 818 function = "ADC15"; 819 groups = "ADC15"; 820 }; 821 822 pinctrl_adc2_default: adc2_default { 823 function = "ADC2"; 824 groups = "ADC2"; 825 }; 826 827 pinctrl_adc3_default: adc3_default { 828 function = "ADC3"; 829 groups = "ADC3"; 830 }; 831 832 pinctrl_adc4_default: adc4_default { 833 function = "ADC4"; 834 groups = "ADC4"; 835 }; 836 837 pinctrl_adc5_default: adc5_default { 838 function = "ADC5"; 839 groups = "ADC5"; 840 }; 841 842 pinctrl_adc6_default: adc6_default { 843 function = "ADC6"; 844 groups = "ADC6"; 845 }; 846 847 pinctrl_adc7_default: adc7_default { 848 function = "ADC7"; 849 groups = "ADC7"; 850 }; 851 852 pinctrl_adc8_default: adc8_default { 853 function = "ADC8"; 854 groups = "ADC8"; 855 }; 856 857 pinctrl_adc9_default: adc9_default { 858 function = "ADC9"; 859 groups = "ADC9"; 860 }; 861 862 pinctrl_bmcint_default: bmcint_default { 863 function = "BMCINT"; 864 groups = "BMCINT"; 865 }; 866 867 pinctrl_ddcclk_default: ddcclk_default { 868 function = "DDCCLK"; 869 groups = "DDCCLK"; 870 }; 871 872 pinctrl_ddcdat_default: ddcdat_default { 873 function = "DDCDAT"; 874 groups = "DDCDAT"; 875 }; 876 877 pinctrl_espi_default: espi_default { 878 function = "ESPI"; 879 groups = "ESPI"; 880 }; 881 882 pinctrl_fwspics1_default: fwspics1_default { 883 function = "FWSPICS1"; 884 groups = "FWSPICS1"; 885 }; 886 887 pinctrl_fwspics2_default: fwspics2_default { 888 function = "FWSPICS2"; 889 groups = "FWSPICS2"; 890 }; 891 892 pinctrl_gpid0_default: gpid0_default { 893 function = "GPID0"; 894 groups = "GPID0"; 895 }; 896 897 pinctrl_gpid2_default: gpid2_default { 898 function = "GPID2"; 899 groups = "GPID2"; 900 }; 901 902 pinctrl_gpid4_default: gpid4_default { 903 function = "GPID4"; 904 groups = "GPID4"; 905 }; 906 907 pinctrl_gpid6_default: gpid6_default { 908 function = "GPID6"; 909 groups = "GPID6"; 910 }; 911 912 pinctrl_gpie0_default: gpie0_default { 913 function = "GPIE0"; 914 groups = "GPIE0"; 915 }; 916 917 pinctrl_gpie2_default: gpie2_default { 918 function = "GPIE2"; 919 groups = "GPIE2"; 920 }; 921 922 pinctrl_gpie4_default: gpie4_default { 923 function = "GPIE4"; 924 groups = "GPIE4"; 925 }; 926 927 pinctrl_gpie6_default: gpie6_default { 928 function = "GPIE6"; 929 groups = "GPIE6"; 930 }; 931 932 pinctrl_i2c10_default: i2c10_default { 933 function = "I2C10"; 934 groups = "I2C10"; 935 }; 936 937 pinctrl_i2c11_default: i2c11_default { 938 function = "I2C11"; 939 groups = "I2C11"; 940 }; 941 942 pinctrl_i2c12_default: i2c12_default { 943 function = "I2C12"; 944 groups = "I2C12"; 945 }; 946 947 pinctrl_i2c13_default: i2c13_default { 948 function = "I2C13"; 949 groups = "I2C13"; 950 }; 951 952 pinctrl_i2c14_default: i2c14_default { 953 function = "I2C14"; 954 groups = "I2C14"; 955 }; 956 957 pinctrl_i2c3_default: i2c3_default { 958 function = "I2C3"; 959 groups = "I2C3"; 960 }; 961 962 pinctrl_i2c4_default: i2c4_default { 963 function = "I2C4"; 964 groups = "I2C4"; 965 }; 966 967 pinctrl_i2c5_default: i2c5_default { 968 function = "I2C5"; 969 groups = "I2C5"; 970 }; 971 972 pinctrl_i2c6_default: i2c6_default { 973 function = "I2C6"; 974 groups = "I2C6"; 975 }; 976 977 pinctrl_i2c7_default: i2c7_default { 978 function = "I2C7"; 979 groups = "I2C7"; 980 }; 981 982 pinctrl_i2c8_default: i2c8_default { 983 function = "I2C8"; 984 groups = "I2C8"; 985 }; 986 987 pinctrl_i2c9_default: i2c9_default { 988 function = "I2C9"; 989 groups = "I2C9"; 990 }; 991 992 pinctrl_lad0_default: lad0_default { 993 function = "LAD0"; 994 groups = "LAD0"; 995 }; 996 997 pinctrl_lad1_default: lad1_default { 998 function = "LAD1"; 999 groups = "LAD1"; 1000 }; 1001 1002 pinctrl_lad2_default: lad2_default { 1003 function = "LAD2"; 1004 groups = "LAD2"; 1005 }; 1006 1007 pinctrl_lad3_default: lad3_default { 1008 function = "LAD3"; 1009 groups = "LAD3"; 1010 }; 1011 1012 pinctrl_lclk_default: lclk_default { 1013 function = "LCLK"; 1014 groups = "LCLK"; 1015 }; 1016 1017 pinctrl_lframe_default: lframe_default { 1018 function = "LFRAME"; 1019 groups = "LFRAME"; 1020 }; 1021 1022 pinctrl_lpchc_default: lpchc_default { 1023 function = "LPCHC"; 1024 groups = "LPCHC"; 1025 }; 1026 1027 pinctrl_lpcpd_default: lpcpd_default { 1028 function = "LPCPD"; 1029 groups = "LPCPD"; 1030 }; 1031 1032 pinctrl_lpcplus_default: lpcplus_default { 1033 function = "LPCPLUS"; 1034 groups = "LPCPLUS"; 1035 }; 1036 1037 pinctrl_lpcpme_default: lpcpme_default { 1038 function = "LPCPME"; 1039 groups = "LPCPME"; 1040 }; 1041 1042 pinctrl_lpcrst_default: lpcrst_default { 1043 function = "LPCRST"; 1044 groups = "LPCRST"; 1045 }; 1046 1047 pinctrl_lpcsmi_default: lpcsmi_default { 1048 function = "LPCSMI"; 1049 groups = "LPCSMI"; 1050 }; 1051 1052 pinctrl_lsirq_default: lsirq_default { 1053 function = "LSIRQ"; 1054 groups = "LSIRQ"; 1055 }; 1056 1057 pinctrl_mac1link_default: mac1link_default { 1058 function = "MAC1LINK"; 1059 groups = "MAC1LINK"; 1060 }; 1061 1062 pinctrl_mac2link_default: mac2link_default { 1063 function = "MAC2LINK"; 1064 groups = "MAC2LINK"; 1065 }; 1066 1067 pinctrl_mac3link_default: mac3link_default { 1068 function = "MAC3LINK"; 1069 groups = "MAC3LINK"; 1070 }; 1071 1072 pinctrl_mac4link_default: mac4link_default { 1073 function = "MAC4LINK"; 1074 groups = "MAC4LINK"; 1075 }; 1076 1077 pinctrl_mdio1_default: mdio1_default { 1078 function = "MDIO1"; 1079 groups = "MDIO1"; 1080 }; 1081 1082 pinctrl_mdio2_default: mdio2_default { 1083 function = "MDIO2"; 1084 groups = "MDIO2"; 1085 }; 1086 1087 pinctrl_mdio3_default: mdio3_default { 1088 function = "MDIO3"; 1089 groups = "MDIO3"; 1090 }; 1091 1092 pinctrl_mdio4_default: mdio4_default { 1093 function = "MDIO4"; 1094 groups = "MDIO4"; 1095 }; 1096 1097 pinctrl_ncts1_default: ncts1_default { 1098 function = "NCTS1"; 1099 groups = "NCTS1"; 1100 }; 1101 1102 pinctrl_ncts2_default: ncts2_default { 1103 function = "NCTS2"; 1104 groups = "NCTS2"; 1105 }; 1106 1107 pinctrl_ncts3_default: ncts3_default { 1108 function = "NCTS3"; 1109 groups = "NCTS3"; 1110 }; 1111 1112 pinctrl_ncts4_default: ncts4_default { 1113 function = "NCTS4"; 1114 groups = "NCTS4"; 1115 }; 1116 1117 pinctrl_ndcd1_default: ndcd1_default { 1118 function = "NDCD1"; 1119 groups = "NDCD1"; 1120 }; 1121 1122 pinctrl_ndcd2_default: ndcd2_default { 1123 function = "NDCD2"; 1124 groups = "NDCD2"; 1125 }; 1126 1127 pinctrl_ndcd3_default: ndcd3_default { 1128 function = "NDCD3"; 1129 groups = "NDCD3"; 1130 }; 1131 1132 pinctrl_ndcd4_default: ndcd4_default { 1133 function = "NDCD4"; 1134 groups = "NDCD4"; 1135 }; 1136 1137 pinctrl_ndsr1_default: ndsr1_default { 1138 function = "NDSR1"; 1139 groups = "NDSR1"; 1140 }; 1141 1142 pinctrl_ndsr2_default: ndsr2_default { 1143 function = "NDSR2"; 1144 groups = "NDSR2"; 1145 }; 1146 1147 pinctrl_ndsr3_default: ndsr3_default { 1148 function = "NDSR3"; 1149 groups = "NDSR3"; 1150 }; 1151 1152 pinctrl_ndsr4_default: ndsr4_default { 1153 function = "NDSR4"; 1154 groups = "NDSR4"; 1155 }; 1156 1157 pinctrl_ndtr1_default: ndtr1_default { 1158 function = "NDTR1"; 1159 groups = "NDTR1"; 1160 }; 1161 1162 pinctrl_ndtr2_default: ndtr2_default { 1163 function = "NDTR2"; 1164 groups = "NDTR2"; 1165 }; 1166 1167 pinctrl_ndtr3_default: ndtr3_default { 1168 function = "NDTR3"; 1169 groups = "NDTR3"; 1170 }; 1171 1172 pinctrl_ndtr4_default: ndtr4_default { 1173 function = "NDTR4"; 1174 groups = "NDTR4"; 1175 }; 1176 1177 pinctrl_nri1_default: nri1_default { 1178 function = "NRI1"; 1179 groups = "NRI1"; 1180 }; 1181 1182 pinctrl_nri2_default: nri2_default { 1183 function = "NRI2"; 1184 groups = "NRI2"; 1185 }; 1186 1187 pinctrl_nri3_default: nri3_default { 1188 function = "NRI3"; 1189 groups = "NRI3"; 1190 }; 1191 1192 pinctrl_nri4_default: nri4_default { 1193 function = "NRI4"; 1194 groups = "NRI4"; 1195 }; 1196 1197 pinctrl_nrts1_default: nrts1_default { 1198 function = "NRTS1"; 1199 groups = "NRTS1"; 1200 }; 1201 1202 pinctrl_nrts2_default: nrts2_default { 1203 function = "NRTS2"; 1204 groups = "NRTS2"; 1205 }; 1206 1207 pinctrl_nrts3_default: nrts3_default { 1208 function = "NRTS3"; 1209 groups = "NRTS3"; 1210 }; 1211 1212 pinctrl_nrts4_default: nrts4_default { 1213 function = "NRTS4"; 1214 groups = "NRTS4"; 1215 }; 1216 1217 pinctrl_oscclk_default: oscclk_default { 1218 function = "OSCCLK"; 1219 groups = "OSCCLK"; 1220 }; 1221 1222 pinctrl_pewake_default: pewake_default { 1223 function = "PEWAKE"; 1224 groups = "PEWAKE"; 1225 }; 1226 1227 pinctrl_pnor_default: pnor_default { 1228 function = "PNOR"; 1229 groups = "PNOR"; 1230 }; 1231 1232 pinctrl_pwm0_default: pwm0_default { 1233 function = "PWM0"; 1234 groups = "PWM0"; 1235 }; 1236 1237 pinctrl_pwm1_default: pwm1_default { 1238 function = "PWM1"; 1239 groups = "PWM1"; 1240 }; 1241 1242 pinctrl_pwm2_default: pwm2_default { 1243 function = "PWM2"; 1244 groups = "PWM2"; 1245 }; 1246 1247 pinctrl_pwm3_default: pwm3_default { 1248 function = "PWM3"; 1249 groups = "PWM3"; 1250 }; 1251 1252 pinctrl_pwm4_default: pwm4_default { 1253 function = "PWM4"; 1254 groups = "PWM4"; 1255 }; 1256 1257 pinctrl_pwm5_default: pwm5_default { 1258 function = "PWM5"; 1259 groups = "PWM5"; 1260 }; 1261 1262 pinctrl_pwm6_default: pwm6_default { 1263 function = "PWM6"; 1264 groups = "PWM6"; 1265 }; 1266 1267 pinctrl_pwm7_default: pwm7_default { 1268 function = "PWM7"; 1269 groups = "PWM7"; 1270 }; 1271 1272 pinctrl_rgmii1_default: rgmii1_default { 1273 function = "RGMII1"; 1274 groups = "RGMII1"; 1275 }; 1276 1277 pinctrl_rgmii2_default: rgmii2_default { 1278 function = "RGMII2"; 1279 groups = "RGMII2"; 1280 }; 1281 1282 pinctrl_rmii1_default: rmii1_default { 1283 function = "RMII1"; 1284 groups = "RMII1"; 1285 }; 1286 1287 pinctrl_rmii2_default: rmii2_default { 1288 function = "RMII2"; 1289 groups = "RMII2"; 1290 }; 1291 1292 pinctrl_rxd1_default: rxd1_default { 1293 function = "RXD1"; 1294 groups = "RXD1"; 1295 }; 1296 1297 pinctrl_rxd2_default: rxd2_default { 1298 function = "RXD2"; 1299 groups = "RXD2"; 1300 }; 1301 1302 pinctrl_rxd3_default: rxd3_default { 1303 function = "RXD3"; 1304 groups = "RXD3"; 1305 }; 1306 1307 pinctrl_rxd4_default: rxd4_default { 1308 function = "RXD4"; 1309 groups = "RXD4"; 1310 }; 1311 1312 pinctrl_salt1_default: salt1_default { 1313 function = "SALT1"; 1314 groups = "SALT1"; 1315 }; 1316 1317 pinctrl_salt10_default: salt10_default { 1318 function = "SALT10"; 1319 groups = "SALT10"; 1320 }; 1321 1322 pinctrl_salt11_default: salt11_default { 1323 function = "SALT11"; 1324 groups = "SALT11"; 1325 }; 1326 1327 pinctrl_salt12_default: salt12_default { 1328 function = "SALT12"; 1329 groups = "SALT12"; 1330 }; 1331 1332 pinctrl_salt13_default: salt13_default { 1333 function = "SALT13"; 1334 groups = "SALT13"; 1335 }; 1336 1337 pinctrl_salt14_default: salt14_default { 1338 function = "SALT14"; 1339 groups = "SALT14"; 1340 }; 1341 1342 pinctrl_salt2_default: salt2_default { 1343 function = "SALT2"; 1344 groups = "SALT2"; 1345 }; 1346 1347 pinctrl_salt3_default: salt3_default { 1348 function = "SALT3"; 1349 groups = "SALT3"; 1350 }; 1351 1352 pinctrl_salt4_default: salt4_default { 1353 function = "SALT4"; 1354 groups = "SALT4"; 1355 }; 1356 1357 pinctrl_salt5_default: salt5_default { 1358 function = "SALT5"; 1359 groups = "SALT5"; 1360 }; 1361 1362 pinctrl_salt6_default: salt6_default { 1363 function = "SALT6"; 1364 groups = "SALT6"; 1365 }; 1366 1367 pinctrl_salt7_default: salt7_default { 1368 function = "SALT7"; 1369 groups = "SALT7"; 1370 }; 1371 1372 pinctrl_salt8_default: salt8_default { 1373 function = "SALT8"; 1374 groups = "SALT8"; 1375 }; 1376 1377 pinctrl_salt9_default: salt9_default { 1378 function = "SALT9"; 1379 groups = "SALT9"; 1380 }; 1381 1382 pinctrl_scl1_default: scl1_default { 1383 function = "SCL1"; 1384 groups = "SCL1"; 1385 }; 1386 1387 pinctrl_scl2_default: scl2_default { 1388 function = "SCL2"; 1389 groups = "SCL2"; 1390 }; 1391 1392 pinctrl_sd1_default: sd1_default { 1393 function = "SD1"; 1394 groups = "SD1"; 1395 }; 1396 1397 pinctrl_sd2_default: sd2_default { 1398 function = "SD2"; 1399 groups = "SD2"; 1400 }; 1401 1402 pinctrl_sda1_default: sda1_default { 1403 function = "SDA1"; 1404 groups = "SDA1"; 1405 }; 1406 1407 pinctrl_sda2_default: sda2_default { 1408 function = "SDA2"; 1409 groups = "SDA2"; 1410 }; 1411 1412 pinctrl_sgps1_default: sgps1_default { 1413 function = "SGPS1"; 1414 groups = "SGPS1"; 1415 }; 1416 1417 pinctrl_sgps2_default: sgps2_default { 1418 function = "SGPS2"; 1419 groups = "SGPS2"; 1420 }; 1421 1422 pinctrl_sioonctrl_default: sioonctrl_default { 1423 function = "SIOONCTRL"; 1424 groups = "SIOONCTRL"; 1425 }; 1426 1427 pinctrl_siopbi_default: siopbi_default { 1428 function = "SIOPBI"; 1429 groups = "SIOPBI"; 1430 }; 1431 1432 pinctrl_siopbo_default: siopbo_default { 1433 function = "SIOPBO"; 1434 groups = "SIOPBO"; 1435 }; 1436 1437 pinctrl_siopwreq_default: siopwreq_default { 1438 function = "SIOPWREQ"; 1439 groups = "SIOPWREQ"; 1440 }; 1441 1442 pinctrl_siopwrgd_default: siopwrgd_default { 1443 function = "SIOPWRGD"; 1444 groups = "SIOPWRGD"; 1445 }; 1446 1447 pinctrl_sios3_default: sios3_default { 1448 function = "SIOS3"; 1449 groups = "SIOS3"; 1450 }; 1451 1452 pinctrl_sios5_default: sios5_default { 1453 function = "SIOS5"; 1454 groups = "SIOS5"; 1455 }; 1456 1457 pinctrl_siosci_default: siosci_default { 1458 function = "SIOSCI"; 1459 groups = "SIOSCI"; 1460 }; 1461 1462 pinctrl_spi1_default: spi1_default { 1463 function = "SPI1"; 1464 groups = "SPI1"; 1465 }; 1466 1467 pinctrl_spi1cs1_default: spi1cs1_default { 1468 function = "SPI1CS1"; 1469 groups = "SPI1CS1"; 1470 }; 1471 1472 pinctrl_spi1debug_default: spi1debug_default { 1473 function = "SPI1DEBUG"; 1474 groups = "SPI1DEBUG"; 1475 }; 1476 1477 pinctrl_spi1passthru_default: spi1passthru_default { 1478 function = "SPI1PASSTHRU"; 1479 groups = "SPI1PASSTHRU"; 1480 }; 1481 1482 pinctrl_spi2ck_default: spi2ck_default { 1483 function = "SPI2CK"; 1484 groups = "SPI2CK"; 1485 }; 1486 1487 pinctrl_spi2cs0_default: spi2cs0_default { 1488 function = "SPI2CS0"; 1489 groups = "SPI2CS0"; 1490 }; 1491 1492 pinctrl_spi2cs1_default: spi2cs1_default { 1493 function = "SPI2CS1"; 1494 groups = "SPI2CS1"; 1495 }; 1496 1497 pinctrl_spi2miso_default: spi2miso_default { 1498 function = "SPI2MISO"; 1499 groups = "SPI2MISO"; 1500 }; 1501 1502 pinctrl_spi2mosi_default: spi2mosi_default { 1503 function = "SPI2MOSI"; 1504 groups = "SPI2MOSI"; 1505 }; 1506 1507 pinctrl_timer3_default: timer3_default { 1508 function = "TIMER3"; 1509 groups = "TIMER3"; 1510 }; 1511 1512 pinctrl_timer4_default: timer4_default { 1513 function = "TIMER4"; 1514 groups = "TIMER4"; 1515 }; 1516 1517 pinctrl_timer5_default: timer5_default { 1518 function = "TIMER5"; 1519 groups = "TIMER5"; 1520 }; 1521 1522 pinctrl_timer6_default: timer6_default { 1523 function = "TIMER6"; 1524 groups = "TIMER6"; 1525 }; 1526 1527 pinctrl_timer7_default: timer7_default { 1528 function = "TIMER7"; 1529 groups = "TIMER7"; 1530 }; 1531 1532 pinctrl_timer8_default: timer8_default { 1533 function = "TIMER8"; 1534 groups = "TIMER8"; 1535 }; 1536 1537 pinctrl_txd1_default: txd1_default { 1538 function = "TXD1"; 1539 groups = "TXD1"; 1540 }; 1541 1542 pinctrl_txd2_default: txd2_default { 1543 function = "TXD2"; 1544 groups = "TXD2"; 1545 }; 1546 1547 pinctrl_txd3_default: txd3_default { 1548 function = "TXD3"; 1549 groups = "TXD3"; 1550 }; 1551 1552 pinctrl_txd4_default: txd4_default { 1553 function = "TXD4"; 1554 groups = "TXD4"; 1555 }; 1556 1557 pinctrl_uart6_default: uart6_default { 1558 function = "UART6"; 1559 groups = "UART6"; 1560 }; 1561 1562 pinctrl_usbcki_default: usbcki_default { 1563 function = "USBCKI"; 1564 groups = "USBCKI"; 1565 }; 1566 1567 pinctrl_usb2ah_default: usb2ah_default { 1568 function = "USB2AH"; 1569 groups = "USB2AH"; 1570 }; 1571 1572 pinctrl_usb11bhid_default: usb11bhid_default { 1573 function = "USB11BHID"; 1574 groups = "USB11BHID"; 1575 }; 1576 1577 pinctrl_usb2bh_default: usb2bh_default { 1578 function = "USB2BH"; 1579 groups = "USB2BH"; 1580 }; 1581 1582 pinctrl_vgabiosrom_default: vgabiosrom_default { 1583 function = "VGABIOSROM"; 1584 groups = "VGABIOSROM"; 1585 }; 1586 1587 pinctrl_vgahs_default: vgahs_default { 1588 function = "VGAHS"; 1589 groups = "VGAHS"; 1590 }; 1591 1592 pinctrl_vgavs_default: vgavs_default { 1593 function = "VGAVS"; 1594 groups = "VGAVS"; 1595 }; 1596 1597 pinctrl_vpi24_default: vpi24_default { 1598 function = "VPI24"; 1599 groups = "VPI24"; 1600 }; 1601 1602 pinctrl_vpo_default: vpo_default { 1603 function = "VPO"; 1604 groups = "VPO"; 1605 }; 1606 1607 pinctrl_wdtrst1_default: wdtrst1_default { 1608 function = "WDTRST1"; 1609 groups = "WDTRST1"; 1610 }; 1611 1612 pinctrl_wdtrst2_default: wdtrst2_default { 1613 function = "WDTRST2"; 1614 groups = "WDTRST2"; 1615 }; 1616}; 1617