1// SPDX-License-Identifier: GPL-2.0+ 2#include <dt-bindings/interrupt-controller/arm-gic.h> 3#include "skeleton.dtsi" 4 5/ { 6 model = "Aspeed BMC"; 7 compatible = "aspeed,ast2600"; 8 #address-cells = <1>; 9 #size-cells = <1>; 10 11 aliases { 12 i2c0 = &i2c0; 13 i2c1 = &i2c1; 14 i2c2 = &i2c2; 15 i2c3 = &i2c3; 16 i2c4 = &i2c4; 17 i2c5 = &i2c5; 18 i2c6 = &i2c6; 19 i2c7 = &i2c7; 20 i2c8 = &i2c8; 21 i2c9 = &i2c9; 22 i2c10 = &i2c10; 23 i2c11 = &i2c11; 24 i2c12 = &i2c12; 25 i2c13 = &i2c13; 26 i2c14 = &i2c14; 27 i2c15 = &i2c15; 28 serial0 = &uart1; 29 serial1 = &uart2; 30 serial2 = &uart3; 31 serial3 = &uart4; 32 serial4 = &uart5; 33 serial5 = &uart6; 34 serial6 = &uart7; 35 serial7 = &uart8; 36 serial8 = &uart9; 37 serial9 = &uart10; 38 serial10 = &uart11; 39 serial11 = &uart12; 40 serial12 = &uart13; 41 }; 42 43 cpus { 44 #address-cells = <1>; 45 #size-cells = <0>; 46 enable-method = "aspeed,ast2600-smp"; 47 48 cpu@0 { 49 compatible = "arm,cortex-a7"; 50 device_type = "cpu"; 51 reg = <0>; 52 clock-frequency = <48000000>; 53 }; 54 55 cpu@1 { 56 compatible = "arm,cortex-a7"; 57 device_type = "cpu"; 58 reg = <1>; 59 clock-frequency = <48000000>; 60 }; 61 62 }; 63 64 timer { 65 compatible = "arm,armv7-timer"; 66 interrupt-parent = <&gic>; 67 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 68 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 69 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 70 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 71 clock-frequency = <25000000>; 72 }; 73 74 memory@80000000 { 75 device_type = "memory"; 76 reg = <0x80000000 0>; 77 }; 78 79 reserved-memory { 80 #address-cells = <1>; 81 #size-cells = <1>; 82 ranges; 83 84 gfx_memory: framebuffer { 85 size = <0x01000000>; 86 alignment = <0x01000000>; 87 compatible = "shared-dma-pool"; 88 reusable; 89 }; 90 91 video_memory: video { 92 size = <0x04000000>; 93 alignment = <0x01000000>; 94 compatible = "shared-dma-pool"; 95 no-map; 96 }; 97 }; 98 99 ahb { 100 compatible = "simple-bus"; 101 #address-cells = <1>; 102 #size-cells = <1>; 103 device_type = "soc"; 104 ranges; 105 106 gic: interrupt-controller@40461000 { 107 compatible = "arm,cortex-a7-gic"; 108 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 109 #interrupt-cells = <3>; 110 interrupt-controller; 111 interrupt-parent = <&gic>; 112 reg = <0x40461000 0x1000>, 113 <0x40462000 0x1000>, 114 <0x40464000 0x2000>, 115 <0x40466000 0x2000>; 116 }; 117 118 119 edac: sdram@1e6e0000 { 120 compatible = "aspeed,ast2600-sdram-edac"; 121 reg = <0x1e6e0000 0x174>; 122 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 123 }; 124 125 mac0: ftgmac@1e660000 { 126 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 127 reg = <0x1e660000 0x180>, <0x1e650000 0x4>; 128 #address-cells = <1>; 129 #size-cells = <0>; 130 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 131#if 0 132 phy-handle = <&phy0>; 133#endif 134 }; 135 136 mac2: ftgmac@1e670000 { 137 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 138 reg = <0x1e670000 0x180>, <0x1e650010 0x4>; 139 #address-cells = <1>; 140 #size-cells = <0>; 141 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 142#if 0 143 phy-handle = <&phy0>; 144#endif 145 status = "disabled"; 146 }; 147 148 mac1: ftgmac@1e680000 { 149 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 150 reg = <0x1e680000 0x180>, <0x1e650008 0x4>; 151 #address-cells = <1>; 152 #size-cells = <0>; 153 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 154#if 0 155 phy-handle = <&phy0>; 156#endif 157 status = "disabled"; 158 }; 159 160 mac3: ftgmac@1e690000 { 161 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 162 reg = <0x1e690000 0x180>, <0x1e650018 0x4>; 163 #address-cells = <1>; 164 #size-cells = <0>; 165 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 166#if 0 167 phy-handle = <&phy0>; 168#endif 169 status = "disabled"; 170 }; 171 172 173 apb { 174 compatible = "simple-bus"; 175 #address-cells = <1>; 176 #size-cells = <1>; 177 ranges; 178 179 syscon: syscon@1e6e2000 { 180 compatible = "aspeed,aspeed-scu", "aspeed,ast2600-scu", "syscon", "simple-mfd"; 181 reg = <0x1e6e2000 0x1000>; 182 #address-cells = <1>; 183 #size-cells = <1>; 184 #clock-cells = <1>; 185 #reset-cells = <1>; 186 ranges = <0 0x1e6e2000 0x1000>; 187 188 vga_scratch: scratch { 189 compatible = "aspeed,bmc-misc"; 190 }; 191 192 scu_ic0: interrupt-controller@0 { 193 #interrupt-cells = <1>; 194 compatible = "aspeed,ast2600-scu-ic"; 195 reg = <0x560 0x10>; 196 interrupt-parent = <&gic>; 197 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 198 interrupt-controller; 199 }; 200 201 scu_ic1: interrupt-controller@1 { 202 #interrupt-cells = <1>; 203 compatible = "aspeed,ast2600-scu-ic"; 204 reg = <0x570 0x10>; 205 interrupt-parent = <&gic>; 206 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 207 interrupt-controller; 208 }; 209 210 }; 211 212 smp-memram@0 { 213 compatible = "aspeed,ast2600-smpmem", "syscon"; 214 reg = <0x1e6e2180 0x40>; 215 }; 216 217 218 uart1: serial@1e783000 { 219 compatible = "ns16550a"; 220 reg = <0x1e783000 0x20>; 221 reg-shift = <2>; 222 no-loopback-test; 223 status = "disabled"; 224 }; 225 226 uart5: serial@1e784000 { 227 compatible = "ns16550a"; 228 reg = <0x1e784000 0x1000>; 229 reg-shift = <2>; 230 clock-frequency = <1846154>; 231 no-loopback-test; 232 }; 233 234 wdt1: watchdog@1e785000 { 235 compatible = "aspeed,ast2600-wdt"; 236 reg = <0x1e785000 0x40>; 237 }; 238 239 wdt2: watchdog@1e785040 { 240 compatible = "aspeed,ast2600-wdt"; 241 reg = <0x1e785040 0x40>; 242 }; 243 244 wdt3: watchdog@1e785080 { 245 compatible = "aspeed,ast2600-wdt"; 246 reg = <0x1e785080 0x40>; 247 }; 248 249 wdt4: watchdog@1e7850C0 { 250 compatible = "aspeed,ast2600-wdt"; 251 reg = <0x1e7850C0 0x40>; 252 }; 253 254 lpc: lpc@1e789000 { 255 compatible = "aspeed,ast-lpc", "simple-mfd", "syscon"; 256 reg = <0x1e789000 0x200>; 257 258 #address-cells = <1>; 259 #size-cells = <1>; 260 ranges = <0x0 0x1e789000 0x1000>; 261 262 lpc_bmc: lpc-bmc@0 { 263 compatible = "aspeed,ast2600-lpc-bmc", "simple-mfd", "syscon"; 264 reg = <0x0 0x80>; 265 reg-io-width = <4>; 266 #address-cells = <1>; 267 #size-cells = <1>; 268 ranges = <0x0 0x0 0x80>; 269 270 kcs1: kcs1@0 { 271 compatible = "aspeed,ast2600-kcs-bmc"; 272 reg = <0x0 0x80>; 273 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 274 kcs_chan = <1>; 275 kcs_addr = <0xCA0>; 276 status = "disabled"; 277 }; 278 279 kcs2: kcs2@0 { 280 compatible = "aspeed,ast2600-kcs-bmc"; 281 reg = <0x0 0x80>; 282 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 283 kcs_chan = <2>; 284 kcs_addr = <0xCA8>; 285 status = "disabled"; 286 }; 287 288 kcs3: kcs3@0 { 289 compatible = "aspeed,ast2600-kcs-bmc"; 290 reg = <0x0 0x80>; 291 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 292 kcs_chan = <3>; 293 kcs_addr = <0xCA2>; 294 }; 295 296 kcs4: kcs4@0 { 297 compatible = "aspeed,ast2600-kcs-bmc"; 298 reg = <0x0 0x120>; 299 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 300 kcs_chan = <4>; 301 kcs_addr = <0xCA4>; 302 status = "disabled"; 303 }; 304 305 }; 306 307 lpc_host: lpc-host@80 { 308 compatible = "aspeed,ast2600-lpc-host", "simple-mfd", "syscon"; 309 reg = <0x80 0x1e0>; 310 reg-io-width = <4>; 311 312 #address-cells = <1>; 313 #size-cells = <1>; 314 ranges = <0x0 0x80 0x1e0>; 315 316 lpc_ctrl: lpc-ctrl@0 { 317 compatible = "aspeed,ast2600-lpc-ctrl"; 318 reg = <0x0 0x80>; 319 status = "disabled"; 320 }; 321 322 lpc_snoop: lpc-snoop@0 { 323 compatible = "aspeed,ast2600-lpc-snoop"; 324 reg = <0x0 0x80>; 325 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 326 snoop-ports = <0x80>; 327 status = "disabled"; 328 }; 329 330 lhc: lhc@20 { 331 compatible = "aspeed,ast2600-lhc"; 332 reg = <0x20 0x24 0x48 0x8>; 333 }; 334 335 lpc_reset: reset-controller@18 { 336 compatible = "aspeed,ast2600-lpc-reset"; 337 reg = <0x18 0x4>; 338 #reset-cells = <1>; 339 status = "disabled"; 340 }; 341 342 ibt: ibt@c0 { 343 compatible = "aspeed,ast2600-ibt-bmc"; 344 reg = <0xc0 0x18>; 345 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 346 status = "disabled"; 347 }; 348 349 sio_regs: regs { 350 compatible = "aspeed,bmc-misc"; 351 }; 352 353 mbox: mbox@180 { 354 compatible = "aspeed,ast2600-mbox"; 355 reg = <0x180 0x5c>; 356 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 357 #mbox-cells = <1>; 358 status = "disabled"; 359 }; 360 }; 361 }; 362 363 uart2: serial@1e78d000 { 364 compatible = "ns16550a"; 365 reg = <0x1e78d000 0x20>; 366 reg-shift = <2>; 367 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 368 no-loopback-test; 369 status = "disabled"; 370 }; 371 372 uart3: serial@1e78e000 { 373 compatible = "ns16550a"; 374 reg = <0x1e78e000 0x20>; 375 reg-shift = <2>; 376 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 377 no-loopback-test; 378 status = "disabled"; 379 }; 380 381 uart4: serial@1e78f000 { 382 compatible = "ns16550a"; 383 reg = <0x1e78f000 0x20>; 384 reg-shift = <2>; 385 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 386 no-loopback-test; 387 status = "disabled"; 388 }; 389 390 i2c: bus@1e78a000 { 391 compatible = "simple-bus"; 392 #address-cells = <1>; 393 #size-cells = <1>; 394 ranges = <0 0x1e78a000 0x1000>; 395 }; 396 397 uart6: serial@1e790000 { 398 compatible = "ns16550a"; 399 reg = <0x1e790000 0x20>; 400 reg-shift = <2>; 401 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 402 no-loopback-test; 403 status = "disabled"; 404 }; 405 406 uart7: serial@1e790100 { 407 compatible = "ns16550a"; 408 reg = <0x1e790100 0x20>; 409 reg-shift = <2>; 410 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 411 no-loopback-test; 412 status = "disabled"; 413 }; 414 415 uart8: serial@1e790200 { 416 compatible = "ns16550a"; 417 reg = <0x1e790200 0x20>; 418 reg-shift = <2>; 419 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 420 no-loopback-test; 421 status = "disabled"; 422 }; 423 424 uart9: serial@1e790300 { 425 compatible = "ns16550a"; 426 reg = <0x1e790300 0x20>; 427 reg-shift = <2>; 428 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 429 no-loopback-test; 430 status = "disabled"; 431 }; 432 433 uart10: serial@1e790400 { 434 compatible = "ns16550a"; 435 reg = <0x1e790400 0x20>; 436 reg-shift = <2>; 437 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 438 no-loopback-test; 439 status = "disabled"; 440 }; 441 442 uart11: serial@1e790500 { 443 compatible = "ns16550a"; 444 reg = <0x1e790400 0x20>; 445 reg-shift = <2>; 446 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 447 no-loopback-test; 448 status = "disabled"; 449 }; 450 451 uart12: serial@1e790600 { 452 compatible = "ns16550a"; 453 reg = <0x1e790600 0x20>; 454 reg-shift = <2>; 455 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 456 no-loopback-test; 457 status = "disabled"; 458 }; 459 460 uart13: serial@1e790700 { 461 compatible = "ns16550a"; 462 reg = <0x1e790700 0x20>; 463 reg-shift = <2>; 464 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 465 no-loopback-test; 466 status = "disabled"; 467 }; 468 469 470 471 }; 472 473 }; 474 475}; 476 477&i2c { 478 i2cglobal: i2cg@00 { 479 compatible = "aspeed,ast2600-i2c-global", "syscon", "simple-mfd"; 480 reg = <0x0 0x40>; 481 482#if 0 483 new-mode; 484#endif 485 }; 486 487 i2c0: i2c@80 { 488 #address-cells = <1>; 489 #size-cells = <0>; 490 #interrupt-cells = <1>; 491 492 reg = <0x80 0x80 0xC00 0x20>; 493 compatible = "aspeed,ast2600-i2c-bus"; 494#if 0 495 compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 496 #compatible = "aspeed,ast2500-i2c-bus"; 497 #compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 498#endif 499 bus-frequency = <100000>; 500 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 501 }; 502 503 i2c1: i2c@100 { 504 #address-cells = <1>; 505 #size-cells = <0>; 506 #interrupt-cells = <1>; 507 508 reg = <0x100 0x80 0xC20 0x20>; 509 compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 510#if 0 511 #compatible = "aspeed,ast2500-i2c-bus"; 512 #compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 513#endif 514 bus-frequency = <100000>; 515 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 516 }; 517 518 i2c2: i2c@180 { 519 #address-cells = <1>; 520 #size-cells = <0>; 521 #interrupt-cells = <1>; 522 523 reg = <0x180 0x80 0xC40 0x20>; 524 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 525 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 526 bus-frequency = <100000>; 527 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 528 }; 529 530 i2c3: i2c@200 { 531 #address-cells = <1>; 532 #size-cells = <0>; 533 #interrupt-cells = <1>; 534 535 reg = <0x200 0x40 0xC60 0x20>; 536 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 537 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 538 bus-frequency = <100000>; 539 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 540 }; 541 542 i2c4: i2c@280 { 543 #address-cells = <1>; 544 #size-cells = <0>; 545 #interrupt-cells = <1>; 546 547 reg = <0x280 0x80 0xC80 0x20>; 548 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 549 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 550 bus-frequency = <100000>; 551 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 552 }; 553 554 i2c5: i2c@300 { 555 #address-cells = <1>; 556 #size-cells = <0>; 557 #interrupt-cells = <1>; 558 559 reg = <0x300 0x40 0xCA0 0x20>; 560 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 561 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 562 bus-frequency = <100000>; 563 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 564 }; 565 566 i2c6: i2c@380 { 567 #address-cells = <1>; 568 #size-cells = <0>; 569 #interrupt-cells = <1>; 570 571 reg = <0x380 0x80 0xCC0 0x20>; 572 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 573 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 574 bus-frequency = <100000>; 575 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 576 }; 577 578 i2c7: i2c@400 { 579 #address-cells = <1>; 580 #size-cells = <0>; 581 #interrupt-cells = <1>; 582 583 reg = <0x400 0x80 0xCE0 0x20>; 584 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 585 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 586 bus-frequency = <100000>; 587 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 588 }; 589 590 i2c8: i2c@480 { 591 #address-cells = <1>; 592 #size-cells = <0>; 593 #interrupt-cells = <1>; 594 595 reg = <0x480 0x80 0xD00 0x20>; 596 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 597 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 598 bus-frequency = <100000>; 599 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 600 }; 601 602 i2c9: i2c@500 { 603 #address-cells = <1>; 604 #size-cells = <0>; 605 #interrupt-cells = <1>; 606 607 reg = <0x500 0x80 0xD20 0x20>; 608 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 609 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 610 bus-frequency = <100000>; 611 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 612 status = "disabled"; 613 }; 614 615 i2c10: i2c@580 { 616 #address-cells = <1>; 617 #size-cells = <0>; 618 #interrupt-cells = <1>; 619 620 reg = <0x580 0x80 0xD40 0x20>; 621 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 622 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 623 bus-frequency = <100000>; 624 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 625 status = "disabled"; 626 }; 627 628 i2c11: i2c@600 { 629 #address-cells = <1>; 630 #size-cells = <0>; 631 #interrupt-cells = <1>; 632 633 reg = <0x600 0x80 0xD60 0x20>; 634 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 635 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 636 bus-frequency = <100000>; 637 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 638 status = "disabled"; 639 }; 640 641 i2c12: i2c@680 { 642 #address-cells = <1>; 643 #size-cells = <0>; 644 #interrupt-cells = <1>; 645 646 reg = <0x680 0x80 0xD80 0x20>; 647 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 648 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 649 bus-frequency = <100000>; 650 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 651 status = "disabled"; 652 }; 653 654 i2c13: i2c@700 { 655 #address-cells = <1>; 656 #size-cells = <0>; 657 #interrupt-cells = <1>; 658 659 reg = <0x700 0x80 0xDA0 0x20>; 660 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 661 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 662 bus-frequency = <100000>; 663 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 664 status = "disabled"; 665 }; 666 667 i2c14: i2c@780 { 668 #address-cells = <1>; 669 #size-cells = <0>; 670 #interrupt-cells = <1>; 671 672 reg = <0x780 0x80 0xDC0 0x20>; 673 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 674 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 675 bus-frequency = <100000>; 676 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 677 status = "disabled"; 678 }; 679 680 i2c15: i2c@800 { 681 #address-cells = <1>; 682 #size-cells = <0>; 683 #interrupt-cells = <1>; 684 685 reg = <0x800 0x80 0xDE0 0x20>; 686 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 687 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 688 bus-frequency = <100000>; 689 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 690 status = "disabled"; 691 }; 692 693}; 694 695