1// SPDX-License-Identifier: GPL-2.0+ 2#include <dt-bindings/interrupt-controller/arm-gic.h> 3#include <dt-bindings/gpio/aspeed-gpio.h> 4#include "skeleton.dtsi" 5 6/ { 7 model = "Aspeed BMC"; 8 compatible = "aspeed,ast2600"; 9 #address-cells = <1>; 10 #size-cells = <1>; 11 interrupt-parent = <&gic>; 12 13 aliases { 14 i2c0 = &i2c0; 15 i2c1 = &i2c1; 16 i2c2 = &i2c2; 17 i2c3 = &i2c3; 18 i2c4 = &i2c4; 19 i2c5 = &i2c5; 20 i2c6 = &i2c6; 21 i2c7 = &i2c7; 22 i2c8 = &i2c8; 23 i2c9 = &i2c9; 24 i2c10 = &i2c10; 25 i2c11 = &i2c11; 26 i2c12 = &i2c12; 27 i2c13 = &i2c13; 28 i2c14 = &i2c14; 29 i2c15 = &i2c15; 30 serial0 = &uart1; 31 serial1 = &uart2; 32 serial2 = &uart3; 33 serial3 = &uart4; 34 serial4 = &uart5; 35 serial5 = &uart6; 36 serial6 = &uart7; 37 serial7 = &uart8; 38 serial8 = &uart9; 39 serial9 = &uart10; 40 serial10 = &uart11; 41 serial11 = &uart12; 42 serial12 = &uart13; 43 }; 44 45 cpus { 46 #address-cells = <1>; 47 #size-cells = <0>; 48 enable-method = "aspeed,ast2600-smp"; 49 50 cpu@0 { 51 compatible = "arm,cortex-a7"; 52 device_type = "cpu"; 53 reg = <0>; 54 clock-frequency = <48000000>; 55 }; 56 57 cpu@1 { 58 compatible = "arm,cortex-a7"; 59 device_type = "cpu"; 60 reg = <1>; 61 clock-frequency = <48000000>; 62 }; 63 64 }; 65 66 timer { 67 compatible = "arm,armv7-timer"; 68 interrupt-parent = <&gic>; 69 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 70 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 71 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 72 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 73 clock-frequency = <25000000>; 74 }; 75 76 memory@80000000 { 77 device_type = "memory"; 78 reg = <0x80000000 0>; 79 }; 80 81 reserved-memory { 82 #address-cells = <1>; 83 #size-cells = <1>; 84 ranges; 85 86 gfx_memory: framebuffer { 87 size = <0x01000000>; 88 alignment = <0x01000000>; 89 compatible = "shared-dma-pool"; 90 reusable; 91 }; 92 93 video_memory: video { 94 size = <0x04000000>; 95 alignment = <0x01000000>; 96 compatible = "shared-dma-pool"; 97 no-map; 98 }; 99 }; 100 101 ahb { 102 compatible = "simple-bus"; 103 #address-cells = <1>; 104 #size-cells = <1>; 105 device_type = "soc"; 106 ranges; 107 108 gic: interrupt-controller@40461000 { 109 compatible = "arm,cortex-a7-gic"; 110 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 111 #interrupt-cells = <3>; 112 interrupt-controller; 113 interrupt-parent = <&gic>; 114 reg = <0x40461000 0x1000>, 115 <0x40462000 0x1000>, 116 <0x40464000 0x2000>, 117 <0x40466000 0x2000>; 118 }; 119 120 fmc: flash-controller@1e620000 { 121 reg = < 0x1e620000 0xc4 122 0x20000000 0x10000000 >; 123 #address-cells = <1>; 124 #size-cells = <0>; 125 compatible = "aspeed,ast2600-fmc"; 126 status = "disabled"; 127 interrupts = <19>; 128 clocks = <&scu ASPEED_CLK_AHB>; 129 flash@0 { 130 reg = < 0 >; 131 compatible = "jedec,spi-nor"; 132 status = "disabled"; 133 }; 134 flash@1 { 135 reg = < 1 >; 136 compatible = "jedec,spi-nor"; 137 status = "disabled"; 138 }; 139 flash@2 { 140 reg = < 2 >; 141 compatible = "jedec,spi-nor"; 142 status = "disabled"; 143 }; 144 }; 145 146 spi1: flash-controller@1e630000 { 147 reg = < 0x1e630000 0xc4 148 0x30000000 0x08000000 >; 149 #address-cells = <1>; 150 #size-cells = <0>; 151 compatible = "aspeed,ast2600-spi"; 152 clocks = <&scu ASPEED_CLK_AHB>; 153 status = "disabled"; 154 flash@0 { 155 reg = < 0 >; 156 compatible = "jedec,spi-nor"; 157 status = "disabled"; 158 }; 159 flash@1 { 160 reg = < 1 >; 161 compatible = "jedec,spi-nor"; 162 status = "disabled"; 163 }; 164 }; 165 166 spi2: flash-controller@1e631000 { 167 reg = < 0x1e631000 0xc4 168 0x38000000 0x08000000 >; 169 #address-cells = <1>; 170 #size-cells = <0>; 171 compatible = "aspeed,ast2600-spi"; 172 clocks = <&scu ASPEED_CLK_AHB>; 173 status = "disabled"; 174 flash@0 { 175 reg = < 0 >; 176 compatible = "jedec,spi-nor"; 177 status = "disabled"; 178 }; 179 flash@1 { 180 reg = < 1 >; 181 compatible = "jedec,spi-nor"; 182 status = "disabled"; 183 }; 184 }; 185 186 edac: sdram@1e6e0000 { 187 compatible = "aspeed,ast2600-sdram-edac"; 188 reg = <0x1e6e0000 0x174>; 189 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 190 }; 191 192 mdio: ethernet@1e650000 { 193 compatible = "aspeed,aspeed-mdio"; 194 reg = <0x1e650000 0x40>; 195 resets = <&rst ASPEED_RESET_MII>; 196 status = "disabled"; 197 }; 198 199 mac0: ethernet@1e660000 { 200 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 201 reg = <0x1e660000 0x180>, <0x1e650000 0x4>; 202 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 203 clocks = <&scu ASPEED_CLK_GATE_MAC1CLK>; 204 status = "disabled"; 205 }; 206 207 mac2: ftgmac@1e670000 { 208 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 209 reg = <0x1e670000 0x180>, <0x1e650010 0x4>; 210 #address-cells = <1>; 211 #size-cells = <0>; 212 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 213 clocks = <&scu ASPEED_CLK_GATE_MAC3CLK>; 214#if 0 215 phy-handle = <&phy0>; 216#endif 217 status = "disabled"; 218 }; 219 220 mac1: ftgmac@1e680000 { 221 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 222 reg = <0x1e680000 0x180>, <0x1e650008 0x4>; 223 #address-cells = <1>; 224 #size-cells = <0>; 225 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 226 clocks = <&scu ASPEED_CLK_GATE_MAC2CLK>; 227#if 0 228 phy-handle = <&phy0>; 229#endif 230 status = "disabled"; 231 }; 232 233 mac3: ftgmac@1e690000 { 234 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 235 reg = <0x1e690000 0x180>, <0x1e650018 0x4>; 236 #address-cells = <1>; 237 #size-cells = <0>; 238 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 239 clocks = <&scu ASPEED_CLK_GATE_MAC4CLK>; 240#if 0 241 phy-handle = <&phy0>; 242#endif 243 status = "disabled"; 244 }; 245 246 247 apb { 248 compatible = "simple-bus"; 249 #address-cells = <1>; 250 #size-cells = <1>; 251 ranges; 252 253 syscon: syscon@1e6e2000 { 254 compatible = "aspeed,g6-scu", "syscon", "simple-mfd"; 255 reg = <0x1e6e2000 0x1000>; 256 #address-cells = <1>; 257 #size-cells = <1>; 258 #clock-cells = <1>; 259 #reset-cells = <1>; 260 ranges = <0 0x1e6e2000 0x1000>; 261 262 pinctrl: pinctrl { 263 compatible = "aspeed,g6-pinctrl"; 264 aspeed,external-nodes = <&gfx &lhc>; 265 266 }; 267 268 vga_scratch: scratch { 269 compatible = "aspeed,bmc-misc"; 270 }; 271 272 scu_ic0: interrupt-controller@0 { 273 #interrupt-cells = <1>; 274 compatible = "aspeed,ast2600-scu-ic"; 275 reg = <0x560 0x10>; 276 interrupt-parent = <&gic>; 277 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 278 interrupt-controller; 279 }; 280 281 scu_ic1: interrupt-controller@1 { 282 #interrupt-cells = <1>; 283 compatible = "aspeed,ast2600-scu-ic"; 284 reg = <0x570 0x10>; 285 interrupt-parent = <&gic>; 286 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 287 interrupt-controller; 288 }; 289 290 }; 291 292 smp-memram@0 { 293 compatible = "aspeed,ast2600-smpmem", "syscon"; 294 reg = <0x1e6e2180 0x40>; 295 }; 296 297 gfx: display@1e6e6000 { 298 compatible = "aspeed,ast2500-gfx", "syscon"; 299 reg = <0x1e6e6000 0x1000>; 300 reg-io-width = <4>; 301 }; 302 303 sdhci: sdhci@1e740000 { 304 #interrupt-cells = <1>; 305 compatible = "aspeed,aspeed-sdhci-irq", "simple-mfd"; 306 reg = <0x1e740000 0x1000>; 307 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 308 interrupt-controller; 309 clocks = <&scu ASPEED_CLK_GATE_SDCLK>, <&scu ASPEED_CLK_GATE_SDEXTCLK>; 310 clock-names = "ctrlclk", "extclk"; 311 #address-cells = <1>; 312 #size-cells = <1>; 313 ranges = <0x0 0x1e740000 0x1000>; 314 315 sdhci_slot0: sdhci_slot0@100 { 316 compatible = "aspeed,sdhci-ast2600"; 317 reg = <0x100 0x100>; 318 interrupts = <0>; 319 interrupt-parent = <&sdhci>; 320 sdhci,auto-cmd12; 321 clocks = <&scu ASPEED_CLK_SDIO>; 322 pwr-gpios = <&gpio0 ASPEED_GPIO(V, 0) GPIO_ACTIVE_LOW>; 323 pwr-sw-gpios = <&gpio0 ASPEED_GPIO(V, 1) GPIO_ACTIVE_LOW>; 324 status = "disabled"; 325 }; 326 327 sdhci_slot1: sdhci_slot1@200 { 328 compatible = "aspeed,sdhci-ast2600"; 329 reg = <0x200 0x100>; 330 interrupts = <1>; 331 interrupt-parent = <&sdhci>; 332 sdhci,auto-cmd12; 333 clocks = <&scu ASPEED_CLK_SDIO>; 334 pwr-gpios = <&gpio0 ASPEED_GPIO(V, 2) GPIO_ACTIVE_LOW>; 335 pwr-sw-gpios = <&gpio0 ASPEED_GPIO(V, 3) GPIO_ACTIVE_LOW>; 336 status = "disabled"; 337 }; 338 339 }; 340 341 emmc: emmc@1e750000 { 342 #interrupt-cells = <1>; 343 compatible = "aspeed,aspeed-emmc-irq", "simple-mfd"; 344 reg = <0x1e750000 0x1000>; 345 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 346 interrupt-controller; 347 clocks = <&scu ASPEED_CLK_GATE_EMMCCLK>, <&scu ASPEED_CLK_GATE_EMMCEXTCLK>; 348 clock-names = "ctrlclk", "extclk"; 349 #address-cells = <1>; 350 #size-cells = <1>; 351 ranges = <0x0 0x1e750000 0x1000>; 352 353 emmc_slot0: emmc_slot0@100 { 354 compatible = "aspeed,emmc-ast2600"; 355 reg = <0x100 0x100>; 356 interrupts = <0>; 357 interrupt-parent = <&emmc>; 358 clocks = <&scu ASPEED_CLK_EMMC>; 359 status = "disabled"; 360 }; 361 362 }; 363 364 gpio0: gpio@1e780000 { 365 compatible = "aspeed,ast2600-gpio"; 366 reg = <0x1e780000 0x1000>; 367 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 368 #gpio-cells = <2>; 369 gpio-controller; 370 interrupt-controller; 371 gpio-ranges = <&pinctrl 0 0 220>; 372 }; 373 374 gpio1: gpio@1e780800 { 375 compatible = "aspeed,ast2600-gpio"; 376 reg = <0x1e780800 0x800>; 377 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 378 #gpio-cells = <2>; 379 gpio-controller; 380 interrupt-controller; 381 gpio-ranges = <&pinctrl 0 0 208>; 382 }; 383 384 uart1: serial@1e783000 { 385 compatible = "ns16550a"; 386 reg = <0x1e783000 0x20>; 387 reg-shift = <2>; 388 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 389 clocks = <&scu ASPEED_CLK_GATE_UART1CLK>; 390 clock-frequency = <1846154>; 391 no-loopback-test; 392 status = "disabled"; 393 }; 394 395 uart5: serial@1e784000 { 396 compatible = "ns16550a"; 397 reg = <0x1e784000 0x1000>; 398 reg-shift = <2>; 399 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 400 clocks = <&scu ASPEED_CLK_GATE_UART5CLK>; 401 clock-frequency = <1846154>; 402 no-loopback-test; 403 status = "disabled"; 404 }; 405 406 wdt1: watchdog@1e785000 { 407 compatible = "aspeed,ast2600-wdt"; 408 reg = <0x1e785000 0x40>; 409 }; 410 411 wdt2: watchdog@1e785040 { 412 compatible = "aspeed,ast2600-wdt"; 413 reg = <0x1e785040 0x40>; 414 }; 415 416 wdt3: watchdog@1e785080 { 417 compatible = "aspeed,ast2600-wdt"; 418 reg = <0x1e785080 0x40>; 419 }; 420 421 wdt4: watchdog@1e7850C0 { 422 compatible = "aspeed,ast2600-wdt"; 423 reg = <0x1e7850C0 0x40>; 424 }; 425 426 lpc: lpc@1e789000 { 427 compatible = "aspeed,ast-lpc", "simple-mfd", "syscon"; 428 reg = <0x1e789000 0x200>; 429 430 #address-cells = <1>; 431 #size-cells = <1>; 432 ranges = <0x0 0x1e789000 0x1000>; 433 434 lpc_bmc: lpc-bmc@0 { 435 compatible = "aspeed,ast2600-lpc-bmc", "simple-mfd", "syscon"; 436 reg = <0x0 0x80>; 437 reg-io-width = <4>; 438 #address-cells = <1>; 439 #size-cells = <1>; 440 ranges = <0x0 0x0 0x80>; 441 442 kcs1: kcs1@0 { 443 compatible = "aspeed,ast2600-kcs-bmc"; 444 reg = <0x0 0x80>; 445 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 446 kcs_chan = <1>; 447 kcs_addr = <0xCA0>; 448 status = "disabled"; 449 }; 450 451 kcs2: kcs2@0 { 452 compatible = "aspeed,ast2600-kcs-bmc"; 453 reg = <0x0 0x80>; 454 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 455 kcs_chan = <2>; 456 kcs_addr = <0xCA8>; 457 status = "disabled"; 458 }; 459 460 kcs3: kcs3@0 { 461 compatible = "aspeed,ast2600-kcs-bmc"; 462 reg = <0x0 0x80>; 463 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 464 kcs_chan = <3>; 465 kcs_addr = <0xCA2>; 466 }; 467 468 kcs4: kcs4@0 { 469 compatible = "aspeed,ast2600-kcs-bmc"; 470 reg = <0x0 0x120>; 471 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 472 kcs_chan = <4>; 473 kcs_addr = <0xCA4>; 474 status = "disabled"; 475 }; 476 477 }; 478 479 lpc_host: lpc-host@80 { 480 compatible = "aspeed,ast2600-lpc-host", "simple-mfd", "syscon"; 481 reg = <0x80 0x1e0>; 482 reg-io-width = <4>; 483 484 #address-cells = <1>; 485 #size-cells = <1>; 486 ranges = <0x0 0x80 0x1e0>; 487 488 lpc_ctrl: lpc-ctrl@0 { 489 compatible = "aspeed,ast2600-lpc-ctrl"; 490 reg = <0x0 0x80>; 491 status = "disabled"; 492 }; 493 494 lpc_snoop: lpc-snoop@0 { 495 compatible = "aspeed,ast2600-lpc-snoop"; 496 reg = <0x0 0x80>; 497 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 498 snoop-ports = <0x80>; 499 status = "disabled"; 500 }; 501 502 lhc: lhc@20 { 503 compatible = "aspeed,ast2600-lhc"; 504 reg = <0x20 0x24 0x48 0x8>; 505 }; 506 507 lpc_reset: reset-controller@18 { 508 compatible = "aspeed,ast2600-lpc-reset"; 509 reg = <0x18 0x4>; 510 #reset-cells = <1>; 511 status = "disabled"; 512 }; 513 514 ibt: ibt@c0 { 515 compatible = "aspeed,ast2600-ibt-bmc"; 516 reg = <0xc0 0x18>; 517 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 518 status = "disabled"; 519 }; 520 521 sio_regs: regs { 522 compatible = "aspeed,bmc-misc"; 523 }; 524 525 mbox: mbox@180 { 526 compatible = "aspeed,ast2600-mbox"; 527 reg = <0x180 0x5c>; 528 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 529 #mbox-cells = <1>; 530 status = "disabled"; 531 }; 532 }; 533 }; 534 535 uart2: serial@1e78d000 { 536 compatible = "ns16550a"; 537 reg = <0x1e78d000 0x20>; 538 reg-shift = <2>; 539 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 540 clocks = <&scu ASPEED_CLK_GATE_UART2CLK>; 541 clock-frequency = <1846154>; 542 no-loopback-test; 543 status = "disabled"; 544 }; 545 546 uart3: serial@1e78e000 { 547 compatible = "ns16550a"; 548 reg = <0x1e78e000 0x20>; 549 reg-shift = <2>; 550 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 551 clocks = <&scu ASPEED_CLK_GATE_UART3CLK>; 552 clock-frequency = <1846154>; 553 no-loopback-test; 554 status = "disabled"; 555 }; 556 557 uart4: serial@1e78f000 { 558 compatible = "ns16550a"; 559 reg = <0x1e78f000 0x20>; 560 reg-shift = <2>; 561 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 562 clocks = <&scu ASPEED_CLK_GATE_UART4CLK>; 563 clock-frequency = <1846154>; 564 no-loopback-test; 565 status = "disabled"; 566 }; 567 568 i2c: bus@1e78a000 { 569 compatible = "simple-bus"; 570 #address-cells = <1>; 571 #size-cells = <1>; 572 ranges = <0 0x1e78a000 0x1000>; 573 }; 574 575 uart6: serial@1e790000 { 576 compatible = "ns16550a"; 577 reg = <0x1e790000 0x20>; 578 reg-shift = <2>; 579 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 580 clocks = <&scu ASPEED_CLK_GATE_UART6CLK>; 581 clock-frequency = <1846154>; 582 no-loopback-test; 583 status = "disabled"; 584 }; 585 586 uart7: serial@1e790100 { 587 compatible = "ns16550a"; 588 reg = <0x1e790100 0x20>; 589 reg-shift = <2>; 590 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 591 clocks = <&scu ASPEED_CLK_GATE_UART7CLK>; 592 clock-frequency = <1846154>; 593 no-loopback-test; 594 status = "disabled"; 595 }; 596 597 uart8: serial@1e790200 { 598 compatible = "ns16550a"; 599 reg = <0x1e790200 0x20>; 600 reg-shift = <2>; 601 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 602 clocks = <&scu ASPEED_CLK_GATE_UART8CLK>; 603 clock-frequency = <1846154>; 604 no-loopback-test; 605 status = "disabled"; 606 }; 607 608 uart9: serial@1e790300 { 609 compatible = "ns16550a"; 610 reg = <0x1e790300 0x20>; 611 reg-shift = <2>; 612 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 613 clocks = <&scu ASPEED_CLK_GATE_UART9CLK>; 614 clock-frequency = <1846154>; 615 no-loopback-test; 616 status = "disabled"; 617 }; 618 619 uart10: serial@1e790400 { 620 compatible = "ns16550a"; 621 reg = <0x1e790400 0x20>; 622 reg-shift = <2>; 623 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 624 clocks = <&scu ASPEED_CLK_GATE_UART10CLK>; 625 clock-frequency = <1846154>; 626 no-loopback-test; 627 status = "disabled"; 628 }; 629 630 uart11: serial@1e790500 { 631 compatible = "ns16550a"; 632 reg = <0x1e790400 0x20>; 633 reg-shift = <2>; 634 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 635 clocks = <&scu ASPEED_CLK_GATE_UART11CLK>; 636 clock-frequency = <1846154>; 637 no-loopback-test; 638 status = "disabled"; 639 }; 640 641 uart12: serial@1e790600 { 642 compatible = "ns16550a"; 643 reg = <0x1e790600 0x20>; 644 reg-shift = <2>; 645 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 646 clocks = <&scu ASPEED_CLK_GATE_UART12CLK>; 647 clock-frequency = <1846154>; 648 no-loopback-test; 649 status = "disabled"; 650 }; 651 652 uart13: serial@1e790700 { 653 compatible = "ns16550a"; 654 reg = <0x1e790700 0x20>; 655 reg-shift = <2>; 656 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 657 clocks = <&scu ASPEED_CLK_GATE_UART13CLK>; 658 clock-frequency = <1846154>; 659 no-loopback-test; 660 status = "disabled"; 661 }; 662 663 664 665 }; 666 667 }; 668 669}; 670 671&i2c { 672 i2cglobal: i2cg@00 { 673 compatible = "aspeed,ast2600-i2c-global"; 674 reg = <0x0 0x40>; 675 resets = <&rst ASPEED_RESET_I2C>; 676#if 0 677 new-mode; 678#endif 679 }; 680 681 i2c0: i2c@80 { 682 #address-cells = <1>; 683 #size-cells = <0>; 684 #interrupt-cells = <1>; 685 686 reg = <0x80 0x80 0xC00 0x20>; 687 compatible = "aspeed,ast2600-i2c-bus"; 688 bus-frequency = <100000>; 689 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 690 clocks = <&scu ASPEED_CLK_APB>; 691 status = "disabled"; 692 }; 693 694 i2c1: i2c@100 { 695 #address-cells = <1>; 696 #size-cells = <0>; 697 #interrupt-cells = <1>; 698 699 reg = <0x100 0x80 0xC20 0x20>; 700 compatible = "aspeed,ast2600-i2c-bus"; 701 bus-frequency = <100000>; 702 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 703 clocks = <&scu ASPEED_CLK_APB>; 704 status = "disabled"; 705 }; 706 707 i2c2: i2c@180 { 708 #address-cells = <1>; 709 #size-cells = <0>; 710 #interrupt-cells = <1>; 711 712 reg = <0x180 0x80 0xC40 0x20>; 713 compatible = "aspeed,ast2600-i2c-bus"; 714 bus-frequency = <100000>; 715 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 716 clocks = <&scu ASPEED_CLK_APB>; 717 }; 718 719 i2c3: i2c@200 { 720 #address-cells = <1>; 721 #size-cells = <0>; 722 #interrupt-cells = <1>; 723 724 reg = <0x200 0x40 0xC60 0x20>; 725 compatible = "aspeed,ast2600-i2c-bus"; 726 bus-frequency = <100000>; 727 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 728 clocks = <&scu ASPEED_CLK_APB>; 729 }; 730 731 i2c4: i2c@280 { 732 #address-cells = <1>; 733 #size-cells = <0>; 734 #interrupt-cells = <1>; 735 736 reg = <0x280 0x80 0xC80 0x20>; 737 compatible = "aspeed,ast2600-i2c-bus"; 738 bus-frequency = <100000>; 739 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 740 clocks = <&scu ASPEED_CLK_APB>; 741 }; 742 743 i2c5: i2c@300 { 744 #address-cells = <1>; 745 #size-cells = <0>; 746 #interrupt-cells = <1>; 747 748 reg = <0x300 0x40 0xCA0 0x20>; 749 compatible = "aspeed,ast2600-i2c-bus"; 750 bus-frequency = <100000>; 751 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 752 clocks = <&scu ASPEED_CLK_APB>; 753 }; 754 755 i2c6: i2c@380 { 756 #address-cells = <1>; 757 #size-cells = <0>; 758 #interrupt-cells = <1>; 759 760 reg = <0x380 0x80 0xCC0 0x20>; 761 compatible = "aspeed,ast2600-i2c-bus"; 762 bus-frequency = <100000>; 763 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 764 clocks = <&scu ASPEED_CLK_APB>; 765 }; 766 767 i2c7: i2c@400 { 768 #address-cells = <1>; 769 #size-cells = <0>; 770 #interrupt-cells = <1>; 771 772 reg = <0x400 0x80 0xCE0 0x20>; 773 compatible = "aspeed,ast2600-i2c-bus"; 774 bus-frequency = <100000>; 775 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 776 clocks = <&scu ASPEED_CLK_APB>; 777 }; 778 779 i2c8: i2c@480 { 780 #address-cells = <1>; 781 #size-cells = <0>; 782 #interrupt-cells = <1>; 783 784 reg = <0x480 0x80 0xD00 0x20>; 785 compatible = "aspeed,ast2600-i2c-bus"; 786 bus-frequency = <100000>; 787 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 788 clocks = <&scu ASPEED_CLK_APB>; 789 }; 790 791 i2c9: i2c@500 { 792 #address-cells = <1>; 793 #size-cells = <0>; 794 #interrupt-cells = <1>; 795 796 reg = <0x500 0x80 0xD20 0x20>; 797 compatible = "aspeed,ast2600-i2c-bus"; 798 bus-frequency = <100000>; 799 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 800 clocks = <&scu ASPEED_CLK_APB>; 801 status = "disabled"; 802 }; 803 804 i2c10: i2c@580 { 805 #address-cells = <1>; 806 #size-cells = <0>; 807 #interrupt-cells = <1>; 808 809 reg = <0x580 0x80 0xD40 0x20>; 810 compatible = "aspeed,ast2600-i2c-bus"; 811 bus-frequency = <100000>; 812 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 813 clocks = <&scu ASPEED_CLK_APB>; 814 status = "disabled"; 815 }; 816 817 i2c11: i2c@600 { 818 #address-cells = <1>; 819 #size-cells = <0>; 820 #interrupt-cells = <1>; 821 822 reg = <0x600 0x80 0xD60 0x20>; 823 compatible = "aspeed,ast2600-i2c-bus"; 824 bus-frequency = <100000>; 825 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 826 clocks = <&scu ASPEED_CLK_APB>; 827 status = "disabled"; 828 }; 829 830 i2c12: i2c@680 { 831 #address-cells = <1>; 832 #size-cells = <0>; 833 #interrupt-cells = <1>; 834 835 reg = <0x680 0x80 0xD80 0x20>; 836 compatible = "aspeed,ast2600-i2c-bus"; 837 bus-frequency = <100000>; 838 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 839 clocks = <&scu ASPEED_CLK_APB>; 840 status = "disabled"; 841 }; 842 843 i2c13: i2c@700 { 844 #address-cells = <1>; 845 #size-cells = <0>; 846 #interrupt-cells = <1>; 847 848 reg = <0x700 0x80 0xDA0 0x20>; 849 compatible = "aspeed,ast2600-i2c-bus"; 850 bus-frequency = <100000>; 851 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 852 clocks = <&scu ASPEED_CLK_APB>; 853 status = "disabled"; 854 }; 855 856 i2c14: i2c@780 { 857 #address-cells = <1>; 858 #size-cells = <0>; 859 #interrupt-cells = <1>; 860 861 reg = <0x780 0x80 0xDC0 0x20>; 862 compatible = "aspeed,ast2600-i2c-bus"; 863 bus-frequency = <100000>; 864 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 865 clocks = <&scu ASPEED_CLK_APB>; 866 status = "disabled"; 867 }; 868 869 i2c15: i2c@800 { 870 #address-cells = <1>; 871 #size-cells = <0>; 872 #interrupt-cells = <1>; 873 874 reg = <0x800 0x80 0xDE0 0x20>; 875 compatible = "aspeed,ast2600-i2c-bus"; 876 bus-frequency = <100000>; 877 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 878 clocks = <&scu ASPEED_CLK_APB>; 879 status = "disabled"; 880 }; 881 882}; 883 884&pinctrl { 885 pinctrl_acpi_default: acpi_default { 886 function = "ACPI"; 887 groups = "ACPI"; 888 }; 889 890 pinctrl_adc0_default: adc0_default { 891 function = "ADC0"; 892 groups = "ADC0"; 893 }; 894 895 pinctrl_adc1_default: adc1_default { 896 function = "ADC1"; 897 groups = "ADC1"; 898 }; 899 900 pinctrl_adc10_default: adc10_default { 901 function = "ADC10"; 902 groups = "ADC10"; 903 }; 904 905 pinctrl_adc11_default: adc11_default { 906 function = "ADC11"; 907 groups = "ADC11"; 908 }; 909 910 pinctrl_adc12_default: adc12_default { 911 function = "ADC12"; 912 groups = "ADC12"; 913 }; 914 915 pinctrl_adc13_default: adc13_default { 916 function = "ADC13"; 917 groups = "ADC13"; 918 }; 919 920 pinctrl_adc14_default: adc14_default { 921 function = "ADC14"; 922 groups = "ADC14"; 923 }; 924 925 pinctrl_adc15_default: adc15_default { 926 function = "ADC15"; 927 groups = "ADC15"; 928 }; 929 930 pinctrl_adc2_default: adc2_default { 931 function = "ADC2"; 932 groups = "ADC2"; 933 }; 934 935 pinctrl_adc3_default: adc3_default { 936 function = "ADC3"; 937 groups = "ADC3"; 938 }; 939 940 pinctrl_adc4_default: adc4_default { 941 function = "ADC4"; 942 groups = "ADC4"; 943 }; 944 945 pinctrl_adc5_default: adc5_default { 946 function = "ADC5"; 947 groups = "ADC5"; 948 }; 949 950 pinctrl_adc6_default: adc6_default { 951 function = "ADC6"; 952 groups = "ADC6"; 953 }; 954 955 pinctrl_adc7_default: adc7_default { 956 function = "ADC7"; 957 groups = "ADC7"; 958 }; 959 960 pinctrl_adc8_default: adc8_default { 961 function = "ADC8"; 962 groups = "ADC8"; 963 }; 964 965 pinctrl_adc9_default: adc9_default { 966 function = "ADC9"; 967 groups = "ADC9"; 968 }; 969 970 pinctrl_bmcint_default: bmcint_default { 971 function = "BMCINT"; 972 groups = "BMCINT"; 973 }; 974 975 pinctrl_ddcclk_default: ddcclk_default { 976 function = "DDCCLK"; 977 groups = "DDCCLK"; 978 }; 979 980 pinctrl_ddcdat_default: ddcdat_default { 981 function = "DDCDAT"; 982 groups = "DDCDAT"; 983 }; 984 985 pinctrl_espi_default: espi_default { 986 function = "ESPI"; 987 groups = "ESPI"; 988 }; 989 990 pinctrl_fwspics1_default: fwspics1_default { 991 function = "FWSPICS1"; 992 groups = "FWSPICS1"; 993 }; 994 995 pinctrl_fwspics2_default: fwspics2_default { 996 function = "FWSPICS2"; 997 groups = "FWSPICS2"; 998 }; 999 1000 pinctrl_gpid0_default: gpid0_default { 1001 function = "GPID0"; 1002 groups = "GPID0"; 1003 }; 1004 1005 pinctrl_gpid2_default: gpid2_default { 1006 function = "GPID2"; 1007 groups = "GPID2"; 1008 }; 1009 1010 pinctrl_gpid4_default: gpid4_default { 1011 function = "GPID4"; 1012 groups = "GPID4"; 1013 }; 1014 1015 pinctrl_gpid6_default: gpid6_default { 1016 function = "GPID6"; 1017 groups = "GPID6"; 1018 }; 1019 1020 pinctrl_gpie0_default: gpie0_default { 1021 function = "GPIE0"; 1022 groups = "GPIE0"; 1023 }; 1024 1025 pinctrl_gpie2_default: gpie2_default { 1026 function = "GPIE2"; 1027 groups = "GPIE2"; 1028 }; 1029 1030 pinctrl_gpie4_default: gpie4_default { 1031 function = "GPIE4"; 1032 groups = "GPIE4"; 1033 }; 1034 1035 pinctrl_gpie6_default: gpie6_default { 1036 function = "GPIE6"; 1037 groups = "GPIE6"; 1038 }; 1039 1040 pinctrl_i2c10_default: i2c10_default { 1041 function = "I2C10"; 1042 groups = "I2C10"; 1043 }; 1044 1045 pinctrl_i2c11_default: i2c11_default { 1046 function = "I2C11"; 1047 groups = "I2C11"; 1048 }; 1049 1050 pinctrl_i2c12_default: i2c12_default { 1051 function = "I2C12"; 1052 groups = "I2C12"; 1053 }; 1054 1055 pinctrl_i2c13_default: i2c13_default { 1056 function = "I2C13"; 1057 groups = "I2C13"; 1058 }; 1059 1060 pinctrl_i2c14_default: i2c14_default { 1061 function = "I2C14"; 1062 groups = "I2C14"; 1063 }; 1064 1065 pinctrl_i2c3_default: i2c3_default { 1066 function = "I2C3"; 1067 groups = "I2C3"; 1068 }; 1069 1070 pinctrl_i2c4_default: i2c4_default { 1071 function = "I2C4"; 1072 groups = "I2C4"; 1073 }; 1074 1075 pinctrl_i2c5_default: i2c5_default { 1076 function = "I2C5"; 1077 groups = "I2C5"; 1078 }; 1079 1080 pinctrl_i2c6_default: i2c6_default { 1081 function = "I2C6"; 1082 groups = "I2C6"; 1083 }; 1084 1085 pinctrl_i2c7_default: i2c7_default { 1086 function = "I2C7"; 1087 groups = "I2C7"; 1088 }; 1089 1090 pinctrl_i2c8_default: i2c8_default { 1091 function = "I2C8"; 1092 groups = "I2C8"; 1093 }; 1094 1095 pinctrl_i2c9_default: i2c9_default { 1096 function = "I2C9"; 1097 groups = "I2C9"; 1098 }; 1099 1100 pinctrl_lad0_default: lad0_default { 1101 function = "LAD0"; 1102 groups = "LAD0"; 1103 }; 1104 1105 pinctrl_lad1_default: lad1_default { 1106 function = "LAD1"; 1107 groups = "LAD1"; 1108 }; 1109 1110 pinctrl_lad2_default: lad2_default { 1111 function = "LAD2"; 1112 groups = "LAD2"; 1113 }; 1114 1115 pinctrl_lad3_default: lad3_default { 1116 function = "LAD3"; 1117 groups = "LAD3"; 1118 }; 1119 1120 pinctrl_lclk_default: lclk_default { 1121 function = "LCLK"; 1122 groups = "LCLK"; 1123 }; 1124 1125 pinctrl_lframe_default: lframe_default { 1126 function = "LFRAME"; 1127 groups = "LFRAME"; 1128 }; 1129 1130 pinctrl_lpchc_default: lpchc_default { 1131 function = "LPCHC"; 1132 groups = "LPCHC"; 1133 }; 1134 1135 pinctrl_lpcpd_default: lpcpd_default { 1136 function = "LPCPD"; 1137 groups = "LPCPD"; 1138 }; 1139 1140 pinctrl_lpcplus_default: lpcplus_default { 1141 function = "LPCPLUS"; 1142 groups = "LPCPLUS"; 1143 }; 1144 1145 pinctrl_lpcpme_default: lpcpme_default { 1146 function = "LPCPME"; 1147 groups = "LPCPME"; 1148 }; 1149 1150 pinctrl_lpcrst_default: lpcrst_default { 1151 function = "LPCRST"; 1152 groups = "LPCRST"; 1153 }; 1154 1155 pinctrl_lpcsmi_default: lpcsmi_default { 1156 function = "LPCSMI"; 1157 groups = "LPCSMI"; 1158 }; 1159 1160 pinctrl_lsirq_default: lsirq_default { 1161 function = "LSIRQ"; 1162 groups = "LSIRQ"; 1163 }; 1164 1165 pinctrl_mac1link_default: mac1link_default { 1166 function = "MAC1LINK"; 1167 groups = "MAC1LINK"; 1168 }; 1169 1170 pinctrl_mac2link_default: mac2link_default { 1171 function = "MAC2LINK"; 1172 groups = "MAC2LINK"; 1173 }; 1174 1175 pinctrl_mac3link_default: mac3link_default { 1176 function = "MAC3LINK"; 1177 groups = "MAC3LINK"; 1178 }; 1179 1180 pinctrl_mac4link_default: mac4link_default { 1181 function = "MAC4LINK"; 1182 groups = "MAC4LINK"; 1183 }; 1184 1185 pinctrl_mdio1_default: mdio1_default { 1186 function = "MDIO1"; 1187 groups = "MDIO1"; 1188 }; 1189 1190 pinctrl_mdio2_default: mdio2_default { 1191 function = "MDIO2"; 1192 groups = "MDIO2"; 1193 }; 1194 1195 pinctrl_mdio3_default: mdio3_default { 1196 function = "MDIO3"; 1197 groups = "MDIO3"; 1198 }; 1199 1200 pinctrl_mdio4_default: mdio4_default { 1201 function = "MDIO4"; 1202 groups = "MDIO4"; 1203 }; 1204 1205 pinctrl_ncts1_default: ncts1_default { 1206 function = "NCTS1"; 1207 groups = "NCTS1"; 1208 }; 1209 1210 pinctrl_ncts2_default: ncts2_default { 1211 function = "NCTS2"; 1212 groups = "NCTS2"; 1213 }; 1214 1215 pinctrl_ncts3_default: ncts3_default { 1216 function = "NCTS3"; 1217 groups = "NCTS3"; 1218 }; 1219 1220 pinctrl_ncts4_default: ncts4_default { 1221 function = "NCTS4"; 1222 groups = "NCTS4"; 1223 }; 1224 1225 pinctrl_ndcd1_default: ndcd1_default { 1226 function = "NDCD1"; 1227 groups = "NDCD1"; 1228 }; 1229 1230 pinctrl_ndcd2_default: ndcd2_default { 1231 function = "NDCD2"; 1232 groups = "NDCD2"; 1233 }; 1234 1235 pinctrl_ndcd3_default: ndcd3_default { 1236 function = "NDCD3"; 1237 groups = "NDCD3"; 1238 }; 1239 1240 pinctrl_ndcd4_default: ndcd4_default { 1241 function = "NDCD4"; 1242 groups = "NDCD4"; 1243 }; 1244 1245 pinctrl_ndsr1_default: ndsr1_default { 1246 function = "NDSR1"; 1247 groups = "NDSR1"; 1248 }; 1249 1250 pinctrl_ndsr2_default: ndsr2_default { 1251 function = "NDSR2"; 1252 groups = "NDSR2"; 1253 }; 1254 1255 pinctrl_ndsr3_default: ndsr3_default { 1256 function = "NDSR3"; 1257 groups = "NDSR3"; 1258 }; 1259 1260 pinctrl_ndsr4_default: ndsr4_default { 1261 function = "NDSR4"; 1262 groups = "NDSR4"; 1263 }; 1264 1265 pinctrl_ndtr1_default: ndtr1_default { 1266 function = "NDTR1"; 1267 groups = "NDTR1"; 1268 }; 1269 1270 pinctrl_ndtr2_default: ndtr2_default { 1271 function = "NDTR2"; 1272 groups = "NDTR2"; 1273 }; 1274 1275 pinctrl_ndtr3_default: ndtr3_default { 1276 function = "NDTR3"; 1277 groups = "NDTR3"; 1278 }; 1279 1280 pinctrl_ndtr4_default: ndtr4_default { 1281 function = "NDTR4"; 1282 groups = "NDTR4"; 1283 }; 1284 1285 pinctrl_nri1_default: nri1_default { 1286 function = "NRI1"; 1287 groups = "NRI1"; 1288 }; 1289 1290 pinctrl_nri2_default: nri2_default { 1291 function = "NRI2"; 1292 groups = "NRI2"; 1293 }; 1294 1295 pinctrl_nri3_default: nri3_default { 1296 function = "NRI3"; 1297 groups = "NRI3"; 1298 }; 1299 1300 pinctrl_nri4_default: nri4_default { 1301 function = "NRI4"; 1302 groups = "NRI4"; 1303 }; 1304 1305 pinctrl_nrts1_default: nrts1_default { 1306 function = "NRTS1"; 1307 groups = "NRTS1"; 1308 }; 1309 1310 pinctrl_nrts2_default: nrts2_default { 1311 function = "NRTS2"; 1312 groups = "NRTS2"; 1313 }; 1314 1315 pinctrl_nrts3_default: nrts3_default { 1316 function = "NRTS3"; 1317 groups = "NRTS3"; 1318 }; 1319 1320 pinctrl_nrts4_default: nrts4_default { 1321 function = "NRTS4"; 1322 groups = "NRTS4"; 1323 }; 1324 1325 pinctrl_oscclk_default: oscclk_default { 1326 function = "OSCCLK"; 1327 groups = "OSCCLK"; 1328 }; 1329 1330 pinctrl_pewake_default: pewake_default { 1331 function = "PEWAKE"; 1332 groups = "PEWAKE"; 1333 }; 1334 1335 pinctrl_pnor_default: pnor_default { 1336 function = "PNOR"; 1337 groups = "PNOR"; 1338 }; 1339 1340 pinctrl_pwm0_default: pwm0_default { 1341 function = "PWM0"; 1342 groups = "PWM0"; 1343 }; 1344 1345 pinctrl_pwm1_default: pwm1_default { 1346 function = "PWM1"; 1347 groups = "PWM1"; 1348 }; 1349 1350 pinctrl_pwm2_default: pwm2_default { 1351 function = "PWM2"; 1352 groups = "PWM2"; 1353 }; 1354 1355 pinctrl_pwm3_default: pwm3_default { 1356 function = "PWM3"; 1357 groups = "PWM3"; 1358 }; 1359 1360 pinctrl_pwm4_default: pwm4_default { 1361 function = "PWM4"; 1362 groups = "PWM4"; 1363 }; 1364 1365 pinctrl_pwm5_default: pwm5_default { 1366 function = "PWM5"; 1367 groups = "PWM5"; 1368 }; 1369 1370 pinctrl_pwm6_default: pwm6_default { 1371 function = "PWM6"; 1372 groups = "PWM6"; 1373 }; 1374 1375 pinctrl_pwm7_default: pwm7_default { 1376 function = "PWM7"; 1377 groups = "PWM7"; 1378 }; 1379 1380 pinctrl_rgmii1_default: rgmii1_default { 1381 function = "RGMII1"; 1382 groups = "RGMII1"; 1383 }; 1384 1385 pinctrl_rgmii2_default: rgmii2_default { 1386 function = "RGMII2"; 1387 groups = "RGMII2"; 1388 }; 1389 1390 pinctrl_rmii1_default: rmii1_default { 1391 function = "RMII1"; 1392 groups = "RMII1"; 1393 }; 1394 1395 pinctrl_rmii2_default: rmii2_default { 1396 function = "RMII2"; 1397 groups = "RMII2"; 1398 }; 1399 1400 pinctrl_rxd1_default: rxd1_default { 1401 function = "RXD1"; 1402 groups = "RXD1"; 1403 }; 1404 1405 pinctrl_rxd2_default: rxd2_default { 1406 function = "RXD2"; 1407 groups = "RXD2"; 1408 }; 1409 1410 pinctrl_rxd3_default: rxd3_default { 1411 function = "RXD3"; 1412 groups = "RXD3"; 1413 }; 1414 1415 pinctrl_rxd4_default: rxd4_default { 1416 function = "RXD4"; 1417 groups = "RXD4"; 1418 }; 1419 1420 pinctrl_salt1_default: salt1_default { 1421 function = "SALT1"; 1422 groups = "SALT1"; 1423 }; 1424 1425 pinctrl_salt10_default: salt10_default { 1426 function = "SALT10"; 1427 groups = "SALT10"; 1428 }; 1429 1430 pinctrl_salt11_default: salt11_default { 1431 function = "SALT11"; 1432 groups = "SALT11"; 1433 }; 1434 1435 pinctrl_salt12_default: salt12_default { 1436 function = "SALT12"; 1437 groups = "SALT12"; 1438 }; 1439 1440 pinctrl_salt13_default: salt13_default { 1441 function = "SALT13"; 1442 groups = "SALT13"; 1443 }; 1444 1445 pinctrl_salt14_default: salt14_default { 1446 function = "SALT14"; 1447 groups = "SALT14"; 1448 }; 1449 1450 pinctrl_salt2_default: salt2_default { 1451 function = "SALT2"; 1452 groups = "SALT2"; 1453 }; 1454 1455 pinctrl_salt3_default: salt3_default { 1456 function = "SALT3"; 1457 groups = "SALT3"; 1458 }; 1459 1460 pinctrl_salt4_default: salt4_default { 1461 function = "SALT4"; 1462 groups = "SALT4"; 1463 }; 1464 1465 pinctrl_salt5_default: salt5_default { 1466 function = "SALT5"; 1467 groups = "SALT5"; 1468 }; 1469 1470 pinctrl_salt6_default: salt6_default { 1471 function = "SALT6"; 1472 groups = "SALT6"; 1473 }; 1474 1475 pinctrl_salt7_default: salt7_default { 1476 function = "SALT7"; 1477 groups = "SALT7"; 1478 }; 1479 1480 pinctrl_salt8_default: salt8_default { 1481 function = "SALT8"; 1482 groups = "SALT8"; 1483 }; 1484 1485 pinctrl_salt9_default: salt9_default { 1486 function = "SALT9"; 1487 groups = "SALT9"; 1488 }; 1489 1490 pinctrl_scl1_default: scl1_default { 1491 function = "SCL1"; 1492 groups = "SCL1"; 1493 }; 1494 1495 pinctrl_scl2_default: scl2_default { 1496 function = "SCL2"; 1497 groups = "SCL2"; 1498 }; 1499 1500 pinctrl_sd1_default: sd1_default { 1501 function = "SD1"; 1502 groups = "SD1"; 1503 }; 1504 1505 pinctrl_sd2_default: sd2_default { 1506 function = "SD2"; 1507 groups = "SD2"; 1508 }; 1509 1510 pinctrl_emmc_default: emmc_default { 1511 function = "EMMC"; 1512 groups = "EMMC"; 1513 }; 1514 1515 pinctrl_sda1_default: sda1_default { 1516 function = "SDA1"; 1517 groups = "SDA1"; 1518 }; 1519 1520 pinctrl_sda2_default: sda2_default { 1521 function = "SDA2"; 1522 groups = "SDA2"; 1523 }; 1524 1525 pinctrl_sgps1_default: sgps1_default { 1526 function = "SGPS1"; 1527 groups = "SGPS1"; 1528 }; 1529 1530 pinctrl_sgps2_default: sgps2_default { 1531 function = "SGPS2"; 1532 groups = "SGPS2"; 1533 }; 1534 1535 pinctrl_sioonctrl_default: sioonctrl_default { 1536 function = "SIOONCTRL"; 1537 groups = "SIOONCTRL"; 1538 }; 1539 1540 pinctrl_siopbi_default: siopbi_default { 1541 function = "SIOPBI"; 1542 groups = "SIOPBI"; 1543 }; 1544 1545 pinctrl_siopbo_default: siopbo_default { 1546 function = "SIOPBO"; 1547 groups = "SIOPBO"; 1548 }; 1549 1550 pinctrl_siopwreq_default: siopwreq_default { 1551 function = "SIOPWREQ"; 1552 groups = "SIOPWREQ"; 1553 }; 1554 1555 pinctrl_siopwrgd_default: siopwrgd_default { 1556 function = "SIOPWRGD"; 1557 groups = "SIOPWRGD"; 1558 }; 1559 1560 pinctrl_sios3_default: sios3_default { 1561 function = "SIOS3"; 1562 groups = "SIOS3"; 1563 }; 1564 1565 pinctrl_sios5_default: sios5_default { 1566 function = "SIOS5"; 1567 groups = "SIOS5"; 1568 }; 1569 1570 pinctrl_siosci_default: siosci_default { 1571 function = "SIOSCI"; 1572 groups = "SIOSCI"; 1573 }; 1574 1575 pinctrl_spi1_default: spi1_default { 1576 function = "SPI1"; 1577 groups = "SPI1"; 1578 }; 1579 1580 pinctrl_spi1cs1_default: spi1cs1_default { 1581 function = "SPI1CS1"; 1582 groups = "SPI1CS1"; 1583 }; 1584 1585 pinctrl_spi1debug_default: spi1debug_default { 1586 function = "SPI1DEBUG"; 1587 groups = "SPI1DEBUG"; 1588 }; 1589 1590 pinctrl_spi1passthru_default: spi1passthru_default { 1591 function = "SPI1PASSTHRU"; 1592 groups = "SPI1PASSTHRU"; 1593 }; 1594 1595 pinctrl_spi2ck_default: spi2ck_default { 1596 function = "SPI2CK"; 1597 groups = "SPI2CK"; 1598 }; 1599 1600 pinctrl_spi2cs0_default: spi2cs0_default { 1601 function = "SPI2CS0"; 1602 groups = "SPI2CS0"; 1603 }; 1604 1605 pinctrl_spi2cs1_default: spi2cs1_default { 1606 function = "SPI2CS1"; 1607 groups = "SPI2CS1"; 1608 }; 1609 1610 pinctrl_spi2miso_default: spi2miso_default { 1611 function = "SPI2MISO"; 1612 groups = "SPI2MISO"; 1613 }; 1614 1615 pinctrl_spi2mosi_default: spi2mosi_default { 1616 function = "SPI2MOSI"; 1617 groups = "SPI2MOSI"; 1618 }; 1619 1620 pinctrl_timer3_default: timer3_default { 1621 function = "TIMER3"; 1622 groups = "TIMER3"; 1623 }; 1624 1625 pinctrl_timer4_default: timer4_default { 1626 function = "TIMER4"; 1627 groups = "TIMER4"; 1628 }; 1629 1630 pinctrl_timer5_default: timer5_default { 1631 function = "TIMER5"; 1632 groups = "TIMER5"; 1633 }; 1634 1635 pinctrl_timer6_default: timer6_default { 1636 function = "TIMER6"; 1637 groups = "TIMER6"; 1638 }; 1639 1640 pinctrl_timer7_default: timer7_default { 1641 function = "TIMER7"; 1642 groups = "TIMER7"; 1643 }; 1644 1645 pinctrl_timer8_default: timer8_default { 1646 function = "TIMER8"; 1647 groups = "TIMER8"; 1648 }; 1649 1650 pinctrl_txd1_default: txd1_default { 1651 function = "TXD1"; 1652 groups = "TXD1"; 1653 }; 1654 1655 pinctrl_txd2_default: txd2_default { 1656 function = "TXD2"; 1657 groups = "TXD2"; 1658 }; 1659 1660 pinctrl_txd3_default: txd3_default { 1661 function = "TXD3"; 1662 groups = "TXD3"; 1663 }; 1664 1665 pinctrl_txd4_default: txd4_default { 1666 function = "TXD4"; 1667 groups = "TXD4"; 1668 }; 1669 1670 pinctrl_uart6_default: uart6_default { 1671 function = "UART6"; 1672 groups = "UART6"; 1673 }; 1674 1675 pinctrl_usbcki_default: usbcki_default { 1676 function = "USBCKI"; 1677 groups = "USBCKI"; 1678 }; 1679 1680 pinctrl_usb2ah_default: usb2ah_default { 1681 function = "USB2AH"; 1682 groups = "USB2AH"; 1683 }; 1684 1685 pinctrl_usb11bhid_default: usb11bhid_default { 1686 function = "USB11BHID"; 1687 groups = "USB11BHID"; 1688 }; 1689 1690 pinctrl_usb2bh_default: usb2bh_default { 1691 function = "USB2BH"; 1692 groups = "USB2BH"; 1693 }; 1694 1695 pinctrl_vgabiosrom_default: vgabiosrom_default { 1696 function = "VGABIOSROM"; 1697 groups = "VGABIOSROM"; 1698 }; 1699 1700 pinctrl_vgahs_default: vgahs_default { 1701 function = "VGAHS"; 1702 groups = "VGAHS"; 1703 }; 1704 1705 pinctrl_vgavs_default: vgavs_default { 1706 function = "VGAVS"; 1707 groups = "VGAVS"; 1708 }; 1709 1710 pinctrl_vpi24_default: vpi24_default { 1711 function = "VPI24"; 1712 groups = "VPI24"; 1713 }; 1714 1715 pinctrl_vpo_default: vpo_default { 1716 function = "VPO"; 1717 groups = "VPO"; 1718 }; 1719 1720 pinctrl_wdtrst1_default: wdtrst1_default { 1721 function = "WDTRST1"; 1722 groups = "WDTRST1"; 1723 }; 1724 1725 pinctrl_wdtrst2_default: wdtrst2_default { 1726 function = "WDTRST2"; 1727 groups = "WDTRST2"; 1728 }; 1729}; 1730