1// SPDX-License-Identifier: GPL-2.0+ 2#include <dt-bindings/interrupt-controller/arm-gic.h> 3#include <dt-bindings/gpio/aspeed-gpio.h> 4#include "skeleton.dtsi" 5 6/ { 7 model = "Aspeed BMC"; 8 compatible = "aspeed,ast2600"; 9 #address-cells = <1>; 10 #size-cells = <1>; 11 interrupt-parent = <&gic>; 12 13 aliases { 14 i2c0 = &i2c0; 15 i2c1 = &i2c1; 16 i2c2 = &i2c2; 17 i2c3 = &i2c3; 18 i2c4 = &i2c4; 19 i2c5 = &i2c5; 20 i2c6 = &i2c6; 21 i2c7 = &i2c7; 22 i2c8 = &i2c8; 23 i2c9 = &i2c9; 24 i2c10 = &i2c10; 25 i2c11 = &i2c11; 26 i2c12 = &i2c12; 27 i2c13 = &i2c13; 28 i2c14 = &i2c14; 29 i2c15 = &i2c15; 30 serial0 = &uart1; 31 serial1 = &uart2; 32 serial2 = &uart3; 33 serial3 = &uart4; 34 serial4 = &uart5; 35 serial5 = &uart6; 36 serial6 = &uart7; 37 serial7 = &uart8; 38 serial8 = &uart9; 39 serial9 = &uart10; 40 serial10 = &uart11; 41 serial11 = &uart12; 42 serial12 = &uart13; 43 }; 44 45 cpus { 46 #address-cells = <1>; 47 #size-cells = <0>; 48 enable-method = "aspeed,ast2600-smp"; 49 50 cpu@0 { 51 compatible = "arm,cortex-a7"; 52 device_type = "cpu"; 53 reg = <0>; 54 }; 55 56 cpu@1 { 57 compatible = "arm,cortex-a7"; 58 device_type = "cpu"; 59 reg = <1>; 60 }; 61 62 }; 63 64 timer { 65 compatible = "arm,armv7-timer"; 66 interrupt-parent = <&gic>; 67 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 68 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 69 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 70 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 71 }; 72 73 reserved-memory { 74 #address-cells = <1>; 75 #size-cells = <1>; 76 ranges; 77 78 gfx_memory: framebuffer { 79 size = <0x01000000>; 80 alignment = <0x01000000>; 81 compatible = "shared-dma-pool"; 82 reusable; 83 }; 84 85 video_memory: video { 86 size = <0x04000000>; 87 alignment = <0x01000000>; 88 compatible = "shared-dma-pool"; 89 no-map; 90 }; 91 }; 92 93 ahb { 94 compatible = "simple-bus"; 95 #address-cells = <1>; 96 #size-cells = <1>; 97 device_type = "soc"; 98 ranges; 99 100 gic: interrupt-controller@40461000 { 101 compatible = "arm,cortex-a7-gic"; 102 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 103 #interrupt-cells = <3>; 104 interrupt-controller; 105 interrupt-parent = <&gic>; 106 reg = <0x40461000 0x1000>, 107 <0x40462000 0x1000>, 108 <0x40464000 0x2000>, 109 <0x40466000 0x2000>; 110 }; 111 112 ahbc: ahbc@1e600000 { 113 compatible = "aspeed,aspeed-ahbc"; 114 reg = < 0x1e600000 0x100>; 115 }; 116 117 fmc: flash-controller@1e620000 { 118 reg = < 0x1e620000 0xc4 119 0x20000000 0x10000000 >; 120 #address-cells = <1>; 121 #size-cells = <0>; 122 compatible = "aspeed,ast2600-fmc"; 123 status = "disabled"; 124 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 125 clocks = <&scu ASPEED_CLK_AHB>; 126 num-cs = <3>; 127 flash@0 { 128 reg = < 0 >; 129 compatible = "jedec,spi-nor"; 130 status = "disabled"; 131 }; 132 flash@1 { 133 reg = < 1 >; 134 compatible = "jedec,spi-nor"; 135 status = "disabled"; 136 }; 137 flash@2 { 138 reg = < 2 >; 139 compatible = "jedec,spi-nor"; 140 status = "disabled"; 141 }; 142 }; 143 144 spi1: flash-controller@1e630000 { 145 reg = < 0x1e630000 0xc4 146 0x30000000 0x08000000 >; 147 #address-cells = <1>; 148 #size-cells = <0>; 149 compatible = "aspeed,ast2600-spi"; 150 clocks = <&scu ASPEED_CLK_AHB>; 151 num-cs = <2>; 152 status = "disabled"; 153 flash@0 { 154 reg = < 0 >; 155 compatible = "jedec,spi-nor"; 156 status = "disabled"; 157 }; 158 flash@1 { 159 reg = < 1 >; 160 compatible = "jedec,spi-nor"; 161 status = "disabled"; 162 }; 163 }; 164 165 spi2: flash-controller@1e631000 { 166 reg = < 0x1e631000 0xc4 167 0x50000000 0x08000000 >; 168 #address-cells = <1>; 169 #size-cells = <0>; 170 compatible = "aspeed,ast2600-spi"; 171 clocks = <&scu ASPEED_CLK_AHB>; 172 num-cs = <3>; 173 status = "disabled"; 174 flash@0 { 175 reg = < 0 >; 176 compatible = "jedec,spi-nor"; 177 status = "disabled"; 178 }; 179 flash@1 { 180 reg = < 1 >; 181 compatible = "jedec,spi-nor"; 182 status = "disabled"; 183 }; 184 flash@2 { 185 reg = < 2 >; 186 compatible = "jedec,spi-nor"; 187 status = "disabled"; 188 }; 189 }; 190 191 edac: sdram@1e6e0000 { 192 compatible = "aspeed,ast2600-sdram-edac"; 193 reg = <0x1e6e0000 0x174>; 194 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 195 }; 196 197 mdio: ethernet@1e650000 { 198 compatible = "aspeed,aspeed-mdio"; 199 reg = <0x1e650000 0x40>; 200 resets = <&rst ASPEED_RESET_MII>; 201 status = "disabled"; 202 }; 203 204 mac1: ftgmac@1e660000 { 205 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 206 reg = <0x1e660000 0x180>, <0x1e650000 0x4>; 207 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 208 clocks = <&scu ASPEED_CLK_GATE_MAC1CLK>; 209 status = "disabled"; 210 }; 211 212 mac2: ftgmac@1e680000 { 213 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 214 reg = <0x1e680000 0x180>, <0x1e650008 0x4>; 215 #address-cells = <1>; 216 #size-cells = <0>; 217 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 218 clocks = <&scu ASPEED_CLK_GATE_MAC2CLK>; 219 status = "disabled"; 220 }; 221 222 mac3: ftgmac@1e670000 { 223 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 224 reg = <0x1e670000 0x180>, <0x1e650010 0x4>; 225 #address-cells = <1>; 226 #size-cells = <0>; 227 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 228 clocks = <&scu ASPEED_CLK_GATE_MAC3CLK>; 229 status = "disabled"; 230 }; 231 232 mac4: ftgmac@1e690000 { 233 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 234 reg = <0x1e690000 0x180>, <0x1e650018 0x4>; 235 #address-cells = <1>; 236 #size-cells = <0>; 237 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 238 clocks = <&scu ASPEED_CLK_GATE_MAC4CLK>; 239 status = "disabled"; 240 }; 241 242 ehci0: usb@1e6a1000 { 243 compatible = "aspeed,aspeed-ehci", "usb-ehci"; 244 reg = <0x1e6a1000 0x100>; 245 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 246 clocks = <&scu ASPEED_CLK_GATE_USBPORT1CLK>; 247 pinctrl-names = "default"; 248 pinctrl-0 = <&pinctrl_usb2ah_default>; 249 status = "disabled"; 250 }; 251 252 ehci1: usb@1e6a3000 { 253 compatible = "aspeed,aspeed-ehci", "usb-ehci"; 254 reg = <0x1e6a3000 0x100>; 255 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 256 clocks = <&scu ASPEED_CLK_GATE_USBPORT2CLK>; 257 pinctrl-names = "default"; 258 pinctrl-0 = <&pinctrl_usb2bh_default>; 259 status = "disabled"; 260 }; 261 262 apb { 263 compatible = "simple-bus"; 264 #address-cells = <1>; 265 #size-cells = <1>; 266 ranges; 267 268 syscon: syscon@1e6e2000 { 269 compatible = "aspeed,g6-scu", "syscon", "simple-mfd"; 270 reg = <0x1e6e2000 0x1000>; 271 #address-cells = <1>; 272 #size-cells = <1>; 273 #clock-cells = <1>; 274 #reset-cells = <1>; 275 ranges = <0 0x1e6e2000 0x1000>; 276 277 pinctrl: pinctrl { 278 compatible = "aspeed,g6-pinctrl"; 279 aspeed,external-nodes = <&gfx &lhc>; 280 281 }; 282 283 vga_scratch: scratch { 284 compatible = "aspeed,bmc-misc"; 285 }; 286 287 scu_ic0: interrupt-controller@0 { 288 #interrupt-cells = <1>; 289 compatible = "aspeed,ast2600-scu-ic"; 290 reg = <0x560 0x10>; 291 interrupt-parent = <&gic>; 292 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 293 interrupt-controller; 294 }; 295 296 scu_ic1: interrupt-controller@1 { 297 #interrupt-cells = <1>; 298 compatible = "aspeed,ast2600-scu-ic"; 299 reg = <0x570 0x10>; 300 interrupt-parent = <&gic>; 301 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 302 interrupt-controller; 303 }; 304 305 }; 306 307 smp-memram@0 { 308 compatible = "aspeed,ast2600-smpmem", "syscon"; 309 reg = <0x1e6e2180 0x40>; 310 }; 311 312 gfx: display@1e6e6000 { 313 compatible = "aspeed,ast2500-gfx", "syscon"; 314 reg = <0x1e6e6000 0x1000>; 315 reg-io-width = <4>; 316 }; 317 318 pcie_bridge0: pcie@1e6ed000 { 319 compatible = "aspeed,ast2600-pcie"; 320 #address-cells = <3>; 321 #size-cells = <2>; 322 reg = <0x1e6ed000 0x100>; 323 ranges = <0x81000000 0x0 0x0 0x0 0x0 0x10000 /* downstream I/O */ 324 0x82000000 0x0 0x60000000 0x60000000 0x0 0x10000000>; /* non-prefetchable memory */ 325 device_type = "pci"; 326 bus-range = <0x00 0xff>; 327 resets = <&rst ASPEED_RESET_PCIE_DEV_O>; 328 cfg-handle = <&pcie_cfg0>; 329 pinctrl-names = "default"; 330 pinctrl-0 = <&pinctrl_pcie0rc_default>; 331 332 status = "disabled"; 333 }; 334 335 pcie_bridge1: pcie@1e6ed200 { 336 compatible = "aspeed,ast2600-pcie"; 337 #address-cells = <3>; 338 #size-cells = <2>; 339 reg = <0x1e6ed200 0x100>; 340 ranges = <0x81000000 0x0 0x0 0x10000 0x00 0x10000 /* downstream I/O */ 341 0x82000000 0x0 0x70000000 0x70000000 0x0 0x10000000>; /* non-prefetchable memory */ 342 device_type = "pci"; 343 bus-range = <0x00 0xff>; 344 resets = <&rst ASPEED_RESET_PCIE_RC_O>; 345 cfg-handle = <&pcie_cfg1>; 346 pinctrl-names = "default"; 347 pinctrl-0 = <&pinctrl_pcie1rc_default>; 348 349 status = "disabled"; 350 }; 351 352 sdhci: sdhci@1e740000 { 353 #interrupt-cells = <1>; 354 compatible = "aspeed,aspeed-sdhci-irq", "simple-mfd"; 355 reg = <0x1e740000 0x1000>; 356 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 357 interrupt-controller; 358 clocks = <&scu ASPEED_CLK_GATE_SDCLK>, <&scu ASPEED_CLK_GATE_SDEXTCLK>; 359 clock-names = "ctrlclk", "extclk"; 360 #address-cells = <1>; 361 #size-cells = <1>; 362 ranges = <0x0 0x1e740000 0x1000>; 363 364 sdhci_slot0: sdhci_slot0@100 { 365 compatible = "aspeed,sdhci-ast2600"; 366 reg = <0x100 0x100>; 367 interrupts = <0>; 368 interrupt-parent = <&sdhci>; 369 sdhci,auto-cmd12; 370 clocks = <&scu ASPEED_CLK_SDIO>; 371 status = "disabled"; 372 }; 373 374 sdhci_slot1: sdhci_slot1@200 { 375 compatible = "aspeed,sdhci-ast2600"; 376 reg = <0x200 0x100>; 377 interrupts = <1>; 378 interrupt-parent = <&sdhci>; 379 sdhci,auto-cmd12; 380 clocks = <&scu ASPEED_CLK_SDIO>; 381 status = "disabled"; 382 }; 383 }; 384 385 emmc: emmc@1e750000 { 386 #interrupt-cells = <1>; 387 compatible = "aspeed,aspeed-emmc-irq", "simple-mfd"; 388 reg = <0x1e750000 0x1000>; 389 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 390 interrupt-controller; 391 clocks = <&scu ASPEED_CLK_GATE_EMMCCLK>, <&scu ASPEED_CLK_GATE_EMMCEXTCLK>; 392 clock-names = "ctrlclk", "extclk"; 393 #address-cells = <1>; 394 #size-cells = <1>; 395 ranges = <0x0 0x1e750000 0x1000>; 396 397 emmc_slot0: emmc_slot0@100 { 398 compatible = "aspeed,emmc-ast2600"; 399 reg = <0x100 0x100>; 400 interrupts = <0>; 401 interrupt-parent = <&emmc>; 402 clocks = <&scu ASPEED_CLK_EMMC>; 403 status = "disabled"; 404 }; 405 }; 406 407 h2x: h2x@1e770000 { 408 compatible = "aspeed,ast2600-h2x"; 409 reg = <0x1e770000 0x100>; 410 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 411 resets = <&rst ASPEED_RESET_H2X>; 412 #address-cells = <1>; 413 #size-cells = <1>; 414 ranges = <0x0 0x1e770000 0x100>; 415 416 status = "disabled"; 417 418 pcie_cfg0: cfg0@80 { 419 reg = <0x80 0x80>; 420 compatible = "aspeed,ast2600-pcie-cfg"; 421 }; 422 423 pcie_cfg1: cfg1@C0 { 424 compatible = "aspeed,ast2600-pcie-cfg"; 425 reg = <0xC0 0x80>; 426 }; 427 }; 428 429 gpio0: gpio@1e780000 { 430 compatible = "aspeed,ast2600-gpio"; 431 reg = <0x1e780000 0x1000>; 432 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 433 #gpio-cells = <2>; 434 gpio-controller; 435 interrupt-controller; 436 gpio-ranges = <&pinctrl 0 0 220>; 437 }; 438 439 gpio1: gpio@1e780800 { 440 compatible = "aspeed,ast2600-gpio"; 441 reg = <0x1e780800 0x800>; 442 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 443 #gpio-cells = <2>; 444 gpio-controller; 445 interrupt-controller; 446 gpio-ranges = <&pinctrl 0 0 208>; 447 }; 448 449 uart1: serial@1e783000 { 450 compatible = "ns16550a"; 451 reg = <0x1e783000 0x20>; 452 reg-shift = <2>; 453 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 454 clocks = <&scu ASPEED_CLK_GATE_UART1CLK>; 455 clock-frequency = <1846154>; 456 no-loopback-test; 457 status = "disabled"; 458 }; 459 460 uart5: serial@1e784000 { 461 compatible = "ns16550a"; 462 reg = <0x1e784000 0x1000>; 463 reg-shift = <2>; 464 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 465 clocks = <&scu ASPEED_CLK_GATE_UART5CLK>; 466 clock-frequency = <1846154>; 467 no-loopback-test; 468 status = "disabled"; 469 }; 470 471 wdt1: watchdog@1e785000 { 472 compatible = "aspeed,ast2600-wdt"; 473 reg = <0x1e785000 0x40>; 474 }; 475 476 wdt2: watchdog@1e785040 { 477 compatible = "aspeed,ast2600-wdt"; 478 reg = <0x1e785040 0x40>; 479 }; 480 481 wdt3: watchdog@1e785080 { 482 compatible = "aspeed,ast2600-wdt"; 483 reg = <0x1e785080 0x40>; 484 }; 485 486 wdt4: watchdog@1e7850C0 { 487 compatible = "aspeed,ast2600-wdt"; 488 reg = <0x1e7850C0 0x40>; 489 }; 490 491 lpc: lpc@1e789000 { 492 compatible = "aspeed,ast-lpc", "simple-mfd", "syscon"; 493 reg = <0x1e789000 0x200>; 494 495 #address-cells = <1>; 496 #size-cells = <1>; 497 ranges = <0x0 0x1e789000 0x1000>; 498 499 lpc_bmc: lpc-bmc@0 { 500 compatible = "aspeed,ast2600-lpc-bmc", "simple-mfd", "syscon"; 501 reg = <0x0 0x80>; 502 reg-io-width = <4>; 503 #address-cells = <1>; 504 #size-cells = <1>; 505 ranges = <0x0 0x0 0x80>; 506 507 kcs1: kcs1@0 { 508 compatible = "aspeed,ast2600-kcs-bmc"; 509 reg = <0x0 0x80>; 510 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 511 kcs_chan = <1>; 512 kcs_addr = <0xCA0>; 513 status = "disabled"; 514 }; 515 516 kcs2: kcs2@0 { 517 compatible = "aspeed,ast2600-kcs-bmc"; 518 reg = <0x0 0x80>; 519 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 520 kcs_chan = <2>; 521 kcs_addr = <0xCA8>; 522 status = "disabled"; 523 }; 524 525 kcs3: kcs3@0 { 526 compatible = "aspeed,ast2600-kcs-bmc"; 527 reg = <0x0 0x80>; 528 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 529 kcs_chan = <3>; 530 kcs_addr = <0xCA2>; 531 }; 532 533 kcs4: kcs4@0 { 534 compatible = "aspeed,ast2600-kcs-bmc"; 535 reg = <0x0 0x120>; 536 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 537 kcs_chan = <4>; 538 kcs_addr = <0xCA4>; 539 status = "disabled"; 540 }; 541 542 }; 543 544 lpc_host: lpc-host@80 { 545 compatible = "aspeed,ast2600-lpc-host", "simple-mfd", "syscon"; 546 reg = <0x80 0x1e0>; 547 reg-io-width = <4>; 548 549 #address-cells = <1>; 550 #size-cells = <1>; 551 ranges = <0x0 0x80 0x1e0>; 552 553 lpc_ctrl: lpc-ctrl@0 { 554 compatible = "aspeed,ast2600-lpc-ctrl"; 555 reg = <0x0 0x80>; 556 status = "disabled"; 557 }; 558 559 lpc_snoop: lpc-snoop@0 { 560 compatible = "aspeed,ast2600-lpc-snoop"; 561 reg = <0x0 0x80>; 562 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 563 snoop-ports = <0x80>; 564 status = "disabled"; 565 }; 566 567 lhc: lhc@20 { 568 compatible = "aspeed,ast2600-lhc"; 569 reg = <0x20 0x24 0x48 0x8>; 570 }; 571 572 lpc_reset: reset-controller@18 { 573 compatible = "aspeed,ast2600-lpc-reset"; 574 reg = <0x18 0x4>; 575 #reset-cells = <1>; 576 status = "disabled"; 577 }; 578 579 ibt: ibt@c0 { 580 compatible = "aspeed,ast2600-ibt-bmc"; 581 reg = <0xc0 0x18>; 582 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 583 status = "disabled"; 584 }; 585 586 sio_regs: regs { 587 compatible = "aspeed,bmc-misc"; 588 }; 589 590 mbox: mbox@180 { 591 compatible = "aspeed,ast2600-mbox"; 592 reg = <0x180 0x5c>; 593 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 594 #mbox-cells = <1>; 595 status = "disabled"; 596 }; 597 }; 598 }; 599 600 uart2: serial@1e78d000 { 601 compatible = "ns16550a"; 602 reg = <0x1e78d000 0x20>; 603 reg-shift = <2>; 604 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 605 clocks = <&scu ASPEED_CLK_GATE_UART2CLK>; 606 clock-frequency = <1846154>; 607 no-loopback-test; 608 status = "disabled"; 609 }; 610 611 uart3: serial@1e78e000 { 612 compatible = "ns16550a"; 613 reg = <0x1e78e000 0x20>; 614 reg-shift = <2>; 615 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 616 clocks = <&scu ASPEED_CLK_GATE_UART3CLK>; 617 clock-frequency = <1846154>; 618 no-loopback-test; 619 status = "disabled"; 620 }; 621 622 uart4: serial@1e78f000 { 623 compatible = "ns16550a"; 624 reg = <0x1e78f000 0x20>; 625 reg-shift = <2>; 626 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 627 clocks = <&scu ASPEED_CLK_GATE_UART4CLK>; 628 clock-frequency = <1846154>; 629 no-loopback-test; 630 status = "disabled"; 631 }; 632 633 i2c: bus@1e78a000 { 634 compatible = "simple-bus"; 635 #address-cells = <1>; 636 #size-cells = <1>; 637 ranges = <0 0x1e78a000 0x1000>; 638 }; 639 640 fsim0: fsi@1e79b000 { 641 compatible = "aspeed,ast2600-fsi-master", "fsi-master"; 642 reg = <0x1e79b000 0x94>; 643 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 644 pinctrl-names = "default"; 645 pinctrl-0 = <&pinctrl_fsi1_default>; 646 clocks = <&scu ASPEED_CLK_GATE_FSICLK>; 647 status = "disabled"; 648 }; 649 650 fsim1: fsi@1e79b100 { 651 compatible = "aspeed,ast2600-fsi-master", "fsi-master"; 652 reg = <0x1e79b100 0x94>; 653 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 654 pinctrl-names = "default"; 655 pinctrl-0 = <&pinctrl_fsi2_default>; 656 clocks = <&scu ASPEED_CLK_GATE_FSICLK>; 657 status = "disabled"; 658 }; 659 660 uart6: serial@1e790000 { 661 compatible = "ns16550a"; 662 reg = <0x1e790000 0x20>; 663 reg-shift = <2>; 664 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 665 clocks = <&scu ASPEED_CLK_GATE_UART6CLK>; 666 clock-frequency = <1846154>; 667 no-loopback-test; 668 status = "disabled"; 669 }; 670 671 uart7: serial@1e790100 { 672 compatible = "ns16550a"; 673 reg = <0x1e790100 0x20>; 674 reg-shift = <2>; 675 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 676 clocks = <&scu ASPEED_CLK_GATE_UART7CLK>; 677 clock-frequency = <1846154>; 678 no-loopback-test; 679 status = "disabled"; 680 }; 681 682 uart8: serial@1e790200 { 683 compatible = "ns16550a"; 684 reg = <0x1e790200 0x20>; 685 reg-shift = <2>; 686 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 687 clocks = <&scu ASPEED_CLK_GATE_UART8CLK>; 688 clock-frequency = <1846154>; 689 no-loopback-test; 690 status = "disabled"; 691 }; 692 693 uart9: serial@1e790300 { 694 compatible = "ns16550a"; 695 reg = <0x1e790300 0x20>; 696 reg-shift = <2>; 697 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 698 clocks = <&scu ASPEED_CLK_GATE_UART9CLK>; 699 clock-frequency = <1846154>; 700 no-loopback-test; 701 status = "disabled"; 702 }; 703 704 uart10: serial@1e790400 { 705 compatible = "ns16550a"; 706 reg = <0x1e790400 0x20>; 707 reg-shift = <2>; 708 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 709 clocks = <&scu ASPEED_CLK_GATE_UART10CLK>; 710 clock-frequency = <1846154>; 711 no-loopback-test; 712 status = "disabled"; 713 }; 714 715 uart11: serial@1e790500 { 716 compatible = "ns16550a"; 717 reg = <0x1e790400 0x20>; 718 reg-shift = <2>; 719 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 720 clocks = <&scu ASPEED_CLK_GATE_UART11CLK>; 721 clock-frequency = <1846154>; 722 no-loopback-test; 723 status = "disabled"; 724 }; 725 726 uart12: serial@1e790600 { 727 compatible = "ns16550a"; 728 reg = <0x1e790600 0x20>; 729 reg-shift = <2>; 730 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 731 clocks = <&scu ASPEED_CLK_GATE_UART12CLK>; 732 clock-frequency = <1846154>; 733 no-loopback-test; 734 status = "disabled"; 735 }; 736 737 uart13: serial@1e790700 { 738 compatible = "ns16550a"; 739 reg = <0x1e790700 0x20>; 740 reg-shift = <2>; 741 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 742 clocks = <&scu ASPEED_CLK_GATE_UART13CLK>; 743 clock-frequency = <1846154>; 744 no-loopback-test; 745 status = "disabled"; 746 }; 747 748 749 750 }; 751 752 }; 753 754}; 755 756&i2c { 757 i2cglobal: i2cg@00 { 758 compatible = "aspeed,ast2600-i2c-global"; 759 reg = <0x0 0x40>; 760 resets = <&rst ASPEED_RESET_I2C>; 761#if 0 762 new-mode; 763#endif 764 }; 765 766 i2c0: i2c@80 { 767 #address-cells = <1>; 768 #size-cells = <0>; 769 #interrupt-cells = <1>; 770 771 reg = <0x80 0x80 0xC00 0x20>; 772 compatible = "aspeed,ast2600-i2c-bus"; 773 bus-frequency = <100000>; 774 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 775 clocks = <&scu ASPEED_CLK_APB2>; 776 status = "disabled"; 777 }; 778 779 i2c1: i2c@100 { 780 #address-cells = <1>; 781 #size-cells = <0>; 782 #interrupt-cells = <1>; 783 784 reg = <0x100 0x80 0xC20 0x20>; 785 compatible = "aspeed,ast2600-i2c-bus"; 786 bus-frequency = <100000>; 787 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 788 clocks = <&scu ASPEED_CLK_APB2>; 789 status = "disabled"; 790 }; 791 792 i2c2: i2c@180 { 793 #address-cells = <1>; 794 #size-cells = <0>; 795 #interrupt-cells = <1>; 796 797 reg = <0x180 0x80 0xC40 0x20>; 798 compatible = "aspeed,ast2600-i2c-bus"; 799 bus-frequency = <100000>; 800 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 801 clocks = <&scu ASPEED_CLK_APB2>; 802 }; 803 804 i2c3: i2c@200 { 805 #address-cells = <1>; 806 #size-cells = <0>; 807 #interrupt-cells = <1>; 808 809 reg = <0x200 0x40 0xC60 0x20>; 810 compatible = "aspeed,ast2600-i2c-bus"; 811 bus-frequency = <100000>; 812 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 813 clocks = <&scu ASPEED_CLK_APB2>; 814 }; 815 816 i2c4: i2c@280 { 817 #address-cells = <1>; 818 #size-cells = <0>; 819 #interrupt-cells = <1>; 820 821 reg = <0x280 0x80 0xC80 0x20>; 822 compatible = "aspeed,ast2600-i2c-bus"; 823 bus-frequency = <100000>; 824 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 825 clocks = <&scu ASPEED_CLK_APB2>; 826 }; 827 828 i2c5: i2c@300 { 829 #address-cells = <1>; 830 #size-cells = <0>; 831 #interrupt-cells = <1>; 832 833 reg = <0x300 0x40 0xCA0 0x20>; 834 compatible = "aspeed,ast2600-i2c-bus"; 835 bus-frequency = <100000>; 836 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 837 clocks = <&scu ASPEED_CLK_APB2>; 838 }; 839 840 i2c6: i2c@380 { 841 #address-cells = <1>; 842 #size-cells = <0>; 843 #interrupt-cells = <1>; 844 845 reg = <0x380 0x80 0xCC0 0x20>; 846 compatible = "aspeed,ast2600-i2c-bus"; 847 bus-frequency = <100000>; 848 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 849 clocks = <&scu ASPEED_CLK_APB2>; 850 }; 851 852 i2c7: i2c@400 { 853 #address-cells = <1>; 854 #size-cells = <0>; 855 #interrupt-cells = <1>; 856 857 reg = <0x400 0x80 0xCE0 0x20>; 858 compatible = "aspeed,ast2600-i2c-bus"; 859 bus-frequency = <100000>; 860 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 861 clocks = <&scu ASPEED_CLK_APB2>; 862 }; 863 864 i2c8: i2c@480 { 865 #address-cells = <1>; 866 #size-cells = <0>; 867 #interrupt-cells = <1>; 868 869 reg = <0x480 0x80 0xD00 0x20>; 870 compatible = "aspeed,ast2600-i2c-bus"; 871 bus-frequency = <100000>; 872 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 873 clocks = <&scu ASPEED_CLK_APB2>; 874 }; 875 876 i2c9: i2c@500 { 877 #address-cells = <1>; 878 #size-cells = <0>; 879 #interrupt-cells = <1>; 880 881 reg = <0x500 0x80 0xD20 0x20>; 882 compatible = "aspeed,ast2600-i2c-bus"; 883 bus-frequency = <100000>; 884 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 885 clocks = <&scu ASPEED_CLK_APB2>; 886 status = "disabled"; 887 }; 888 889 i2c10: i2c@580 { 890 #address-cells = <1>; 891 #size-cells = <0>; 892 #interrupt-cells = <1>; 893 894 reg = <0x580 0x80 0xD40 0x20>; 895 compatible = "aspeed,ast2600-i2c-bus"; 896 bus-frequency = <100000>; 897 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 898 clocks = <&scu ASPEED_CLK_APB2>; 899 status = "disabled"; 900 }; 901 902 i2c11: i2c@600 { 903 #address-cells = <1>; 904 #size-cells = <0>; 905 #interrupt-cells = <1>; 906 907 reg = <0x600 0x80 0xD60 0x20>; 908 compatible = "aspeed,ast2600-i2c-bus"; 909 bus-frequency = <100000>; 910 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 911 clocks = <&scu ASPEED_CLK_APB2>; 912 status = "disabled"; 913 }; 914 915 i2c12: i2c@680 { 916 #address-cells = <1>; 917 #size-cells = <0>; 918 #interrupt-cells = <1>; 919 920 reg = <0x680 0x80 0xD80 0x20>; 921 compatible = "aspeed,ast2600-i2c-bus"; 922 bus-frequency = <100000>; 923 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 924 clocks = <&scu ASPEED_CLK_APB2>; 925 status = "disabled"; 926 }; 927 928 i2c13: i2c@700 { 929 #address-cells = <1>; 930 #size-cells = <0>; 931 #interrupt-cells = <1>; 932 933 reg = <0x700 0x80 0xDA0 0x20>; 934 compatible = "aspeed,ast2600-i2c-bus"; 935 bus-frequency = <100000>; 936 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 937 clocks = <&scu ASPEED_CLK_APB2>; 938 status = "disabled"; 939 }; 940 941 i2c14: i2c@780 { 942 #address-cells = <1>; 943 #size-cells = <0>; 944 #interrupt-cells = <1>; 945 946 reg = <0x780 0x80 0xDC0 0x20>; 947 compatible = "aspeed,ast2600-i2c-bus"; 948 bus-frequency = <100000>; 949 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 950 clocks = <&scu ASPEED_CLK_APB2>; 951 status = "disabled"; 952 }; 953 954 i2c15: i2c@800 { 955 #address-cells = <1>; 956 #size-cells = <0>; 957 #interrupt-cells = <1>; 958 959 reg = <0x800 0x80 0xDE0 0x20>; 960 compatible = "aspeed,ast2600-i2c-bus"; 961 bus-frequency = <100000>; 962 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 963 clocks = <&scu ASPEED_CLK_APB2>; 964 status = "disabled"; 965 }; 966 967}; 968 969&pinctrl { 970 pinctrl_fmcquad_default: fmcquad_default { 971 function = "FMCQUAD"; 972 groups = "FMCQUAD"; 973 }; 974 975 pinctrl_spi1_default: spi1_default { 976 function = "SPI1"; 977 groups = "SPI1"; 978 }; 979 980 pinctrl_spi1abr_default: spi1abr_default { 981 function = "SPI1ABR"; 982 groups = "SPI1ABR"; 983 }; 984 985 pinctrl_spi1cs1_default: spi1cs1_default { 986 function = "SPI1CS1"; 987 groups = "SPI1CS1"; 988 }; 989 990 pinctrl_spi1wp_default: spi1wp_default { 991 function = "SPI1WP"; 992 groups = "SPI1WP"; 993 }; 994 995 pinctrl_spi1quad_default: spi1quad_default { 996 function = "SPI1QUAD"; 997 groups = "SPI1QUAD"; 998 }; 999 1000 pinctrl_spi2_default: spi2_default { 1001 function = "SPI2"; 1002 groups = "SPI2"; 1003 }; 1004 1005 pinctrl_spi2cs1_default: spi2cs1_default { 1006 function = "SPI2CS1"; 1007 groups = "SPI2CS1"; 1008 }; 1009 1010 pinctrl_spi2cs2_default: spi2cs2_default { 1011 function = "SPI2CS2"; 1012 groups = "SPI2CS2"; 1013 }; 1014 1015 pinctrl_spi2quad_default: spi2quad_default { 1016 function = "SPI2QUAD"; 1017 groups = "SPI2QUAD"; 1018 }; 1019 1020 pinctrl_acpi_default: acpi_default { 1021 function = "ACPI"; 1022 groups = "ACPI"; 1023 }; 1024 1025 pinctrl_adc0_default: adc0_default { 1026 function = "ADC0"; 1027 groups = "ADC0"; 1028 }; 1029 1030 pinctrl_adc1_default: adc1_default { 1031 function = "ADC1"; 1032 groups = "ADC1"; 1033 }; 1034 1035 pinctrl_adc10_default: adc10_default { 1036 function = "ADC10"; 1037 groups = "ADC10"; 1038 }; 1039 1040 pinctrl_adc11_default: adc11_default { 1041 function = "ADC11"; 1042 groups = "ADC11"; 1043 }; 1044 1045 pinctrl_adc12_default: adc12_default { 1046 function = "ADC12"; 1047 groups = "ADC12"; 1048 }; 1049 1050 pinctrl_adc13_default: adc13_default { 1051 function = "ADC13"; 1052 groups = "ADC13"; 1053 }; 1054 1055 pinctrl_adc14_default: adc14_default { 1056 function = "ADC14"; 1057 groups = "ADC14"; 1058 }; 1059 1060 pinctrl_adc15_default: adc15_default { 1061 function = "ADC15"; 1062 groups = "ADC15"; 1063 }; 1064 1065 pinctrl_adc2_default: adc2_default { 1066 function = "ADC2"; 1067 groups = "ADC2"; 1068 }; 1069 1070 pinctrl_adc3_default: adc3_default { 1071 function = "ADC3"; 1072 groups = "ADC3"; 1073 }; 1074 1075 pinctrl_adc4_default: adc4_default { 1076 function = "ADC4"; 1077 groups = "ADC4"; 1078 }; 1079 1080 pinctrl_adc5_default: adc5_default { 1081 function = "ADC5"; 1082 groups = "ADC5"; 1083 }; 1084 1085 pinctrl_adc6_default: adc6_default { 1086 function = "ADC6"; 1087 groups = "ADC6"; 1088 }; 1089 1090 pinctrl_adc7_default: adc7_default { 1091 function = "ADC7"; 1092 groups = "ADC7"; 1093 }; 1094 1095 pinctrl_adc8_default: adc8_default { 1096 function = "ADC8"; 1097 groups = "ADC8"; 1098 }; 1099 1100 pinctrl_adc9_default: adc9_default { 1101 function = "ADC9"; 1102 groups = "ADC9"; 1103 }; 1104 1105 pinctrl_bmcint_default: bmcint_default { 1106 function = "BMCINT"; 1107 groups = "BMCINT"; 1108 }; 1109 1110 pinctrl_ddcclk_default: ddcclk_default { 1111 function = "DDCCLK"; 1112 groups = "DDCCLK"; 1113 }; 1114 1115 pinctrl_ddcdat_default: ddcdat_default { 1116 function = "DDCDAT"; 1117 groups = "DDCDAT"; 1118 }; 1119 1120 pinctrl_espi_default: espi_default { 1121 function = "ESPI"; 1122 groups = "ESPI"; 1123 }; 1124 1125 pinctrl_fsi1_default: fsi1_default { 1126 function = "FSI1"; 1127 groups = "FSI1"; 1128 }; 1129 1130 pinctrl_fsi2_default: fsi2_default { 1131 function = "FSI2"; 1132 groups = "FSI2"; 1133 }; 1134 1135 pinctrl_fwspics1_default: fwspics1_default { 1136 function = "FWSPICS1"; 1137 groups = "FWSPICS1"; 1138 }; 1139 1140 pinctrl_fwspics2_default: fwspics2_default { 1141 function = "FWSPICS2"; 1142 groups = "FWSPICS2"; 1143 }; 1144 1145 pinctrl_gpid0_default: gpid0_default { 1146 function = "GPID0"; 1147 groups = "GPID0"; 1148 }; 1149 1150 pinctrl_gpid2_default: gpid2_default { 1151 function = "GPID2"; 1152 groups = "GPID2"; 1153 }; 1154 1155 pinctrl_gpid4_default: gpid4_default { 1156 function = "GPID4"; 1157 groups = "GPID4"; 1158 }; 1159 1160 pinctrl_gpid6_default: gpid6_default { 1161 function = "GPID6"; 1162 groups = "GPID6"; 1163 }; 1164 1165 pinctrl_gpie0_default: gpie0_default { 1166 function = "GPIE0"; 1167 groups = "GPIE0"; 1168 }; 1169 1170 pinctrl_gpie2_default: gpie2_default { 1171 function = "GPIE2"; 1172 groups = "GPIE2"; 1173 }; 1174 1175 pinctrl_gpie4_default: gpie4_default { 1176 function = "GPIE4"; 1177 groups = "GPIE4"; 1178 }; 1179 1180 pinctrl_gpie6_default: gpie6_default { 1181 function = "GPIE6"; 1182 groups = "GPIE6"; 1183 }; 1184 1185 pinctrl_i2c1_default: i2c1_default { 1186 function = "I2C1"; 1187 groups = "I2C1"; 1188 }; 1189 pinctrl_i2c2_default: i2c2_default { 1190 function = "I2C2"; 1191 groups = "I2C2"; 1192 }; 1193 1194 pinctrl_i2c3_default: i2c3_default { 1195 function = "I2C3"; 1196 groups = "I2C3"; 1197 }; 1198 1199 pinctrl_i2c4_default: i2c4_default { 1200 function = "I2C4"; 1201 groups = "I2C4"; 1202 }; 1203 1204 pinctrl_i2c5_default: i2c5_default { 1205 function = "I2C5"; 1206 groups = "I2C5"; 1207 }; 1208 1209 pinctrl_i2c6_default: i2c6_default { 1210 function = "I2C6"; 1211 groups = "I2C6"; 1212 }; 1213 1214 pinctrl_i2c7_default: i2c7_default { 1215 function = "I2C7"; 1216 groups = "I2C7"; 1217 }; 1218 1219 pinctrl_i2c8_default: i2c8_default { 1220 function = "I2C8"; 1221 groups = "I2C8"; 1222 }; 1223 1224 pinctrl_i2c9_default: i2c9_default { 1225 function = "I2C9"; 1226 groups = "I2C9"; 1227 }; 1228 1229 pinctrl_i2c10_default: i2c10_default { 1230 function = "I2C10"; 1231 groups = "I2C10"; 1232 }; 1233 1234 pinctrl_i2c11_default: i2c11_default { 1235 function = "I2C11"; 1236 groups = "I2C11"; 1237 }; 1238 1239 pinctrl_i2c12_default: i2c12_default { 1240 function = "I2C12"; 1241 groups = "I2C12"; 1242 }; 1243 1244 pinctrl_i2c13_default: i2c13_default { 1245 function = "I2C13"; 1246 groups = "I2C13"; 1247 }; 1248 1249 pinctrl_i2c14_default: i2c14_default { 1250 function = "I2C14"; 1251 groups = "I2C14"; 1252 }; 1253 1254 pinctrl_i2c15_default: i2c15_default { 1255 function = "I2C15"; 1256 groups = "I2C15"; 1257 }; 1258 1259 pinctrl_i2c16_default: i2c16_default { 1260 function = "I2C16"; 1261 groups = "I2C16"; 1262 }; 1263 1264 pinctrl_lad0_default: lad0_default { 1265 function = "LAD0"; 1266 groups = "LAD0"; 1267 }; 1268 1269 pinctrl_lad1_default: lad1_default { 1270 function = "LAD1"; 1271 groups = "LAD1"; 1272 }; 1273 1274 pinctrl_lad2_default: lad2_default { 1275 function = "LAD2"; 1276 groups = "LAD2"; 1277 }; 1278 1279 pinctrl_lad3_default: lad3_default { 1280 function = "LAD3"; 1281 groups = "LAD3"; 1282 }; 1283 1284 pinctrl_lclk_default: lclk_default { 1285 function = "LCLK"; 1286 groups = "LCLK"; 1287 }; 1288 1289 pinctrl_lframe_default: lframe_default { 1290 function = "LFRAME"; 1291 groups = "LFRAME"; 1292 }; 1293 1294 pinctrl_lpchc_default: lpchc_default { 1295 function = "LPCHC"; 1296 groups = "LPCHC"; 1297 }; 1298 1299 pinctrl_lpcpd_default: lpcpd_default { 1300 function = "LPCPD"; 1301 groups = "LPCPD"; 1302 }; 1303 1304 pinctrl_lpcplus_default: lpcplus_default { 1305 function = "LPCPLUS"; 1306 groups = "LPCPLUS"; 1307 }; 1308 1309 pinctrl_lpcpme_default: lpcpme_default { 1310 function = "LPCPME"; 1311 groups = "LPCPME"; 1312 }; 1313 1314 pinctrl_lpcrst_default: lpcrst_default { 1315 function = "LPCRST"; 1316 groups = "LPCRST"; 1317 }; 1318 1319 pinctrl_lpcsmi_default: lpcsmi_default { 1320 function = "LPCSMI"; 1321 groups = "LPCSMI"; 1322 }; 1323 1324 pinctrl_lsirq_default: lsirq_default { 1325 function = "LSIRQ"; 1326 groups = "LSIRQ"; 1327 }; 1328 1329 pinctrl_mac1link_default: mac1link_default { 1330 function = "MAC1LINK"; 1331 groups = "MAC1LINK"; 1332 }; 1333 1334 pinctrl_mac2link_default: mac2link_default { 1335 function = "MAC2LINK"; 1336 groups = "MAC2LINK"; 1337 }; 1338 1339 pinctrl_mac3link_default: mac3link_default { 1340 function = "MAC3LINK"; 1341 groups = "MAC3LINK"; 1342 }; 1343 1344 pinctrl_mac4link_default: mac4link_default { 1345 function = "MAC4LINK"; 1346 groups = "MAC4LINK"; 1347 }; 1348 1349 pinctrl_mdio1_default: mdio1_default { 1350 function = "MDIO1"; 1351 groups = "MDIO1"; 1352 }; 1353 1354 pinctrl_mdio2_default: mdio2_default { 1355 function = "MDIO2"; 1356 groups = "MDIO2"; 1357 }; 1358 1359 pinctrl_mdio3_default: mdio3_default { 1360 function = "MDIO3"; 1361 groups = "MDIO3"; 1362 }; 1363 1364 pinctrl_mdio4_default: mdio4_default { 1365 function = "MDIO4"; 1366 groups = "MDIO4"; 1367 }; 1368 1369 pinctrl_rmii1_default: rmii1_default { 1370 function = "RMII1"; 1371 groups = "RMII1"; 1372 }; 1373 1374 pinctrl_rmii2_default: rmii2_default { 1375 function = "RMII2"; 1376 groups = "RMII2"; 1377 }; 1378 1379 pinctrl_rmii3_default: rmii3_default { 1380 function = "RMII3"; 1381 groups = "RMII3"; 1382 }; 1383 1384 pinctrl_rmii4_default: rmii4_default { 1385 function = "RMII4"; 1386 groups = "RMII4"; 1387 }; 1388 1389 pinctrl_ncts1_default: ncts1_default { 1390 function = "NCTS1"; 1391 groups = "NCTS1"; 1392 }; 1393 1394 pinctrl_ncts2_default: ncts2_default { 1395 function = "NCTS2"; 1396 groups = "NCTS2"; 1397 }; 1398 1399 pinctrl_ncts3_default: ncts3_default { 1400 function = "NCTS3"; 1401 groups = "NCTS3"; 1402 }; 1403 1404 pinctrl_ncts4_default: ncts4_default { 1405 function = "NCTS4"; 1406 groups = "NCTS4"; 1407 }; 1408 1409 pinctrl_ndcd1_default: ndcd1_default { 1410 function = "NDCD1"; 1411 groups = "NDCD1"; 1412 }; 1413 1414 pinctrl_ndcd2_default: ndcd2_default { 1415 function = "NDCD2"; 1416 groups = "NDCD2"; 1417 }; 1418 1419 pinctrl_ndcd3_default: ndcd3_default { 1420 function = "NDCD3"; 1421 groups = "NDCD3"; 1422 }; 1423 1424 pinctrl_ndcd4_default: ndcd4_default { 1425 function = "NDCD4"; 1426 groups = "NDCD4"; 1427 }; 1428 1429 pinctrl_ndsr1_default: ndsr1_default { 1430 function = "NDSR1"; 1431 groups = "NDSR1"; 1432 }; 1433 1434 pinctrl_ndsr2_default: ndsr2_default { 1435 function = "NDSR2"; 1436 groups = "NDSR2"; 1437 }; 1438 1439 pinctrl_ndsr3_default: ndsr3_default { 1440 function = "NDSR3"; 1441 groups = "NDSR3"; 1442 }; 1443 1444 pinctrl_ndsr4_default: ndsr4_default { 1445 function = "NDSR4"; 1446 groups = "NDSR4"; 1447 }; 1448 1449 pinctrl_ndtr1_default: ndtr1_default { 1450 function = "NDTR1"; 1451 groups = "NDTR1"; 1452 }; 1453 1454 pinctrl_ndtr2_default: ndtr2_default { 1455 function = "NDTR2"; 1456 groups = "NDTR2"; 1457 }; 1458 1459 pinctrl_ndtr3_default: ndtr3_default { 1460 function = "NDTR3"; 1461 groups = "NDTR3"; 1462 }; 1463 1464 pinctrl_ndtr4_default: ndtr4_default { 1465 function = "NDTR4"; 1466 groups = "NDTR4"; 1467 }; 1468 1469 pinctrl_nri1_default: nri1_default { 1470 function = "NRI1"; 1471 groups = "NRI1"; 1472 }; 1473 1474 pinctrl_nri2_default: nri2_default { 1475 function = "NRI2"; 1476 groups = "NRI2"; 1477 }; 1478 1479 pinctrl_nri3_default: nri3_default { 1480 function = "NRI3"; 1481 groups = "NRI3"; 1482 }; 1483 1484 pinctrl_nri4_default: nri4_default { 1485 function = "NRI4"; 1486 groups = "NRI4"; 1487 }; 1488 1489 pinctrl_nrts1_default: nrts1_default { 1490 function = "NRTS1"; 1491 groups = "NRTS1"; 1492 }; 1493 1494 pinctrl_nrts2_default: nrts2_default { 1495 function = "NRTS2"; 1496 groups = "NRTS2"; 1497 }; 1498 1499 pinctrl_nrts3_default: nrts3_default { 1500 function = "NRTS3"; 1501 groups = "NRTS3"; 1502 }; 1503 1504 pinctrl_nrts4_default: nrts4_default { 1505 function = "NRTS4"; 1506 groups = "NRTS4"; 1507 }; 1508 1509 pinctrl_oscclk_default: oscclk_default { 1510 function = "OSCCLK"; 1511 groups = "OSCCLK"; 1512 }; 1513 1514 pinctrl_pewake_default: pewake_default { 1515 function = "PEWAKE"; 1516 groups = "PEWAKE"; 1517 }; 1518 1519 pinctrl_pnor_default: pnor_default { 1520 function = "PNOR"; 1521 groups = "PNOR"; 1522 }; 1523 1524 pinctrl_pwm0_default: pwm0_default { 1525 function = "PWM0"; 1526 groups = "PWM0"; 1527 }; 1528 1529 pinctrl_pwm1_default: pwm1_default { 1530 function = "PWM1"; 1531 groups = "PWM1"; 1532 }; 1533 1534 pinctrl_pwm2_default: pwm2_default { 1535 function = "PWM2"; 1536 groups = "PWM2"; 1537 }; 1538 1539 pinctrl_pwm3_default: pwm3_default { 1540 function = "PWM3"; 1541 groups = "PWM3"; 1542 }; 1543 1544 pinctrl_pwm4_default: pwm4_default { 1545 function = "PWM4"; 1546 groups = "PWM4"; 1547 }; 1548 1549 pinctrl_pwm5_default: pwm5_default { 1550 function = "PWM5"; 1551 groups = "PWM5"; 1552 }; 1553 1554 pinctrl_pwm6_default: pwm6_default { 1555 function = "PWM6"; 1556 groups = "PWM6"; 1557 }; 1558 1559 pinctrl_pwm7_default: pwm7_default { 1560 function = "PWM7"; 1561 groups = "PWM7"; 1562 }; 1563 1564 pinctrl_rgmii1_default: rgmii1_default { 1565 function = "RGMII1"; 1566 groups = "RGMII1"; 1567 }; 1568 1569 pinctrl_rgmii2_default: rgmii2_default { 1570 function = "RGMII2"; 1571 groups = "RGMII2"; 1572 }; 1573 1574 pinctrl_rgmii3_default: rgmii3_default { 1575 function = "RGMII3"; 1576 groups = "RGMII3"; 1577 }; 1578 1579 pinctrl_rgmii4_default: rgmii4_default { 1580 function = "RGMII4"; 1581 groups = "RGMII4"; 1582 }; 1583 1584 pinctrl_rmii1_default: rmii1_default { 1585 function = "RMII1"; 1586 groups = "RMII1"; 1587 }; 1588 1589 pinctrl_rmii2_default: rmii2_default { 1590 function = "RMII2"; 1591 groups = "RMII2"; 1592 }; 1593 1594 pinctrl_rxd1_default: rxd1_default { 1595 function = "RXD1"; 1596 groups = "RXD1"; 1597 }; 1598 1599 pinctrl_rxd2_default: rxd2_default { 1600 function = "RXD2"; 1601 groups = "RXD2"; 1602 }; 1603 1604 pinctrl_rxd3_default: rxd3_default { 1605 function = "RXD3"; 1606 groups = "RXD3"; 1607 }; 1608 1609 pinctrl_rxd4_default: rxd4_default { 1610 function = "RXD4"; 1611 groups = "RXD4"; 1612 }; 1613 1614 pinctrl_salt1_default: salt1_default { 1615 function = "SALT1"; 1616 groups = "SALT1"; 1617 }; 1618 1619 pinctrl_salt10_default: salt10_default { 1620 function = "SALT10"; 1621 groups = "SALT10"; 1622 }; 1623 1624 pinctrl_salt11_default: salt11_default { 1625 function = "SALT11"; 1626 groups = "SALT11"; 1627 }; 1628 1629 pinctrl_salt12_default: salt12_default { 1630 function = "SALT12"; 1631 groups = "SALT12"; 1632 }; 1633 1634 pinctrl_salt13_default: salt13_default { 1635 function = "SALT13"; 1636 groups = "SALT13"; 1637 }; 1638 1639 pinctrl_salt14_default: salt14_default { 1640 function = "SALT14"; 1641 groups = "SALT14"; 1642 }; 1643 1644 pinctrl_salt2_default: salt2_default { 1645 function = "SALT2"; 1646 groups = "SALT2"; 1647 }; 1648 1649 pinctrl_salt3_default: salt3_default { 1650 function = "SALT3"; 1651 groups = "SALT3"; 1652 }; 1653 1654 pinctrl_salt4_default: salt4_default { 1655 function = "SALT4"; 1656 groups = "SALT4"; 1657 }; 1658 1659 pinctrl_salt5_default: salt5_default { 1660 function = "SALT5"; 1661 groups = "SALT5"; 1662 }; 1663 1664 pinctrl_salt6_default: salt6_default { 1665 function = "SALT6"; 1666 groups = "SALT6"; 1667 }; 1668 1669 pinctrl_salt7_default: salt7_default { 1670 function = "SALT7"; 1671 groups = "SALT7"; 1672 }; 1673 1674 pinctrl_salt8_default: salt8_default { 1675 function = "SALT8"; 1676 groups = "SALT8"; 1677 }; 1678 1679 pinctrl_salt9_default: salt9_default { 1680 function = "SALT9"; 1681 groups = "SALT9"; 1682 }; 1683 1684 pinctrl_scl1_default: scl1_default { 1685 function = "SCL1"; 1686 groups = "SCL1"; 1687 }; 1688 1689 pinctrl_scl2_default: scl2_default { 1690 function = "SCL2"; 1691 groups = "SCL2"; 1692 }; 1693 1694 pinctrl_sd1_default: sd1_default { 1695 function = "SD1"; 1696 groups = "SD1"; 1697 }; 1698 1699 pinctrl_sd2_default: sd2_default { 1700 function = "SD2"; 1701 groups = "SD2"; 1702 }; 1703 1704 pinctrl_emmc_default: emmc_default { 1705 function = "EMMC"; 1706 groups = "EMMC"; 1707 }; 1708 1709 pinctrl_emmcg8_default: emmcg8_default { 1710 function = "EMMCG8"; 1711 groups = "EMMCG8"; 1712 }; 1713 1714 pinctrl_sda1_default: sda1_default { 1715 function = "SDA1"; 1716 groups = "SDA1"; 1717 }; 1718 1719 pinctrl_sda2_default: sda2_default { 1720 function = "SDA2"; 1721 groups = "SDA2"; 1722 }; 1723 1724 pinctrl_sgps1_default: sgps1_default { 1725 function = "SGPS1"; 1726 groups = "SGPS1"; 1727 }; 1728 1729 pinctrl_sgps2_default: sgps2_default { 1730 function = "SGPS2"; 1731 groups = "SGPS2"; 1732 }; 1733 1734 pinctrl_sioonctrl_default: sioonctrl_default { 1735 function = "SIOONCTRL"; 1736 groups = "SIOONCTRL"; 1737 }; 1738 1739 pinctrl_siopbi_default: siopbi_default { 1740 function = "SIOPBI"; 1741 groups = "SIOPBI"; 1742 }; 1743 1744 pinctrl_siopbo_default: siopbo_default { 1745 function = "SIOPBO"; 1746 groups = "SIOPBO"; 1747 }; 1748 1749 pinctrl_siopwreq_default: siopwreq_default { 1750 function = "SIOPWREQ"; 1751 groups = "SIOPWREQ"; 1752 }; 1753 1754 pinctrl_siopwrgd_default: siopwrgd_default { 1755 function = "SIOPWRGD"; 1756 groups = "SIOPWRGD"; 1757 }; 1758 1759 pinctrl_sios3_default: sios3_default { 1760 function = "SIOS3"; 1761 groups = "SIOS3"; 1762 }; 1763 1764 pinctrl_sios5_default: sios5_default { 1765 function = "SIOS5"; 1766 groups = "SIOS5"; 1767 }; 1768 1769 pinctrl_siosci_default: siosci_default { 1770 function = "SIOSCI"; 1771 groups = "SIOSCI"; 1772 }; 1773 1774 pinctrl_spi1_default: spi1_default { 1775 function = "SPI1"; 1776 groups = "SPI1"; 1777 }; 1778 1779 pinctrl_spi1cs1_default: spi1cs1_default { 1780 function = "SPI1CS1"; 1781 groups = "SPI1CS1"; 1782 }; 1783 1784 pinctrl_spi1debug_default: spi1debug_default { 1785 function = "SPI1DEBUG"; 1786 groups = "SPI1DEBUG"; 1787 }; 1788 1789 pinctrl_spi1passthru_default: spi1passthru_default { 1790 function = "SPI1PASSTHRU"; 1791 groups = "SPI1PASSTHRU"; 1792 }; 1793 1794 pinctrl_spi2ck_default: spi2ck_default { 1795 function = "SPI2CK"; 1796 groups = "SPI2CK"; 1797 }; 1798 1799 pinctrl_spi2cs0_default: spi2cs0_default { 1800 function = "SPI2CS0"; 1801 groups = "SPI2CS0"; 1802 }; 1803 1804 pinctrl_spi2cs1_default: spi2cs1_default { 1805 function = "SPI2CS1"; 1806 groups = "SPI2CS1"; 1807 }; 1808 1809 pinctrl_spi2miso_default: spi2miso_default { 1810 function = "SPI2MISO"; 1811 groups = "SPI2MISO"; 1812 }; 1813 1814 pinctrl_spi2mosi_default: spi2mosi_default { 1815 function = "SPI2MOSI"; 1816 groups = "SPI2MOSI"; 1817 }; 1818 1819 pinctrl_timer3_default: timer3_default { 1820 function = "TIMER3"; 1821 groups = "TIMER3"; 1822 }; 1823 1824 pinctrl_timer4_default: timer4_default { 1825 function = "TIMER4"; 1826 groups = "TIMER4"; 1827 }; 1828 1829 pinctrl_timer5_default: timer5_default { 1830 function = "TIMER5"; 1831 groups = "TIMER5"; 1832 }; 1833 1834 pinctrl_timer6_default: timer6_default { 1835 function = "TIMER6"; 1836 groups = "TIMER6"; 1837 }; 1838 1839 pinctrl_timer7_default: timer7_default { 1840 function = "TIMER7"; 1841 groups = "TIMER7"; 1842 }; 1843 1844 pinctrl_timer8_default: timer8_default { 1845 function = "TIMER8"; 1846 groups = "TIMER8"; 1847 }; 1848 1849 pinctrl_txd1_default: txd1_default { 1850 function = "TXD1"; 1851 groups = "TXD1"; 1852 }; 1853 1854 pinctrl_txd2_default: txd2_default { 1855 function = "TXD2"; 1856 groups = "TXD2"; 1857 }; 1858 1859 pinctrl_txd3_default: txd3_default { 1860 function = "TXD3"; 1861 groups = "TXD3"; 1862 }; 1863 1864 pinctrl_txd4_default: txd4_default { 1865 function = "TXD4"; 1866 groups = "TXD4"; 1867 }; 1868 1869 pinctrl_uart6_default: uart6_default { 1870 function = "UART6"; 1871 groups = "UART6"; 1872 }; 1873 1874 pinctrl_usbcki_default: usbcki_default { 1875 function = "USBCKI"; 1876 groups = "USBCKI"; 1877 }; 1878 1879 pinctrl_usb2ah_default: usb2ah_default { 1880 function = "USB2AH"; 1881 groups = "USB2AH"; 1882 }; 1883 1884 pinctrl_usb11bhid_default: usb11bhid_default { 1885 function = "USB11BHID"; 1886 groups = "USB11BHID"; 1887 }; 1888 1889 pinctrl_usb2bh_default: usb2bh_default { 1890 function = "USB2BH"; 1891 groups = "USB2BH"; 1892 }; 1893 1894 pinctrl_vgabiosrom_default: vgabiosrom_default { 1895 function = "VGABIOSROM"; 1896 groups = "VGABIOSROM"; 1897 }; 1898 1899 pinctrl_vgahs_default: vgahs_default { 1900 function = "VGAHS"; 1901 groups = "VGAHS"; 1902 }; 1903 1904 pinctrl_vgavs_default: vgavs_default { 1905 function = "VGAVS"; 1906 groups = "VGAVS"; 1907 }; 1908 1909 pinctrl_vpi24_default: vpi24_default { 1910 function = "VPI24"; 1911 groups = "VPI24"; 1912 }; 1913 1914 pinctrl_vpo_default: vpo_default { 1915 function = "VPO"; 1916 groups = "VPO"; 1917 }; 1918 1919 pinctrl_wdtrst1_default: wdtrst1_default { 1920 function = "WDTRST1"; 1921 groups = "WDTRST1"; 1922 }; 1923 1924 pinctrl_wdtrst2_default: wdtrst2_default { 1925 function = "WDTRST2"; 1926 groups = "WDTRST2"; 1927 }; 1928 1929 pinctrl_pcie0rc_default: pcie0rc_default { 1930 function = "PCIE0RC"; 1931 groups = "PCIE0RC"; 1932 }; 1933 1934 pinctrl_pcie1rc_default: pcie1rc_default { 1935 function = "PCIE1RC"; 1936 groups = "PCIE1RC"; 1937 }; 1938}; 1939