1// SPDX-License-Identifier: GPL-2.0+ 2#include <dt-bindings/interrupt-controller/arm-gic.h> 3#include <dt-bindings/gpio/aspeed-gpio.h> 4#include "skeleton.dtsi" 5 6/ { 7 model = "Aspeed BMC"; 8 compatible = "aspeed,ast2600"; 9 #address-cells = <1>; 10 #size-cells = <1>; 11 interrupt-parent = <&gic>; 12 13 aliases { 14 i2c0 = &i2c0; 15 i2c1 = &i2c1; 16 i2c2 = &i2c2; 17 i2c3 = &i2c3; 18 i2c4 = &i2c4; 19 i2c5 = &i2c5; 20 i2c6 = &i2c6; 21 i2c7 = &i2c7; 22 i2c8 = &i2c8; 23 i2c9 = &i2c9; 24 i2c10 = &i2c10; 25 i2c11 = &i2c11; 26 i2c12 = &i2c12; 27 i2c13 = &i2c13; 28 i2c14 = &i2c14; 29 i2c15 = &i2c15; 30 serial0 = &uart1; 31 serial1 = &uart2; 32 serial2 = &uart3; 33 serial3 = &uart4; 34 serial4 = &uart5; 35 serial5 = &uart6; 36 serial6 = &uart7; 37 serial7 = &uart8; 38 serial8 = &uart9; 39 serial9 = &uart10; 40 serial10 = &uart11; 41 serial11 = &uart12; 42 serial12 = &uart13; 43 }; 44 45 cpus { 46 #address-cells = <1>; 47 #size-cells = <0>; 48 enable-method = "aspeed,ast2600-smp"; 49 50 cpu@0 { 51 compatible = "arm,cortex-a7"; 52 device_type = "cpu"; 53 reg = <0>; 54 }; 55 56 cpu@1 { 57 compatible = "arm,cortex-a7"; 58 device_type = "cpu"; 59 reg = <1>; 60 }; 61 62 }; 63 64 timer { 65 compatible = "arm,armv7-timer"; 66 interrupt-parent = <&gic>; 67 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 68 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 69 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 70 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 71 }; 72 73 reserved-memory { 74 #address-cells = <1>; 75 #size-cells = <1>; 76 ranges; 77 78 gfx_memory: framebuffer { 79 size = <0x01000000>; 80 alignment = <0x01000000>; 81 compatible = "shared-dma-pool"; 82 reusable; 83 }; 84 85 video_memory: video { 86 size = <0x04000000>; 87 alignment = <0x01000000>; 88 compatible = "shared-dma-pool"; 89 no-map; 90 }; 91 }; 92 93 ahb { 94 compatible = "simple-bus"; 95 #address-cells = <1>; 96 #size-cells = <1>; 97 device_type = "soc"; 98 ranges; 99 100 gic: interrupt-controller@40461000 { 101 compatible = "arm,cortex-a7-gic"; 102 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 103 #interrupt-cells = <3>; 104 interrupt-controller; 105 interrupt-parent = <&gic>; 106 reg = <0x40461000 0x1000>, 107 <0x40462000 0x1000>, 108 <0x40464000 0x2000>, 109 <0x40466000 0x2000>; 110 }; 111 112 ahbc: ahbc@1e600000 { 113 compatible = "aspeed,aspeed-ahbc"; 114 reg = < 0x1e600000 0x100>; 115 }; 116 117 fmc: flash-controller@1e620000 { 118 reg = < 0x1e620000 0xc4 119 0x20000000 0x10000000 >; 120 #address-cells = <1>; 121 #size-cells = <0>; 122 compatible = "aspeed,ast2600-fmc"; 123 status = "disabled"; 124 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 125 clocks = <&scu ASPEED_CLK_AHB>; 126 num-cs = <3>; 127 flash@0 { 128 reg = < 0 >; 129 compatible = "jedec,spi-nor"; 130 status = "disabled"; 131 }; 132 flash@1 { 133 reg = < 1 >; 134 compatible = "jedec,spi-nor"; 135 status = "disabled"; 136 }; 137 flash@2 { 138 reg = < 2 >; 139 compatible = "jedec,spi-nor"; 140 status = "disabled"; 141 }; 142 }; 143 144 spi1: flash-controller@1e630000 { 145 reg = < 0x1e630000 0xc4 146 0x30000000 0x08000000 >; 147 #address-cells = <1>; 148 #size-cells = <0>; 149 compatible = "aspeed,ast2600-spi"; 150 clocks = <&scu ASPEED_CLK_AHB>; 151 num-cs = <2>; 152 status = "disabled"; 153 flash@0 { 154 reg = < 0 >; 155 compatible = "jedec,spi-nor"; 156 status = "disabled"; 157 }; 158 flash@1 { 159 reg = < 1 >; 160 compatible = "jedec,spi-nor"; 161 status = "disabled"; 162 }; 163 }; 164 165 spi2: flash-controller@1e631000 { 166 reg = < 0x1e631000 0xc4 167 0x50000000 0x08000000 >; 168 #address-cells = <1>; 169 #size-cells = <0>; 170 compatible = "aspeed,ast2600-spi"; 171 clocks = <&scu ASPEED_CLK_AHB>; 172 num-cs = <3>; 173 status = "disabled"; 174 flash@0 { 175 reg = < 0 >; 176 compatible = "jedec,spi-nor"; 177 status = "disabled"; 178 }; 179 flash@1 { 180 reg = < 1 >; 181 compatible = "jedec,spi-nor"; 182 status = "disabled"; 183 }; 184 flash@2 { 185 reg = < 2 >; 186 compatible = "jedec,spi-nor"; 187 status = "disabled"; 188 }; 189 }; 190 191 edac: sdram@1e6e0000 { 192 compatible = "aspeed,ast2600-sdram-edac"; 193 reg = <0x1e6e0000 0x174>; 194 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 195 }; 196 197 mdio: ethernet@1e650000 { 198 compatible = "aspeed,aspeed-mdio"; 199 reg = <0x1e650000 0x40>; 200 resets = <&rst ASPEED_RESET_MII>; 201 status = "disabled"; 202 }; 203 204 mac0: ftgmac@1e660000 { 205 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 206 reg = <0x1e660000 0x180>, <0x1e650000 0x4>; 207 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 208 clocks = <&scu ASPEED_CLK_GATE_MAC1CLK>; 209 status = "disabled"; 210 }; 211 212 mac1: ftgmac@1e680000 { 213 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 214 reg = <0x1e680000 0x180>, <0x1e650008 0x4>; 215 #address-cells = <1>; 216 #size-cells = <0>; 217 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 218 clocks = <&scu ASPEED_CLK_GATE_MAC2CLK>; 219 status = "disabled"; 220 }; 221 222 mac2: ftgmac@1e670000 { 223 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 224 reg = <0x1e670000 0x180>, <0x1e650010 0x4>; 225 #address-cells = <1>; 226 #size-cells = <0>; 227 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 228 clocks = <&scu ASPEED_CLK_GATE_MAC3CLK>; 229 status = "disabled"; 230 }; 231 232 mac3: ftgmac@1e690000 { 233 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 234 reg = <0x1e690000 0x180>, <0x1e650018 0x4>; 235 #address-cells = <1>; 236 #size-cells = <0>; 237 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 238 clocks = <&scu ASPEED_CLK_GATE_MAC4CLK>; 239 status = "disabled"; 240 }; 241 242 ehci0: usb@1e6a1000 { 243 compatible = "aspeed,aspeed-ehci", "usb-ehci"; 244 reg = <0x1e6a1000 0x100>; 245 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 246 clocks = <&scu ASPEED_CLK_GATE_USBPORT1CLK>; 247 pinctrl-names = "default"; 248 pinctrl-0 = <&pinctrl_usb2ah_default>; 249 status = "disabled"; 250 }; 251 252 ehci1: usb@1e6a3000 { 253 compatible = "aspeed,aspeed-ehci", "usb-ehci"; 254 reg = <0x1e6a3000 0x100>; 255 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 256 clocks = <&scu ASPEED_CLK_GATE_USBPORT2CLK>; 257 pinctrl-names = "default"; 258 pinctrl-0 = <&pinctrl_usb2bh_default>; 259 status = "disabled"; 260 }; 261 262 apb { 263 compatible = "simple-bus"; 264 #address-cells = <1>; 265 #size-cells = <1>; 266 ranges; 267 268 syscon: syscon@1e6e2000 { 269 compatible = "aspeed,g6-scu", "syscon", "simple-mfd"; 270 reg = <0x1e6e2000 0x1000>; 271 #address-cells = <1>; 272 #size-cells = <1>; 273 #clock-cells = <1>; 274 #reset-cells = <1>; 275 ranges = <0 0x1e6e2000 0x1000>; 276 277 pinctrl: pinctrl { 278 compatible = "aspeed,g6-pinctrl"; 279 aspeed,external-nodes = <&gfx &lhc>; 280 281 }; 282 283 vga_scratch: scratch { 284 compatible = "aspeed,bmc-misc"; 285 }; 286 287 scu_ic0: interrupt-controller@0 { 288 #interrupt-cells = <1>; 289 compatible = "aspeed,ast2600-scu-ic"; 290 reg = <0x560 0x10>; 291 interrupt-parent = <&gic>; 292 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 293 interrupt-controller; 294 }; 295 296 scu_ic1: interrupt-controller@1 { 297 #interrupt-cells = <1>; 298 compatible = "aspeed,ast2600-scu-ic"; 299 reg = <0x570 0x10>; 300 interrupt-parent = <&gic>; 301 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 302 interrupt-controller; 303 }; 304 305 }; 306 307 smp-memram@0 { 308 compatible = "aspeed,ast2600-smpmem", "syscon"; 309 reg = <0x1e6e2180 0x40>; 310 }; 311 312 gfx: display@1e6e6000 { 313 compatible = "aspeed,ast2500-gfx", "syscon"; 314 reg = <0x1e6e6000 0x1000>; 315 reg-io-width = <4>; 316 }; 317 318 pcie_bridge0: pcie@1e6ed000 { 319 compatible = "aspeed,ast2600-pcie"; 320 #address-cells = <3>; 321 #size-cells = <2>; 322 reg = <0x1e6ed000 0x100>; 323 ranges = <0x81000000 0x0 0x0 0x0 0x0 0x10000 /* downstream I/O */ 324 0x82000000 0x0 0x60000000 0x60000000 0x0 0x10000000>; /* non-prefetchable memory */ 325 device_type = "pci"; 326 bus-range = <0x00 0xff>; 327 resets = <&rst ASPEED_RESET_PCIE_DEV_O>; 328 cfg-handle = <&pcie_cfg0>; 329 pinctrl-names = "default"; 330 pinctrl-0 = <&pinctrl_pcie0rc_default>; 331 332 status = "disabled"; 333 }; 334 335 pcie_bridge1: pcie@1e6ed200 { 336 compatible = "aspeed,ast2600-pcie"; 337 #address-cells = <3>; 338 #size-cells = <2>; 339 reg = <0x1e6ed200 0x100>; 340 ranges = <0x81000000 0x0 0x0 0x10000 0x00 0x10000 /* downstream I/O */ 341 0x82000000 0x0 0x70000000 0x70000000 0x0 0x10000000>; /* non-prefetchable memory */ 342 device_type = "pci"; 343 bus-range = <0x00 0xff>; 344 resets = <&rst ASPEED_RESET_PCIE_RC_O>; 345 cfg-handle = <&pcie_cfg1>; 346 pinctrl-names = "default"; 347 pinctrl-0 = <&pinctrl_pcie1rc_default>; 348 349 status = "disabled"; 350 }; 351 352 sdhci: sdhci@1e740000 { 353 #interrupt-cells = <1>; 354 compatible = "aspeed,aspeed-sdhci-irq", "simple-mfd"; 355 reg = <0x1e740000 0x1000>; 356 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 357 interrupt-controller; 358 clocks = <&scu ASPEED_CLK_GATE_SDCLK>, <&scu ASPEED_CLK_GATE_SDEXTCLK>; 359 clock-names = "ctrlclk", "extclk"; 360 #address-cells = <1>; 361 #size-cells = <1>; 362 ranges = <0x0 0x1e740000 0x1000>; 363 364 sdhci_slot0: sdhci_slot0@100 { 365 compatible = "aspeed,sdhci-ast2600"; 366 reg = <0x100 0x100>; 367 interrupts = <0>; 368 interrupt-parent = <&sdhci>; 369 sdhci,auto-cmd12; 370 clocks = <&scu ASPEED_CLK_SDIO>; 371 status = "disabled"; 372 }; 373 374 sdhci_slot1: sdhci_slot1@200 { 375 compatible = "aspeed,sdhci-ast2600"; 376 reg = <0x200 0x100>; 377 interrupts = <1>; 378 interrupt-parent = <&sdhci>; 379 sdhci,auto-cmd12; 380 clocks = <&scu ASPEED_CLK_SDIO>; 381 status = "disabled"; 382 }; 383 }; 384 385 emmc: emmc@1e750000 { 386 #interrupt-cells = <1>; 387 compatible = "aspeed,aspeed-emmc-irq", "simple-mfd"; 388 reg = <0x1e750000 0x1000>; 389 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 390 interrupt-controller; 391 clocks = <&scu ASPEED_CLK_GATE_EMMCCLK>, <&scu ASPEED_CLK_GATE_EMMCEXTCLK>; 392 clock-names = "ctrlclk", "extclk"; 393 #address-cells = <1>; 394 #size-cells = <1>; 395 ranges = <0x0 0x1e750000 0x1000>; 396 397 emmc_slot0: emmc_slot0@100 { 398 compatible = "aspeed,emmc-ast2600"; 399 reg = <0x100 0x100>; 400 interrupts = <0>; 401 interrupt-parent = <&emmc>; 402 clocks = <&scu ASPEED_CLK_EMMC>; 403 status = "disabled"; 404 }; 405 }; 406 407 h2x: h2x@1e770000 { 408 compatible = "aspeed,ast2600-h2x"; 409 reg = <0x1e770000 0x100>; 410 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 411 resets = <&rst ASPEED_RESET_H2X>; 412 #address-cells = <1>; 413 #size-cells = <1>; 414 ranges = <0x0 0x1e770000 0x100>; 415 416 status = "disabled"; 417 418 pcie_cfg0: cfg0@80 { 419 reg = <0x80 0x80>; 420 compatible = "aspeed,ast2600-pcie-cfg"; 421 }; 422 423 pcie_cfg1: cfg1@C0 { 424 compatible = "aspeed,ast2600-pcie-cfg"; 425 reg = <0xC0 0x80>; 426 }; 427 }; 428 429 gpio0: gpio@1e780000 { 430 compatible = "aspeed,ast2600-gpio"; 431 reg = <0x1e780000 0x1000>; 432 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 433 #gpio-cells = <2>; 434 gpio-controller; 435 interrupt-controller; 436 gpio-ranges = <&pinctrl 0 0 220>; 437 ngpios = <208>; 438 }; 439 440 gpio1: gpio@1e780800 { 441 compatible = "aspeed,ast2600-gpio"; 442 reg = <0x1e780800 0x800>; 443 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 444 #gpio-cells = <2>; 445 gpio-controller; 446 interrupt-controller; 447 gpio-ranges = <&pinctrl 0 0 208>; 448 ngpios = <36>; 449 }; 450 451 uart1: serial@1e783000 { 452 compatible = "ns16550a"; 453 reg = <0x1e783000 0x20>; 454 reg-shift = <2>; 455 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 456 clocks = <&scu ASPEED_CLK_GATE_UART1CLK>; 457 clock-frequency = <1846154>; 458 no-loopback-test; 459 status = "disabled"; 460 }; 461 462 uart5: serial@1e784000 { 463 compatible = "ns16550a"; 464 reg = <0x1e784000 0x1000>; 465 reg-shift = <2>; 466 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 467 clocks = <&scu ASPEED_CLK_GATE_UART5CLK>; 468 clock-frequency = <1846154>; 469 no-loopback-test; 470 status = "disabled"; 471 }; 472 473 wdt1: watchdog@1e785000 { 474 compatible = "aspeed,ast2600-wdt"; 475 reg = <0x1e785000 0x40>; 476 }; 477 478 wdt2: watchdog@1e785040 { 479 compatible = "aspeed,ast2600-wdt"; 480 reg = <0x1e785040 0x40>; 481 }; 482 483 wdt3: watchdog@1e785080 { 484 compatible = "aspeed,ast2600-wdt"; 485 reg = <0x1e785080 0x40>; 486 }; 487 488 wdt4: watchdog@1e7850C0 { 489 compatible = "aspeed,ast2600-wdt"; 490 reg = <0x1e7850C0 0x40>; 491 }; 492 493 lpc: lpc@1e789000 { 494 compatible = "aspeed,ast-lpc", "simple-mfd", "syscon"; 495 reg = <0x1e789000 0x200>; 496 497 #address-cells = <1>; 498 #size-cells = <1>; 499 ranges = <0x0 0x1e789000 0x1000>; 500 501 lpc_bmc: lpc-bmc@0 { 502 compatible = "aspeed,ast2600-lpc-bmc", "simple-mfd", "syscon"; 503 reg = <0x0 0x80>; 504 reg-io-width = <4>; 505 #address-cells = <1>; 506 #size-cells = <1>; 507 ranges = <0x0 0x0 0x80>; 508 509 kcs1: kcs1@0 { 510 compatible = "aspeed,ast2600-kcs-bmc"; 511 reg = <0x0 0x80>; 512 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 513 kcs_chan = <1>; 514 kcs_addr = <0xCA0>; 515 status = "disabled"; 516 }; 517 518 kcs2: kcs2@0 { 519 compatible = "aspeed,ast2600-kcs-bmc"; 520 reg = <0x0 0x80>; 521 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 522 kcs_chan = <2>; 523 kcs_addr = <0xCA8>; 524 status = "disabled"; 525 }; 526 527 kcs3: kcs3@0 { 528 compatible = "aspeed,ast2600-kcs-bmc"; 529 reg = <0x0 0x80>; 530 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 531 kcs_chan = <3>; 532 kcs_addr = <0xCA2>; 533 }; 534 535 kcs4: kcs4@0 { 536 compatible = "aspeed,ast2600-kcs-bmc"; 537 reg = <0x0 0x120>; 538 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 539 kcs_chan = <4>; 540 kcs_addr = <0xCA4>; 541 status = "disabled"; 542 }; 543 544 }; 545 546 lpc_host: lpc-host@80 { 547 compatible = "aspeed,ast2600-lpc-host", "simple-mfd", "syscon"; 548 reg = <0x80 0x1e0>; 549 reg-io-width = <4>; 550 551 #address-cells = <1>; 552 #size-cells = <1>; 553 ranges = <0x0 0x80 0x1e0>; 554 555 lpc_ctrl: lpc-ctrl@0 { 556 compatible = "aspeed,ast2600-lpc-ctrl"; 557 reg = <0x0 0x80>; 558 status = "disabled"; 559 }; 560 561 lpc_snoop: lpc-snoop@0 { 562 compatible = "aspeed,ast2600-lpc-snoop"; 563 reg = <0x0 0x80>; 564 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 565 snoop-ports = <0x80>; 566 status = "disabled"; 567 }; 568 569 lhc: lhc@20 { 570 compatible = "aspeed,ast2600-lhc"; 571 reg = <0x20 0x24 0x48 0x8>; 572 }; 573 574 lpc_reset: reset-controller@18 { 575 compatible = "aspeed,ast2600-lpc-reset"; 576 reg = <0x18 0x4>; 577 #reset-cells = <1>; 578 status = "disabled"; 579 }; 580 581 ibt: ibt@c0 { 582 compatible = "aspeed,ast2600-ibt-bmc"; 583 reg = <0xc0 0x18>; 584 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 585 status = "disabled"; 586 }; 587 588 sio_regs: regs { 589 compatible = "aspeed,bmc-misc"; 590 }; 591 592 mbox: mbox@180 { 593 compatible = "aspeed,ast2600-mbox"; 594 reg = <0x180 0x5c>; 595 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 596 #mbox-cells = <1>; 597 status = "disabled"; 598 }; 599 }; 600 }; 601 602 uart2: serial@1e78d000 { 603 compatible = "ns16550a"; 604 reg = <0x1e78d000 0x20>; 605 reg-shift = <2>; 606 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 607 clocks = <&scu ASPEED_CLK_GATE_UART2CLK>; 608 clock-frequency = <1846154>; 609 no-loopback-test; 610 status = "disabled"; 611 }; 612 613 uart3: serial@1e78e000 { 614 compatible = "ns16550a"; 615 reg = <0x1e78e000 0x20>; 616 reg-shift = <2>; 617 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 618 clocks = <&scu ASPEED_CLK_GATE_UART3CLK>; 619 clock-frequency = <1846154>; 620 no-loopback-test; 621 status = "disabled"; 622 }; 623 624 uart4: serial@1e78f000 { 625 compatible = "ns16550a"; 626 reg = <0x1e78f000 0x20>; 627 reg-shift = <2>; 628 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 629 clocks = <&scu ASPEED_CLK_GATE_UART4CLK>; 630 clock-frequency = <1846154>; 631 no-loopback-test; 632 status = "disabled"; 633 }; 634 635 i2c: bus@1e78a000 { 636 compatible = "simple-bus"; 637 #address-cells = <1>; 638 #size-cells = <1>; 639 ranges = <0 0x1e78a000 0x1000>; 640 }; 641 642 fsim0: fsi@1e79b000 { 643 compatible = "aspeed,ast2600-fsi-master", "fsi-master"; 644 reg = <0x1e79b000 0x94>; 645 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 646 pinctrl-names = "default"; 647 pinctrl-0 = <&pinctrl_fsi1_default>; 648 clocks = <&scu ASPEED_CLK_GATE_FSICLK>; 649 status = "disabled"; 650 }; 651 652 fsim1: fsi@1e79b100 { 653 compatible = "aspeed,ast2600-fsi-master", "fsi-master"; 654 reg = <0x1e79b100 0x94>; 655 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 656 pinctrl-names = "default"; 657 pinctrl-0 = <&pinctrl_fsi2_default>; 658 clocks = <&scu ASPEED_CLK_GATE_FSICLK>; 659 status = "disabled"; 660 }; 661 662 uart6: serial@1e790000 { 663 compatible = "ns16550a"; 664 reg = <0x1e790000 0x20>; 665 reg-shift = <2>; 666 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 667 clocks = <&scu ASPEED_CLK_GATE_UART6CLK>; 668 clock-frequency = <1846154>; 669 no-loopback-test; 670 status = "disabled"; 671 }; 672 673 uart7: serial@1e790100 { 674 compatible = "ns16550a"; 675 reg = <0x1e790100 0x20>; 676 reg-shift = <2>; 677 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 678 clocks = <&scu ASPEED_CLK_GATE_UART7CLK>; 679 clock-frequency = <1846154>; 680 no-loopback-test; 681 status = "disabled"; 682 }; 683 684 uart8: serial@1e790200 { 685 compatible = "ns16550a"; 686 reg = <0x1e790200 0x20>; 687 reg-shift = <2>; 688 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 689 clocks = <&scu ASPEED_CLK_GATE_UART8CLK>; 690 clock-frequency = <1846154>; 691 no-loopback-test; 692 status = "disabled"; 693 }; 694 695 uart9: serial@1e790300 { 696 compatible = "ns16550a"; 697 reg = <0x1e790300 0x20>; 698 reg-shift = <2>; 699 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 700 clocks = <&scu ASPEED_CLK_GATE_UART9CLK>; 701 clock-frequency = <1846154>; 702 no-loopback-test; 703 status = "disabled"; 704 }; 705 706 uart10: serial@1e790400 { 707 compatible = "ns16550a"; 708 reg = <0x1e790400 0x20>; 709 reg-shift = <2>; 710 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 711 clocks = <&scu ASPEED_CLK_GATE_UART10CLK>; 712 clock-frequency = <1846154>; 713 no-loopback-test; 714 status = "disabled"; 715 }; 716 717 uart11: serial@1e790500 { 718 compatible = "ns16550a"; 719 reg = <0x1e790400 0x20>; 720 reg-shift = <2>; 721 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 722 clocks = <&scu ASPEED_CLK_GATE_UART11CLK>; 723 clock-frequency = <1846154>; 724 no-loopback-test; 725 status = "disabled"; 726 }; 727 728 uart12: serial@1e790600 { 729 compatible = "ns16550a"; 730 reg = <0x1e790600 0x20>; 731 reg-shift = <2>; 732 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 733 clocks = <&scu ASPEED_CLK_GATE_UART12CLK>; 734 clock-frequency = <1846154>; 735 no-loopback-test; 736 status = "disabled"; 737 }; 738 739 uart13: serial@1e790700 { 740 compatible = "ns16550a"; 741 reg = <0x1e790700 0x20>; 742 reg-shift = <2>; 743 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 744 clocks = <&scu ASPEED_CLK_GATE_UART13CLK>; 745 clock-frequency = <1846154>; 746 no-loopback-test; 747 status = "disabled"; 748 }; 749 750 751 752 }; 753 754 }; 755 756}; 757 758&i2c { 759 i2cglobal: i2cg@00 { 760 compatible = "aspeed,ast2600-i2c-global"; 761 reg = <0x0 0x40>; 762 resets = <&rst ASPEED_RESET_I2C>; 763#if 0 764 new-mode; 765#endif 766 }; 767 768 i2c0: i2c@80 { 769 #address-cells = <1>; 770 #size-cells = <0>; 771 #interrupt-cells = <1>; 772 773 reg = <0x80 0x80 0xC00 0x20>; 774 compatible = "aspeed,ast2600-i2c-bus"; 775 bus-frequency = <100000>; 776 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 777 clocks = <&scu ASPEED_CLK_APB2>; 778 status = "disabled"; 779 }; 780 781 i2c1: i2c@100 { 782 #address-cells = <1>; 783 #size-cells = <0>; 784 #interrupt-cells = <1>; 785 786 reg = <0x100 0x80 0xC20 0x20>; 787 compatible = "aspeed,ast2600-i2c-bus"; 788 bus-frequency = <100000>; 789 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 790 clocks = <&scu ASPEED_CLK_APB2>; 791 status = "disabled"; 792 }; 793 794 i2c2: i2c@180 { 795 #address-cells = <1>; 796 #size-cells = <0>; 797 #interrupt-cells = <1>; 798 799 reg = <0x180 0x80 0xC40 0x20>; 800 compatible = "aspeed,ast2600-i2c-bus"; 801 bus-frequency = <100000>; 802 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 803 clocks = <&scu ASPEED_CLK_APB2>; 804 }; 805 806 i2c3: i2c@200 { 807 #address-cells = <1>; 808 #size-cells = <0>; 809 #interrupt-cells = <1>; 810 811 reg = <0x200 0x40 0xC60 0x20>; 812 compatible = "aspeed,ast2600-i2c-bus"; 813 bus-frequency = <100000>; 814 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 815 clocks = <&scu ASPEED_CLK_APB2>; 816 }; 817 818 i2c4: i2c@280 { 819 #address-cells = <1>; 820 #size-cells = <0>; 821 #interrupt-cells = <1>; 822 823 reg = <0x280 0x80 0xC80 0x20>; 824 compatible = "aspeed,ast2600-i2c-bus"; 825 bus-frequency = <100000>; 826 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 827 clocks = <&scu ASPEED_CLK_APB2>; 828 }; 829 830 i2c5: i2c@300 { 831 #address-cells = <1>; 832 #size-cells = <0>; 833 #interrupt-cells = <1>; 834 835 reg = <0x300 0x40 0xCA0 0x20>; 836 compatible = "aspeed,ast2600-i2c-bus"; 837 bus-frequency = <100000>; 838 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 839 clocks = <&scu ASPEED_CLK_APB2>; 840 }; 841 842 i2c6: i2c@380 { 843 #address-cells = <1>; 844 #size-cells = <0>; 845 #interrupt-cells = <1>; 846 847 reg = <0x380 0x80 0xCC0 0x20>; 848 compatible = "aspeed,ast2600-i2c-bus"; 849 bus-frequency = <100000>; 850 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 851 clocks = <&scu ASPEED_CLK_APB2>; 852 }; 853 854 i2c7: i2c@400 { 855 #address-cells = <1>; 856 #size-cells = <0>; 857 #interrupt-cells = <1>; 858 859 reg = <0x400 0x80 0xCE0 0x20>; 860 compatible = "aspeed,ast2600-i2c-bus"; 861 bus-frequency = <100000>; 862 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 863 clocks = <&scu ASPEED_CLK_APB2>; 864 }; 865 866 i2c8: i2c@480 { 867 #address-cells = <1>; 868 #size-cells = <0>; 869 #interrupt-cells = <1>; 870 871 reg = <0x480 0x80 0xD00 0x20>; 872 compatible = "aspeed,ast2600-i2c-bus"; 873 bus-frequency = <100000>; 874 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 875 clocks = <&scu ASPEED_CLK_APB2>; 876 }; 877 878 i2c9: i2c@500 { 879 #address-cells = <1>; 880 #size-cells = <0>; 881 #interrupt-cells = <1>; 882 883 reg = <0x500 0x80 0xD20 0x20>; 884 compatible = "aspeed,ast2600-i2c-bus"; 885 bus-frequency = <100000>; 886 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 887 clocks = <&scu ASPEED_CLK_APB2>; 888 status = "disabled"; 889 }; 890 891 i2c10: i2c@580 { 892 #address-cells = <1>; 893 #size-cells = <0>; 894 #interrupt-cells = <1>; 895 896 reg = <0x580 0x80 0xD40 0x20>; 897 compatible = "aspeed,ast2600-i2c-bus"; 898 bus-frequency = <100000>; 899 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 900 clocks = <&scu ASPEED_CLK_APB2>; 901 status = "disabled"; 902 }; 903 904 i2c11: i2c@600 { 905 #address-cells = <1>; 906 #size-cells = <0>; 907 #interrupt-cells = <1>; 908 909 reg = <0x600 0x80 0xD60 0x20>; 910 compatible = "aspeed,ast2600-i2c-bus"; 911 bus-frequency = <100000>; 912 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 913 clocks = <&scu ASPEED_CLK_APB2>; 914 status = "disabled"; 915 }; 916 917 i2c12: i2c@680 { 918 #address-cells = <1>; 919 #size-cells = <0>; 920 #interrupt-cells = <1>; 921 922 reg = <0x680 0x80 0xD80 0x20>; 923 compatible = "aspeed,ast2600-i2c-bus"; 924 bus-frequency = <100000>; 925 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 926 clocks = <&scu ASPEED_CLK_APB2>; 927 status = "disabled"; 928 }; 929 930 i2c13: i2c@700 { 931 #address-cells = <1>; 932 #size-cells = <0>; 933 #interrupt-cells = <1>; 934 935 reg = <0x700 0x80 0xDA0 0x20>; 936 compatible = "aspeed,ast2600-i2c-bus"; 937 bus-frequency = <100000>; 938 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 939 clocks = <&scu ASPEED_CLK_APB2>; 940 status = "disabled"; 941 }; 942 943 i2c14: i2c@780 { 944 #address-cells = <1>; 945 #size-cells = <0>; 946 #interrupt-cells = <1>; 947 948 reg = <0x780 0x80 0xDC0 0x20>; 949 compatible = "aspeed,ast2600-i2c-bus"; 950 bus-frequency = <100000>; 951 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 952 clocks = <&scu ASPEED_CLK_APB2>; 953 status = "disabled"; 954 }; 955 956 i2c15: i2c@800 { 957 #address-cells = <1>; 958 #size-cells = <0>; 959 #interrupt-cells = <1>; 960 961 reg = <0x800 0x80 0xDE0 0x20>; 962 compatible = "aspeed,ast2600-i2c-bus"; 963 bus-frequency = <100000>; 964 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 965 clocks = <&scu ASPEED_CLK_APB2>; 966 status = "disabled"; 967 }; 968 969}; 970 971&pinctrl { 972 pinctrl_fmcquad_default: fmcquad_default { 973 function = "FMCQUAD"; 974 groups = "FMCQUAD"; 975 }; 976 977 pinctrl_spi1_default: spi1_default { 978 function = "SPI1"; 979 groups = "SPI1"; 980 }; 981 982 pinctrl_spi1abr_default: spi1abr_default { 983 function = "SPI1ABR"; 984 groups = "SPI1ABR"; 985 }; 986 987 pinctrl_spi1cs1_default: spi1cs1_default { 988 function = "SPI1CS1"; 989 groups = "SPI1CS1"; 990 }; 991 992 pinctrl_spi1wp_default: spi1wp_default { 993 function = "SPI1WP"; 994 groups = "SPI1WP"; 995 }; 996 997 pinctrl_spi1quad_default: spi1quad_default { 998 function = "SPI1QUAD"; 999 groups = "SPI1QUAD"; 1000 }; 1001 1002 pinctrl_spi2_default: spi2_default { 1003 function = "SPI2"; 1004 groups = "SPI2"; 1005 }; 1006 1007 pinctrl_spi2cs1_default: spi2cs1_default { 1008 function = "SPI2CS1"; 1009 groups = "SPI2CS1"; 1010 }; 1011 1012 pinctrl_spi2cs2_default: spi2cs2_default { 1013 function = "SPI2CS2"; 1014 groups = "SPI2CS2"; 1015 }; 1016 1017 pinctrl_spi2quad_default: spi2quad_default { 1018 function = "SPI2QUAD"; 1019 groups = "SPI2QUAD"; 1020 }; 1021 1022 pinctrl_acpi_default: acpi_default { 1023 function = "ACPI"; 1024 groups = "ACPI"; 1025 }; 1026 1027 pinctrl_adc0_default: adc0_default { 1028 function = "ADC0"; 1029 groups = "ADC0"; 1030 }; 1031 1032 pinctrl_adc1_default: adc1_default { 1033 function = "ADC1"; 1034 groups = "ADC1"; 1035 }; 1036 1037 pinctrl_adc10_default: adc10_default { 1038 function = "ADC10"; 1039 groups = "ADC10"; 1040 }; 1041 1042 pinctrl_adc11_default: adc11_default { 1043 function = "ADC11"; 1044 groups = "ADC11"; 1045 }; 1046 1047 pinctrl_adc12_default: adc12_default { 1048 function = "ADC12"; 1049 groups = "ADC12"; 1050 }; 1051 1052 pinctrl_adc13_default: adc13_default { 1053 function = "ADC13"; 1054 groups = "ADC13"; 1055 }; 1056 1057 pinctrl_adc14_default: adc14_default { 1058 function = "ADC14"; 1059 groups = "ADC14"; 1060 }; 1061 1062 pinctrl_adc15_default: adc15_default { 1063 function = "ADC15"; 1064 groups = "ADC15"; 1065 }; 1066 1067 pinctrl_adc2_default: adc2_default { 1068 function = "ADC2"; 1069 groups = "ADC2"; 1070 }; 1071 1072 pinctrl_adc3_default: adc3_default { 1073 function = "ADC3"; 1074 groups = "ADC3"; 1075 }; 1076 1077 pinctrl_adc4_default: adc4_default { 1078 function = "ADC4"; 1079 groups = "ADC4"; 1080 }; 1081 1082 pinctrl_adc5_default: adc5_default { 1083 function = "ADC5"; 1084 groups = "ADC5"; 1085 }; 1086 1087 pinctrl_adc6_default: adc6_default { 1088 function = "ADC6"; 1089 groups = "ADC6"; 1090 }; 1091 1092 pinctrl_adc7_default: adc7_default { 1093 function = "ADC7"; 1094 groups = "ADC7"; 1095 }; 1096 1097 pinctrl_adc8_default: adc8_default { 1098 function = "ADC8"; 1099 groups = "ADC8"; 1100 }; 1101 1102 pinctrl_adc9_default: adc9_default { 1103 function = "ADC9"; 1104 groups = "ADC9"; 1105 }; 1106 1107 pinctrl_bmcint_default: bmcint_default { 1108 function = "BMCINT"; 1109 groups = "BMCINT"; 1110 }; 1111 1112 pinctrl_ddcclk_default: ddcclk_default { 1113 function = "DDCCLK"; 1114 groups = "DDCCLK"; 1115 }; 1116 1117 pinctrl_ddcdat_default: ddcdat_default { 1118 function = "DDCDAT"; 1119 groups = "DDCDAT"; 1120 }; 1121 1122 pinctrl_espi_default: espi_default { 1123 function = "ESPI"; 1124 groups = "ESPI"; 1125 }; 1126 1127 pinctrl_fsi1_default: fsi1_default { 1128 function = "FSI1"; 1129 groups = "FSI1"; 1130 }; 1131 1132 pinctrl_fsi2_default: fsi2_default { 1133 function = "FSI2"; 1134 groups = "FSI2"; 1135 }; 1136 1137 pinctrl_fwspics1_default: fwspics1_default { 1138 function = "FWSPICS1"; 1139 groups = "FWSPICS1"; 1140 }; 1141 1142 pinctrl_fwspics2_default: fwspics2_default { 1143 function = "FWSPICS2"; 1144 groups = "FWSPICS2"; 1145 }; 1146 1147 pinctrl_gpid0_default: gpid0_default { 1148 function = "GPID0"; 1149 groups = "GPID0"; 1150 }; 1151 1152 pinctrl_gpid2_default: gpid2_default { 1153 function = "GPID2"; 1154 groups = "GPID2"; 1155 }; 1156 1157 pinctrl_gpid4_default: gpid4_default { 1158 function = "GPID4"; 1159 groups = "GPID4"; 1160 }; 1161 1162 pinctrl_gpid6_default: gpid6_default { 1163 function = "GPID6"; 1164 groups = "GPID6"; 1165 }; 1166 1167 pinctrl_gpie0_default: gpie0_default { 1168 function = "GPIE0"; 1169 groups = "GPIE0"; 1170 }; 1171 1172 pinctrl_gpie2_default: gpie2_default { 1173 function = "GPIE2"; 1174 groups = "GPIE2"; 1175 }; 1176 1177 pinctrl_gpie4_default: gpie4_default { 1178 function = "GPIE4"; 1179 groups = "GPIE4"; 1180 }; 1181 1182 pinctrl_gpie6_default: gpie6_default { 1183 function = "GPIE6"; 1184 groups = "GPIE6"; 1185 }; 1186 1187 pinctrl_i2c1_default: i2c1_default { 1188 function = "I2C1"; 1189 groups = "I2C1"; 1190 }; 1191 pinctrl_i2c2_default: i2c2_default { 1192 function = "I2C2"; 1193 groups = "I2C2"; 1194 }; 1195 1196 pinctrl_i2c3_default: i2c3_default { 1197 function = "I2C3"; 1198 groups = "I2C3"; 1199 }; 1200 1201 pinctrl_i2c4_default: i2c4_default { 1202 function = "I2C4"; 1203 groups = "I2C4"; 1204 }; 1205 1206 pinctrl_i2c5_default: i2c5_default { 1207 function = "I2C5"; 1208 groups = "I2C5"; 1209 }; 1210 1211 pinctrl_i2c6_default: i2c6_default { 1212 function = "I2C6"; 1213 groups = "I2C6"; 1214 }; 1215 1216 pinctrl_i2c7_default: i2c7_default { 1217 function = "I2C7"; 1218 groups = "I2C7"; 1219 }; 1220 1221 pinctrl_i2c8_default: i2c8_default { 1222 function = "I2C8"; 1223 groups = "I2C8"; 1224 }; 1225 1226 pinctrl_i2c9_default: i2c9_default { 1227 function = "I2C9"; 1228 groups = "I2C9"; 1229 }; 1230 1231 pinctrl_i2c10_default: i2c10_default { 1232 function = "I2C10"; 1233 groups = "I2C10"; 1234 }; 1235 1236 pinctrl_i2c11_default: i2c11_default { 1237 function = "I2C11"; 1238 groups = "I2C11"; 1239 }; 1240 1241 pinctrl_i2c12_default: i2c12_default { 1242 function = "I2C12"; 1243 groups = "I2C12"; 1244 }; 1245 1246 pinctrl_i2c13_default: i2c13_default { 1247 function = "I2C13"; 1248 groups = "I2C13"; 1249 }; 1250 1251 pinctrl_i2c14_default: i2c14_default { 1252 function = "I2C14"; 1253 groups = "I2C14"; 1254 }; 1255 1256 pinctrl_i2c15_default: i2c15_default { 1257 function = "I2C15"; 1258 groups = "I2C15"; 1259 }; 1260 1261 pinctrl_i2c16_default: i2c16_default { 1262 function = "I2C16"; 1263 groups = "I2C16"; 1264 }; 1265 1266 pinctrl_lad0_default: lad0_default { 1267 function = "LAD0"; 1268 groups = "LAD0"; 1269 }; 1270 1271 pinctrl_lad1_default: lad1_default { 1272 function = "LAD1"; 1273 groups = "LAD1"; 1274 }; 1275 1276 pinctrl_lad2_default: lad2_default { 1277 function = "LAD2"; 1278 groups = "LAD2"; 1279 }; 1280 1281 pinctrl_lad3_default: lad3_default { 1282 function = "LAD3"; 1283 groups = "LAD3"; 1284 }; 1285 1286 pinctrl_lclk_default: lclk_default { 1287 function = "LCLK"; 1288 groups = "LCLK"; 1289 }; 1290 1291 pinctrl_lframe_default: lframe_default { 1292 function = "LFRAME"; 1293 groups = "LFRAME"; 1294 }; 1295 1296 pinctrl_lpchc_default: lpchc_default { 1297 function = "LPCHC"; 1298 groups = "LPCHC"; 1299 }; 1300 1301 pinctrl_lpcpd_default: lpcpd_default { 1302 function = "LPCPD"; 1303 groups = "LPCPD"; 1304 }; 1305 1306 pinctrl_lpcplus_default: lpcplus_default { 1307 function = "LPCPLUS"; 1308 groups = "LPCPLUS"; 1309 }; 1310 1311 pinctrl_lpcpme_default: lpcpme_default { 1312 function = "LPCPME"; 1313 groups = "LPCPME"; 1314 }; 1315 1316 pinctrl_lpcrst_default: lpcrst_default { 1317 function = "LPCRST"; 1318 groups = "LPCRST"; 1319 }; 1320 1321 pinctrl_lpcsmi_default: lpcsmi_default { 1322 function = "LPCSMI"; 1323 groups = "LPCSMI"; 1324 }; 1325 1326 pinctrl_lsirq_default: lsirq_default { 1327 function = "LSIRQ"; 1328 groups = "LSIRQ"; 1329 }; 1330 1331 pinctrl_mac1link_default: mac1link_default { 1332 function = "MAC1LINK"; 1333 groups = "MAC1LINK"; 1334 }; 1335 1336 pinctrl_mac2link_default: mac2link_default { 1337 function = "MAC2LINK"; 1338 groups = "MAC2LINK"; 1339 }; 1340 1341 pinctrl_mac3link_default: mac3link_default { 1342 function = "MAC3LINK"; 1343 groups = "MAC3LINK"; 1344 }; 1345 1346 pinctrl_mac4link_default: mac4link_default { 1347 function = "MAC4LINK"; 1348 groups = "MAC4LINK"; 1349 }; 1350 1351 pinctrl_mdio1_default: mdio1_default { 1352 function = "MDIO1"; 1353 groups = "MDIO1"; 1354 }; 1355 1356 pinctrl_mdio2_default: mdio2_default { 1357 function = "MDIO2"; 1358 groups = "MDIO2"; 1359 }; 1360 1361 pinctrl_mdio3_default: mdio3_default { 1362 function = "MDIO3"; 1363 groups = "MDIO3"; 1364 }; 1365 1366 pinctrl_mdio4_default: mdio4_default { 1367 function = "MDIO4"; 1368 groups = "MDIO4"; 1369 }; 1370 1371 pinctrl_rmii1_default: rmii1_default { 1372 function = "RMII1"; 1373 groups = "RMII1"; 1374 }; 1375 1376 pinctrl_rmii2_default: rmii2_default { 1377 function = "RMII2"; 1378 groups = "RMII2"; 1379 }; 1380 1381 pinctrl_rmii3_default: rmii3_default { 1382 function = "RMII3"; 1383 groups = "RMII3"; 1384 }; 1385 1386 pinctrl_rmii4_default: rmii4_default { 1387 function = "RMII4"; 1388 groups = "RMII4"; 1389 }; 1390 1391 pinctrl_rmii1rclk_default: rmii1rclk_default { 1392 function = "RMII1RCLK"; 1393 groups = "RMII1RCLK"; 1394 }; 1395 1396 pinctrl_rmii2rclk_default: rmii2rclk_default { 1397 function = "RMII2RCLK"; 1398 groups = "RMII2RCLK"; 1399 }; 1400 1401 pinctrl_rmii3rclk_default: rmii3rclk_default { 1402 function = "RMII3RCLK"; 1403 groups = "RMII3RCLK"; 1404 }; 1405 1406 pinctrl_rmii4rclk_default: rmii4rclk_default { 1407 function = "RMII4RCLK"; 1408 groups = "RMII4RCLK"; 1409 }; 1410 1411 pinctrl_ncts1_default: ncts1_default { 1412 function = "NCTS1"; 1413 groups = "NCTS1"; 1414 }; 1415 1416 pinctrl_ncts2_default: ncts2_default { 1417 function = "NCTS2"; 1418 groups = "NCTS2"; 1419 }; 1420 1421 pinctrl_ncts3_default: ncts3_default { 1422 function = "NCTS3"; 1423 groups = "NCTS3"; 1424 }; 1425 1426 pinctrl_ncts4_default: ncts4_default { 1427 function = "NCTS4"; 1428 groups = "NCTS4"; 1429 }; 1430 1431 pinctrl_ndcd1_default: ndcd1_default { 1432 function = "NDCD1"; 1433 groups = "NDCD1"; 1434 }; 1435 1436 pinctrl_ndcd2_default: ndcd2_default { 1437 function = "NDCD2"; 1438 groups = "NDCD2"; 1439 }; 1440 1441 pinctrl_ndcd3_default: ndcd3_default { 1442 function = "NDCD3"; 1443 groups = "NDCD3"; 1444 }; 1445 1446 pinctrl_ndcd4_default: ndcd4_default { 1447 function = "NDCD4"; 1448 groups = "NDCD4"; 1449 }; 1450 1451 pinctrl_ndsr1_default: ndsr1_default { 1452 function = "NDSR1"; 1453 groups = "NDSR1"; 1454 }; 1455 1456 pinctrl_ndsr2_default: ndsr2_default { 1457 function = "NDSR2"; 1458 groups = "NDSR2"; 1459 }; 1460 1461 pinctrl_ndsr3_default: ndsr3_default { 1462 function = "NDSR3"; 1463 groups = "NDSR3"; 1464 }; 1465 1466 pinctrl_ndsr4_default: ndsr4_default { 1467 function = "NDSR4"; 1468 groups = "NDSR4"; 1469 }; 1470 1471 pinctrl_ndtr1_default: ndtr1_default { 1472 function = "NDTR1"; 1473 groups = "NDTR1"; 1474 }; 1475 1476 pinctrl_ndtr2_default: ndtr2_default { 1477 function = "NDTR2"; 1478 groups = "NDTR2"; 1479 }; 1480 1481 pinctrl_ndtr3_default: ndtr3_default { 1482 function = "NDTR3"; 1483 groups = "NDTR3"; 1484 }; 1485 1486 pinctrl_ndtr4_default: ndtr4_default { 1487 function = "NDTR4"; 1488 groups = "NDTR4"; 1489 }; 1490 1491 pinctrl_nri1_default: nri1_default { 1492 function = "NRI1"; 1493 groups = "NRI1"; 1494 }; 1495 1496 pinctrl_nri2_default: nri2_default { 1497 function = "NRI2"; 1498 groups = "NRI2"; 1499 }; 1500 1501 pinctrl_nri3_default: nri3_default { 1502 function = "NRI3"; 1503 groups = "NRI3"; 1504 }; 1505 1506 pinctrl_nri4_default: nri4_default { 1507 function = "NRI4"; 1508 groups = "NRI4"; 1509 }; 1510 1511 pinctrl_nrts1_default: nrts1_default { 1512 function = "NRTS1"; 1513 groups = "NRTS1"; 1514 }; 1515 1516 pinctrl_nrts2_default: nrts2_default { 1517 function = "NRTS2"; 1518 groups = "NRTS2"; 1519 }; 1520 1521 pinctrl_nrts3_default: nrts3_default { 1522 function = "NRTS3"; 1523 groups = "NRTS3"; 1524 }; 1525 1526 pinctrl_nrts4_default: nrts4_default { 1527 function = "NRTS4"; 1528 groups = "NRTS4"; 1529 }; 1530 1531 pinctrl_oscclk_default: oscclk_default { 1532 function = "OSCCLK"; 1533 groups = "OSCCLK"; 1534 }; 1535 1536 pinctrl_pewake_default: pewake_default { 1537 function = "PEWAKE"; 1538 groups = "PEWAKE"; 1539 }; 1540 1541 pinctrl_pnor_default: pnor_default { 1542 function = "PNOR"; 1543 groups = "PNOR"; 1544 }; 1545 1546 pinctrl_pwm0_default: pwm0_default { 1547 function = "PWM0"; 1548 groups = "PWM0"; 1549 }; 1550 1551 pinctrl_pwm1_default: pwm1_default { 1552 function = "PWM1"; 1553 groups = "PWM1"; 1554 }; 1555 1556 pinctrl_pwm2_default: pwm2_default { 1557 function = "PWM2"; 1558 groups = "PWM2"; 1559 }; 1560 1561 pinctrl_pwm3_default: pwm3_default { 1562 function = "PWM3"; 1563 groups = "PWM3"; 1564 }; 1565 1566 pinctrl_pwm4_default: pwm4_default { 1567 function = "PWM4"; 1568 groups = "PWM4"; 1569 }; 1570 1571 pinctrl_pwm5_default: pwm5_default { 1572 function = "PWM5"; 1573 groups = "PWM5"; 1574 }; 1575 1576 pinctrl_pwm6_default: pwm6_default { 1577 function = "PWM6"; 1578 groups = "PWM6"; 1579 }; 1580 1581 pinctrl_pwm7_default: pwm7_default { 1582 function = "PWM7"; 1583 groups = "PWM7"; 1584 }; 1585 1586 pinctrl_rgmii1_default: rgmii1_default { 1587 function = "RGMII1"; 1588 groups = "RGMII1"; 1589 }; 1590 1591 pinctrl_rgmii2_default: rgmii2_default { 1592 function = "RGMII2"; 1593 groups = "RGMII2"; 1594 }; 1595 1596 pinctrl_rgmii3_default: rgmii3_default { 1597 function = "RGMII3"; 1598 groups = "RGMII3"; 1599 }; 1600 1601 pinctrl_rgmii4_default: rgmii4_default { 1602 function = "RGMII4"; 1603 groups = "RGMII4"; 1604 }; 1605 1606 pinctrl_rmii1_default: rmii1_default { 1607 function = "RMII1"; 1608 groups = "RMII1"; 1609 }; 1610 1611 pinctrl_rmii2_default: rmii2_default { 1612 function = "RMII2"; 1613 groups = "RMII2"; 1614 }; 1615 1616 pinctrl_rxd1_default: rxd1_default { 1617 function = "RXD1"; 1618 groups = "RXD1"; 1619 }; 1620 1621 pinctrl_rxd2_default: rxd2_default { 1622 function = "RXD2"; 1623 groups = "RXD2"; 1624 }; 1625 1626 pinctrl_rxd3_default: rxd3_default { 1627 function = "RXD3"; 1628 groups = "RXD3"; 1629 }; 1630 1631 pinctrl_rxd4_default: rxd4_default { 1632 function = "RXD4"; 1633 groups = "RXD4"; 1634 }; 1635 1636 pinctrl_salt1_default: salt1_default { 1637 function = "SALT1"; 1638 groups = "SALT1"; 1639 }; 1640 1641 pinctrl_salt10_default: salt10_default { 1642 function = "SALT10"; 1643 groups = "SALT10"; 1644 }; 1645 1646 pinctrl_salt11_default: salt11_default { 1647 function = "SALT11"; 1648 groups = "SALT11"; 1649 }; 1650 1651 pinctrl_salt12_default: salt12_default { 1652 function = "SALT12"; 1653 groups = "SALT12"; 1654 }; 1655 1656 pinctrl_salt13_default: salt13_default { 1657 function = "SALT13"; 1658 groups = "SALT13"; 1659 }; 1660 1661 pinctrl_salt14_default: salt14_default { 1662 function = "SALT14"; 1663 groups = "SALT14"; 1664 }; 1665 1666 pinctrl_salt2_default: salt2_default { 1667 function = "SALT2"; 1668 groups = "SALT2"; 1669 }; 1670 1671 pinctrl_salt3_default: salt3_default { 1672 function = "SALT3"; 1673 groups = "SALT3"; 1674 }; 1675 1676 pinctrl_salt4_default: salt4_default { 1677 function = "SALT4"; 1678 groups = "SALT4"; 1679 }; 1680 1681 pinctrl_salt5_default: salt5_default { 1682 function = "SALT5"; 1683 groups = "SALT5"; 1684 }; 1685 1686 pinctrl_salt6_default: salt6_default { 1687 function = "SALT6"; 1688 groups = "SALT6"; 1689 }; 1690 1691 pinctrl_salt7_default: salt7_default { 1692 function = "SALT7"; 1693 groups = "SALT7"; 1694 }; 1695 1696 pinctrl_salt8_default: salt8_default { 1697 function = "SALT8"; 1698 groups = "SALT8"; 1699 }; 1700 1701 pinctrl_salt9_default: salt9_default { 1702 function = "SALT9"; 1703 groups = "SALT9"; 1704 }; 1705 1706 pinctrl_scl1_default: scl1_default { 1707 function = "SCL1"; 1708 groups = "SCL1"; 1709 }; 1710 1711 pinctrl_scl2_default: scl2_default { 1712 function = "SCL2"; 1713 groups = "SCL2"; 1714 }; 1715 1716 pinctrl_sd1_default: sd1_default { 1717 function = "SD1"; 1718 groups = "SD1"; 1719 }; 1720 1721 pinctrl_sd2_default: sd2_default { 1722 function = "SD2"; 1723 groups = "SD2"; 1724 }; 1725 1726 pinctrl_emmc_default: emmc_default { 1727 function = "EMMC"; 1728 groups = "EMMC"; 1729 }; 1730 1731 pinctrl_emmcg8_default: emmcg8_default { 1732 function = "EMMCG8"; 1733 groups = "EMMCG8"; 1734 }; 1735 1736 pinctrl_sda1_default: sda1_default { 1737 function = "SDA1"; 1738 groups = "SDA1"; 1739 }; 1740 1741 pinctrl_sda2_default: sda2_default { 1742 function = "SDA2"; 1743 groups = "SDA2"; 1744 }; 1745 1746 pinctrl_sgps1_default: sgps1_default { 1747 function = "SGPS1"; 1748 groups = "SGPS1"; 1749 }; 1750 1751 pinctrl_sgps2_default: sgps2_default { 1752 function = "SGPS2"; 1753 groups = "SGPS2"; 1754 }; 1755 1756 pinctrl_sioonctrl_default: sioonctrl_default { 1757 function = "SIOONCTRL"; 1758 groups = "SIOONCTRL"; 1759 }; 1760 1761 pinctrl_siopbi_default: siopbi_default { 1762 function = "SIOPBI"; 1763 groups = "SIOPBI"; 1764 }; 1765 1766 pinctrl_siopbo_default: siopbo_default { 1767 function = "SIOPBO"; 1768 groups = "SIOPBO"; 1769 }; 1770 1771 pinctrl_siopwreq_default: siopwreq_default { 1772 function = "SIOPWREQ"; 1773 groups = "SIOPWREQ"; 1774 }; 1775 1776 pinctrl_siopwrgd_default: siopwrgd_default { 1777 function = "SIOPWRGD"; 1778 groups = "SIOPWRGD"; 1779 }; 1780 1781 pinctrl_sios3_default: sios3_default { 1782 function = "SIOS3"; 1783 groups = "SIOS3"; 1784 }; 1785 1786 pinctrl_sios5_default: sios5_default { 1787 function = "SIOS5"; 1788 groups = "SIOS5"; 1789 }; 1790 1791 pinctrl_siosci_default: siosci_default { 1792 function = "SIOSCI"; 1793 groups = "SIOSCI"; 1794 }; 1795 1796 pinctrl_spi1_default: spi1_default { 1797 function = "SPI1"; 1798 groups = "SPI1"; 1799 }; 1800 1801 pinctrl_spi1cs1_default: spi1cs1_default { 1802 function = "SPI1CS1"; 1803 groups = "SPI1CS1"; 1804 }; 1805 1806 pinctrl_spi1debug_default: spi1debug_default { 1807 function = "SPI1DEBUG"; 1808 groups = "SPI1DEBUG"; 1809 }; 1810 1811 pinctrl_spi1passthru_default: spi1passthru_default { 1812 function = "SPI1PASSTHRU"; 1813 groups = "SPI1PASSTHRU"; 1814 }; 1815 1816 pinctrl_spi2ck_default: spi2ck_default { 1817 function = "SPI2CK"; 1818 groups = "SPI2CK"; 1819 }; 1820 1821 pinctrl_spi2cs0_default: spi2cs0_default { 1822 function = "SPI2CS0"; 1823 groups = "SPI2CS0"; 1824 }; 1825 1826 pinctrl_spi2cs1_default: spi2cs1_default { 1827 function = "SPI2CS1"; 1828 groups = "SPI2CS1"; 1829 }; 1830 1831 pinctrl_spi2miso_default: spi2miso_default { 1832 function = "SPI2MISO"; 1833 groups = "SPI2MISO"; 1834 }; 1835 1836 pinctrl_spi2mosi_default: spi2mosi_default { 1837 function = "SPI2MOSI"; 1838 groups = "SPI2MOSI"; 1839 }; 1840 1841 pinctrl_timer3_default: timer3_default { 1842 function = "TIMER3"; 1843 groups = "TIMER3"; 1844 }; 1845 1846 pinctrl_timer4_default: timer4_default { 1847 function = "TIMER4"; 1848 groups = "TIMER4"; 1849 }; 1850 1851 pinctrl_timer5_default: timer5_default { 1852 function = "TIMER5"; 1853 groups = "TIMER5"; 1854 }; 1855 1856 pinctrl_timer6_default: timer6_default { 1857 function = "TIMER6"; 1858 groups = "TIMER6"; 1859 }; 1860 1861 pinctrl_timer7_default: timer7_default { 1862 function = "TIMER7"; 1863 groups = "TIMER7"; 1864 }; 1865 1866 pinctrl_timer8_default: timer8_default { 1867 function = "TIMER8"; 1868 groups = "TIMER8"; 1869 }; 1870 1871 pinctrl_txd1_default: txd1_default { 1872 function = "TXD1"; 1873 groups = "TXD1"; 1874 }; 1875 1876 pinctrl_txd2_default: txd2_default { 1877 function = "TXD2"; 1878 groups = "TXD2"; 1879 }; 1880 1881 pinctrl_txd3_default: txd3_default { 1882 function = "TXD3"; 1883 groups = "TXD3"; 1884 }; 1885 1886 pinctrl_txd4_default: txd4_default { 1887 function = "TXD4"; 1888 groups = "TXD4"; 1889 }; 1890 1891 pinctrl_uart6_default: uart6_default { 1892 function = "UART6"; 1893 groups = "UART6"; 1894 }; 1895 1896 pinctrl_usbcki_default: usbcki_default { 1897 function = "USBCKI"; 1898 groups = "USBCKI"; 1899 }; 1900 1901 pinctrl_usb2ah_default: usb2ah_default { 1902 function = "USB2AH"; 1903 groups = "USB2AH"; 1904 }; 1905 1906 pinctrl_usb11bhid_default: usb11bhid_default { 1907 function = "USB11BHID"; 1908 groups = "USB11BHID"; 1909 }; 1910 1911 pinctrl_usb2bh_default: usb2bh_default { 1912 function = "USB2BH"; 1913 groups = "USB2BH"; 1914 }; 1915 1916 pinctrl_vgabiosrom_default: vgabiosrom_default { 1917 function = "VGABIOSROM"; 1918 groups = "VGABIOSROM"; 1919 }; 1920 1921 pinctrl_vgahs_default: vgahs_default { 1922 function = "VGAHS"; 1923 groups = "VGAHS"; 1924 }; 1925 1926 pinctrl_vgavs_default: vgavs_default { 1927 function = "VGAVS"; 1928 groups = "VGAVS"; 1929 }; 1930 1931 pinctrl_vpi24_default: vpi24_default { 1932 function = "VPI24"; 1933 groups = "VPI24"; 1934 }; 1935 1936 pinctrl_vpo_default: vpo_default { 1937 function = "VPO"; 1938 groups = "VPO"; 1939 }; 1940 1941 pinctrl_wdtrst1_default: wdtrst1_default { 1942 function = "WDTRST1"; 1943 groups = "WDTRST1"; 1944 }; 1945 1946 pinctrl_wdtrst2_default: wdtrst2_default { 1947 function = "WDTRST2"; 1948 groups = "WDTRST2"; 1949 }; 1950 1951 pinctrl_pcie0rc_default: pcie0rc_default { 1952 function = "PCIE0RC"; 1953 groups = "PCIE0RC"; 1954 }; 1955 1956 pinctrl_pcie1rc_default: pcie1rc_default { 1957 function = "PCIE1RC"; 1958 groups = "PCIE1RC"; 1959 }; 1960}; 1961