1// SPDX-License-Identifier: GPL-2.0+ 2#include <dt-bindings/interrupt-controller/arm-gic.h> 3#include <dt-bindings/gpio/aspeed-gpio.h> 4#include "skeleton.dtsi" 5 6/ { 7 model = "Aspeed BMC"; 8 compatible = "aspeed,ast2600"; 9 #address-cells = <1>; 10 #size-cells = <1>; 11 interrupt-parent = <&gic>; 12 13 aliases { 14 i2c0 = &i2c0; 15 i2c1 = &i2c1; 16 i2c2 = &i2c2; 17 i2c3 = &i2c3; 18 i2c4 = &i2c4; 19 i2c5 = &i2c5; 20 i2c6 = &i2c6; 21 i2c7 = &i2c7; 22 i2c8 = &i2c8; 23 i2c9 = &i2c9; 24 i2c10 = &i2c10; 25 i2c11 = &i2c11; 26 i2c12 = &i2c12; 27 i2c13 = &i2c13; 28 i2c14 = &i2c14; 29 i2c15 = &i2c15; 30 serial0 = &uart1; 31 serial1 = &uart2; 32 serial2 = &uart3; 33 serial3 = &uart4; 34 serial4 = &uart5; 35 serial5 = &uart6; 36 serial6 = &uart7; 37 serial7 = &uart8; 38 serial8 = &uart9; 39 serial9 = &uart10; 40 serial10 = &uart11; 41 serial11 = &uart12; 42 serial12 = &uart13; 43 }; 44 45 cpus { 46 #address-cells = <1>; 47 #size-cells = <0>; 48 enable-method = "aspeed,ast2600-smp"; 49 50 cpu@0 { 51 compatible = "arm,cortex-a7"; 52 device_type = "cpu"; 53 reg = <0>; 54 }; 55 56 cpu@1 { 57 compatible = "arm,cortex-a7"; 58 device_type = "cpu"; 59 reg = <1>; 60 }; 61 62 }; 63 64 timer { 65 compatible = "arm,armv7-timer"; 66 interrupt-parent = <&gic>; 67 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 68 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 69 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 70 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 71 }; 72 73 reserved-memory { 74 #address-cells = <1>; 75 #size-cells = <1>; 76 ranges; 77 78 gfx_memory: framebuffer { 79 size = <0x01000000>; 80 alignment = <0x01000000>; 81 compatible = "shared-dma-pool"; 82 reusable; 83 }; 84 85 video_memory: video { 86 size = <0x04000000>; 87 alignment = <0x01000000>; 88 compatible = "shared-dma-pool"; 89 no-map; 90 }; 91 }; 92 93 ahb { 94 compatible = "simple-bus"; 95 #address-cells = <1>; 96 #size-cells = <1>; 97 device_type = "soc"; 98 ranges; 99 100 gic: interrupt-controller@40461000 { 101 compatible = "arm,cortex-a7-gic"; 102 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 103 #interrupt-cells = <3>; 104 interrupt-controller; 105 interrupt-parent = <&gic>; 106 reg = <0x40461000 0x1000>, 107 <0x40462000 0x1000>, 108 <0x40464000 0x2000>, 109 <0x40466000 0x2000>; 110 }; 111 112 ahbc: ahbc@1e600000 { 113 compatible = "aspeed,aspeed-ahbc"; 114 reg = < 0x1e600000 0x100>; 115 }; 116 117 fmc: flash-controller@1e620000 { 118 reg = < 0x1e620000 0xc4 119 0x20000000 0x10000000 >; 120 #address-cells = <1>; 121 #size-cells = <0>; 122 compatible = "aspeed,ast2600-fmc"; 123 status = "disabled"; 124 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 125 clocks = <&scu ASPEED_CLK_AHB>; 126 num-cs = <3>; 127 flash@0 { 128 reg = < 0 >; 129 compatible = "jedec,spi-nor"; 130 status = "disabled"; 131 }; 132 flash@1 { 133 reg = < 1 >; 134 compatible = "jedec,spi-nor"; 135 status = "disabled"; 136 }; 137 flash@2 { 138 reg = < 2 >; 139 compatible = "jedec,spi-nor"; 140 status = "disabled"; 141 }; 142 }; 143 144 spi1: flash-controller@1e630000 { 145 reg = < 0x1e630000 0xc4 146 0x30000000 0x08000000 >; 147 #address-cells = <1>; 148 #size-cells = <0>; 149 compatible = "aspeed,ast2600-spi"; 150 clocks = <&scu ASPEED_CLK_AHB>; 151 num-cs = <2>; 152 status = "disabled"; 153 flash@0 { 154 reg = < 0 >; 155 compatible = "jedec,spi-nor"; 156 status = "disabled"; 157 }; 158 flash@1 { 159 reg = < 1 >; 160 compatible = "jedec,spi-nor"; 161 status = "disabled"; 162 }; 163 }; 164 165 spi2: flash-controller@1e631000 { 166 reg = < 0x1e631000 0xc4 167 0x50000000 0x08000000 >; 168 #address-cells = <1>; 169 #size-cells = <0>; 170 compatible = "aspeed,ast2600-spi"; 171 clocks = <&scu ASPEED_CLK_AHB>; 172 num-cs = <3>; 173 status = "disabled"; 174 flash@0 { 175 reg = < 0 >; 176 compatible = "jedec,spi-nor"; 177 status = "disabled"; 178 }; 179 flash@1 { 180 reg = < 1 >; 181 compatible = "jedec,spi-nor"; 182 status = "disabled"; 183 }; 184 flash@2 { 185 reg = < 2 >; 186 compatible = "jedec,spi-nor"; 187 status = "disabled"; 188 }; 189 }; 190 191 edac: sdram@1e6e0000 { 192 compatible = "aspeed,ast2600-sdram-edac"; 193 reg = <0x1e6e0000 0x174>; 194 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 195 }; 196 197 mdio: ethernet@1e650000 { 198 compatible = "aspeed,aspeed-mdio"; 199 reg = <0x1e650000 0x40>; 200 resets = <&rst ASPEED_RESET_MII>; 201 status = "disabled"; 202 }; 203 204 mac0: ftgmac@1e660000 { 205 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 206 reg = <0x1e660000 0x180>, <0x1e650000 0x4>; 207 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 208 clocks = <&scu ASPEED_CLK_GATE_MAC1CLK>; 209 status = "disabled"; 210 }; 211 212 mac1: ftgmac@1e680000 { 213 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 214 reg = <0x1e680000 0x180>, <0x1e650008 0x4>; 215 #address-cells = <1>; 216 #size-cells = <0>; 217 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 218 clocks = <&scu ASPEED_CLK_GATE_MAC2CLK>; 219 status = "disabled"; 220 }; 221 222 mac2: ftgmac@1e670000 { 223 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 224 reg = <0x1e670000 0x180>, <0x1e650010 0x4>; 225 #address-cells = <1>; 226 #size-cells = <0>; 227 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 228 clocks = <&scu ASPEED_CLK_GATE_MAC3CLK>; 229 status = "disabled"; 230 }; 231 232 mac3: ftgmac@1e690000 { 233 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 234 reg = <0x1e690000 0x180>, <0x1e650018 0x4>; 235 #address-cells = <1>; 236 #size-cells = <0>; 237 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 238 clocks = <&scu ASPEED_CLK_GATE_MAC4CLK>; 239 status = "disabled"; 240 }; 241 242 vhub: usb-vhub@1e6a0000 { 243 compatible = "aspeed,ast2600-usb-vhub"; 244 reg = <0x1e6a0000 0x350>; 245 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 246 clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>; 247 resets = <&rst ASPEED_RESET_EHCI_P1>; 248 pinctrl-names = "default"; 249 pinctrl-0 = <&pinctrl_usb2ad_default>; 250 status = "disabled"; 251 }; 252 253 ehci0: usb@1e6a1000 { 254 compatible = "aspeed,aspeed-ehci", "usb-ehci"; 255 reg = <0x1e6a1000 0x100>; 256 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 257 clocks = <&scu ASPEED_CLK_GATE_USBPORT1CLK>; 258 pinctrl-names = "default"; 259 pinctrl-0 = <&pinctrl_usb2ah_default>; 260 status = "disabled"; 261 }; 262 263 ehci1: usb@1e6a3000 { 264 compatible = "aspeed,aspeed-ehci", "usb-ehci"; 265 reg = <0x1e6a3000 0x100>; 266 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 267 clocks = <&scu ASPEED_CLK_GATE_USBPORT2CLK>; 268 pinctrl-names = "default"; 269 pinctrl-0 = <&pinctrl_usb2bh_default>; 270 status = "disabled"; 271 }; 272 273 apb { 274 compatible = "simple-bus"; 275 #address-cells = <1>; 276 #size-cells = <1>; 277 ranges; 278 u-boot,dm-pre-reloc; 279 280 syscon: syscon@1e6e2000 { 281 compatible = "aspeed,g6-scu", "syscon", "simple-mfd"; 282 reg = <0x1e6e2000 0x1000>; 283 #address-cells = <1>; 284 #size-cells = <1>; 285 #clock-cells = <1>; 286 #reset-cells = <1>; 287 ranges = <0 0x1e6e2000 0x1000>; 288 u-boot,dm-pre-reloc; 289 290 pinctrl: pinctrl { 291 compatible = "aspeed,g6-pinctrl"; 292 aspeed,external-nodes = <&gfx &lhc>; 293 u-boot,dm-pre-reloc; 294 }; 295 296 vga_scratch: scratch { 297 compatible = "aspeed,bmc-misc"; 298 }; 299 300 scu_ic0: interrupt-controller@0 { 301 #interrupt-cells = <1>; 302 compatible = "aspeed,ast2600-scu-ic"; 303 reg = <0x560 0x10>; 304 interrupt-parent = <&gic>; 305 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 306 interrupt-controller; 307 }; 308 309 scu_ic1: interrupt-controller@1 { 310 #interrupt-cells = <1>; 311 compatible = "aspeed,ast2600-scu-ic"; 312 reg = <0x570 0x10>; 313 interrupt-parent = <&gic>; 314 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 315 interrupt-controller; 316 }; 317 318 }; 319 320 hace: hace@1e6d0000 { 321 compatible = "aspeed,ast2600-hace"; 322 reg = <0x1e6d0000 0x200>; 323 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 324 clocks = <&scu ASPEED_CLK_GATE_YCLK>; 325 clock-names = "yclk"; 326 status = "disabled"; 327 }; 328 329 acry: acry@1e6fa000 { 330 compatible = "aspeed,ast2600-acry"; 331 reg = <0x1e6fa000 0x1000>; 332 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 333 clocks = <&scu ASPEED_CLK_GATE_RSAECCCLK>; 334 clock-names = "rsaeccclk"; 335 status = "disabled"; 336 }; 337 338 smp-memram@0 { 339 compatible = "aspeed,ast2600-smpmem", "syscon"; 340 reg = <0x1e6e2180 0x40>; 341 }; 342 343 gfx: display@1e6e6000 { 344 compatible = "aspeed,ast2500-gfx", "syscon"; 345 reg = <0x1e6e6000 0x1000>; 346 reg-io-width = <4>; 347 }; 348 349 pcie_bridge0: pcie@1e6ed000 { 350 compatible = "aspeed,ast2600-pcie"; 351 #address-cells = <3>; 352 #size-cells = <2>; 353 reg = <0x1e6ed000 0x100>; 354 ranges = <0x81000000 0x0 0x0 0x0 0x0 0x10000 /* downstream I/O */ 355 0x82000000 0x0 0x60000000 0x60000000 0x0 0x10000000>; /* non-prefetchable memory */ 356 device_type = "pci"; 357 bus-range = <0x00 0xff>; 358 resets = <&rst ASPEED_RESET_PCIE_DEV_O>; 359 cfg-handle = <&pcie_cfg0>; 360 pinctrl-names = "default"; 361 pinctrl-0 = <&pinctrl_pcie0rc_default>; 362 363 status = "disabled"; 364 }; 365 366 pcie_bridge1: pcie@1e6ed200 { 367 compatible = "aspeed,ast2600-pcie"; 368 #address-cells = <3>; 369 #size-cells = <2>; 370 reg = <0x1e6ed200 0x100>; 371 ranges = <0x81000000 0x0 0x0 0x10000 0x00 0x10000 /* downstream I/O */ 372 0x82000000 0x0 0x70000000 0x70000000 0x0 0x10000000>; /* non-prefetchable memory */ 373 device_type = "pci"; 374 bus-range = <0x00 0xff>; 375 resets = <&rst ASPEED_RESET_PCIE_RC_O>; 376 cfg-handle = <&pcie_cfg1>; 377 pinctrl-names = "default"; 378 pinctrl-0 = <&pinctrl_pcie1rc_default>; 379 380 status = "disabled"; 381 }; 382 383 sdhci: sdhci@1e740000 { 384 #interrupt-cells = <1>; 385 compatible = "aspeed,aspeed-sdhci-irq", "simple-mfd"; 386 reg = <0x1e740000 0x1000>; 387 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 388 interrupt-controller; 389 clocks = <&scu ASPEED_CLK_GATE_SDCLK>, <&scu ASPEED_CLK_GATE_SDEXTCLK>; 390 clock-names = "ctrlclk", "extclk"; 391 #address-cells = <1>; 392 #size-cells = <1>; 393 ranges = <0x0 0x1e740000 0x1000>; 394 395 sdhci_slot0: sdhci_slot0@100 { 396 compatible = "aspeed,sdhci-ast2600"; 397 reg = <0x100 0x100>; 398 interrupts = <0>; 399 interrupt-parent = <&sdhci>; 400 sdhci,auto-cmd12; 401 clocks = <&scu ASPEED_CLK_SDIO>; 402 status = "disabled"; 403 }; 404 405 sdhci_slot1: sdhci_slot1@200 { 406 compatible = "aspeed,sdhci-ast2600"; 407 reg = <0x200 0x100>; 408 interrupts = <1>; 409 interrupt-parent = <&sdhci>; 410 sdhci,auto-cmd12; 411 clocks = <&scu ASPEED_CLK_SDIO>; 412 status = "disabled"; 413 }; 414 }; 415 416 emmc: emmc@1e750000 { 417 #interrupt-cells = <1>; 418 compatible = "aspeed,aspeed-emmc-irq", "simple-mfd"; 419 reg = <0x1e750000 0x1000>; 420 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 421 interrupt-controller; 422 clocks = <&scu ASPEED_CLK_GATE_EMMCCLK>, <&scu ASPEED_CLK_GATE_EMMCEXTCLK>; 423 clock-names = "ctrlclk", "extclk"; 424 #address-cells = <1>; 425 #size-cells = <1>; 426 ranges = <0x0 0x1e750000 0x1000>; 427 428 emmc_slot0: emmc_slot0@100 { 429 compatible = "aspeed,emmc-ast2600"; 430 reg = <0x100 0x100>; 431 interrupts = <0>; 432 interrupt-parent = <&emmc>; 433 clocks = <&scu ASPEED_CLK_EMMC>; 434 status = "disabled"; 435 }; 436 }; 437 438 h2x: h2x@1e770000 { 439 compatible = "aspeed,ast2600-h2x"; 440 reg = <0x1e770000 0x100>; 441 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 442 resets = <&rst ASPEED_RESET_H2X>; 443 #address-cells = <1>; 444 #size-cells = <1>; 445 ranges = <0x0 0x1e770000 0x100>; 446 447 status = "disabled"; 448 449 pcie_cfg0: cfg0@80 { 450 reg = <0x80 0x80>; 451 compatible = "aspeed,ast2600-pcie-cfg"; 452 }; 453 454 pcie_cfg1: cfg1@C0 { 455 compatible = "aspeed,ast2600-pcie-cfg"; 456 reg = <0xC0 0x80>; 457 }; 458 }; 459 460 gpio0: gpio@1e780000 { 461 compatible = "aspeed,ast2600-gpio"; 462 reg = <0x1e780000 0x400>; 463 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 464 #gpio-cells = <2>; 465 gpio-controller; 466 interrupt-controller; 467 gpio-ranges = <&pinctrl 0 0 208>; 468 ngpios = <208>; 469 }; 470 471 gpio1: gpio@1e780800 { 472 compatible = "aspeed,ast2600-gpio"; 473 reg = <0x1e780800 0x800>; 474 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 475 #gpio-cells = <2>; 476 gpio-controller; 477 interrupt-controller; 478 gpio-ranges = <&pinctrl 0 208 36>; 479 ngpios = <36>; 480 }; 481 482 uart1: serial@1e783000 { 483 compatible = "ns16550a"; 484 reg = <0x1e783000 0x20>; 485 reg-shift = <2>; 486 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 487 clocks = <&scu ASPEED_CLK_GATE_UART1CLK>; 488 clock-frequency = <1846154>; 489 no-loopback-test; 490 u-boot,dm-pre-reloc; 491 pinctrl-names = "default"; 492 pinctrl-0 = <&pinctrl_txd1_default &pinctrl_rxd1_default>; 493 status = "disabled"; 494 }; 495 496 uart5: serial@1e784000 { 497 compatible = "ns16550a"; 498 reg = <0x1e784000 0x1000>; 499 reg-shift = <2>; 500 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 501 clocks = <&scu ASPEED_CLK_GATE_UART5CLK>; 502 clock-frequency = <1846154>; 503 no-loopback-test; 504 u-boot,dm-pre-reloc; 505 status = "disabled"; 506 }; 507 508 wdt1: watchdog@1e785000 { 509 compatible = "aspeed,ast2600-wdt"; 510 reg = <0x1e785000 0x40>; 511 }; 512 513 wdt2: watchdog@1e785040 { 514 compatible = "aspeed,ast2600-wdt"; 515 reg = <0x1e785040 0x40>; 516 }; 517 518 wdt3: watchdog@1e785080 { 519 compatible = "aspeed,ast2600-wdt"; 520 reg = <0x1e785080 0x40>; 521 }; 522 523 wdt4: watchdog@1e7850C0 { 524 compatible = "aspeed,ast2600-wdt"; 525 reg = <0x1e7850C0 0x40>; 526 }; 527 528 lpc: lpc@1e789000 { 529 compatible = "aspeed,ast-lpc", "simple-mfd", "syscon"; 530 reg = <0x1e789000 0x200>; 531 532 #address-cells = <1>; 533 #size-cells = <1>; 534 ranges = <0x0 0x1e789000 0x1000>; 535 536 lpc_bmc: lpc-bmc@0 { 537 compatible = "aspeed,ast2600-lpc-bmc", "simple-mfd", "syscon"; 538 reg = <0x0 0x80>; 539 reg-io-width = <4>; 540 #address-cells = <1>; 541 #size-cells = <1>; 542 ranges = <0x0 0x0 0x80>; 543 544 kcs1: kcs1@0 { 545 compatible = "aspeed,ast2600-kcs-bmc"; 546 reg = <0x0 0x80>; 547 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 548 kcs_chan = <1>; 549 kcs_addr = <0xCA0>; 550 status = "disabled"; 551 }; 552 553 kcs2: kcs2@0 { 554 compatible = "aspeed,ast2600-kcs-bmc"; 555 reg = <0x0 0x80>; 556 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 557 kcs_chan = <2>; 558 kcs_addr = <0xCA8>; 559 status = "disabled"; 560 }; 561 562 kcs3: kcs3@0 { 563 compatible = "aspeed,ast2600-kcs-bmc"; 564 reg = <0x0 0x80>; 565 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 566 kcs_chan = <3>; 567 kcs_addr = <0xCA2>; 568 }; 569 570 kcs4: kcs4@0 { 571 compatible = "aspeed,ast2600-kcs-bmc"; 572 reg = <0x0 0x120>; 573 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 574 kcs_chan = <4>; 575 kcs_addr = <0xCA4>; 576 status = "disabled"; 577 }; 578 579 }; 580 581 lpc_host: lpc-host@80 { 582 compatible = "aspeed,ast2600-lpc-host", "simple-mfd", "syscon"; 583 reg = <0x80 0x1e0>; 584 reg-io-width = <4>; 585 586 #address-cells = <1>; 587 #size-cells = <1>; 588 ranges = <0x0 0x80 0x1e0>; 589 590 lpc_ctrl: lpc-ctrl@0 { 591 compatible = "aspeed,ast2600-lpc-ctrl"; 592 reg = <0x0 0x80>; 593 status = "disabled"; 594 }; 595 596 lpc_snoop: lpc-snoop@0 { 597 compatible = "aspeed,ast2600-lpc-snoop"; 598 reg = <0x0 0x80>; 599 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 600 snoop-ports = <0x80>; 601 status = "disabled"; 602 }; 603 604 lhc: lhc@20 { 605 compatible = "aspeed,ast2600-lhc"; 606 reg = <0x20 0x24 0x48 0x8>; 607 }; 608 609 lpc_reset: reset-controller@18 { 610 compatible = "aspeed,ast2600-lpc-reset"; 611 reg = <0x18 0x4>; 612 #reset-cells = <1>; 613 status = "disabled"; 614 }; 615 616 ibt: ibt@c0 { 617 compatible = "aspeed,ast2600-ibt-bmc"; 618 reg = <0xc0 0x18>; 619 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 620 status = "disabled"; 621 }; 622 623 sio_regs: regs { 624 compatible = "aspeed,bmc-misc"; 625 }; 626 627 mbox: mbox@180 { 628 compatible = "aspeed,ast2600-mbox"; 629 reg = <0x180 0x5c>; 630 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 631 #mbox-cells = <1>; 632 status = "disabled"; 633 }; 634 }; 635 }; 636 637 uart2: serial@1e78d000 { 638 compatible = "ns16550a"; 639 reg = <0x1e78d000 0x20>; 640 reg-shift = <2>; 641 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 642 clocks = <&scu ASPEED_CLK_GATE_UART2CLK>; 643 clock-frequency = <1846154>; 644 no-loopback-test; 645 pinctrl-names = "default"; 646 pinctrl-0 = <&pinctrl_txd2_default &pinctrl_rxd2_default>; 647 u-boot,dm-pre-reloc; 648 status = "disabled"; 649 }; 650 651 uart3: serial@1e78e000 { 652 compatible = "ns16550a"; 653 reg = <0x1e78e000 0x20>; 654 reg-shift = <2>; 655 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 656 clocks = <&scu ASPEED_CLK_GATE_UART3CLK>; 657 clock-frequency = <1846154>; 658 no-loopback-test; 659 pinctrl-names = "default"; 660 pinctrl-0 = <&pinctrl_txd3_default &pinctrl_rxd3_default>; 661 u-boot,dm-pre-reloc; 662 status = "disabled"; 663 }; 664 665 uart4: serial@1e78f000 { 666 compatible = "ns16550a"; 667 reg = <0x1e78f000 0x20>; 668 reg-shift = <2>; 669 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 670 clocks = <&scu ASPEED_CLK_GATE_UART4CLK>; 671 clock-frequency = <1846154>; 672 no-loopback-test; 673 u-boot,dm-pre-reloc; 674 pinctrl-names = "default"; 675 pinctrl-0 = <&pinctrl_txd4_default &pinctrl_rxd4_default>; 676 status = "disabled"; 677 }; 678 679 i2c: bus@1e78a000 { 680 compatible = "simple-bus"; 681 #address-cells = <1>; 682 #size-cells = <1>; 683 ranges = <0 0x1e78a000 0x1000>; 684 }; 685 686 fsim0: fsi@1e79b000 { 687 compatible = "aspeed,ast2600-fsi-master", "fsi-master"; 688 reg = <0x1e79b000 0x94>; 689 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 690 pinctrl-names = "default"; 691 pinctrl-0 = <&pinctrl_fsi1_default>; 692 clocks = <&scu ASPEED_CLK_GATE_FSICLK>; 693 status = "disabled"; 694 }; 695 696 fsim1: fsi@1e79b100 { 697 compatible = "aspeed,ast2600-fsi-master", "fsi-master"; 698 reg = <0x1e79b100 0x94>; 699 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 700 pinctrl-names = "default"; 701 pinctrl-0 = <&pinctrl_fsi2_default>; 702 clocks = <&scu ASPEED_CLK_GATE_FSICLK>; 703 status = "disabled"; 704 }; 705 706 uart6: serial@1e790000 { 707 compatible = "ns16550a"; 708 reg = <0x1e790000 0x20>; 709 reg-shift = <2>; 710 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 711 clocks = <&scu ASPEED_CLK_GATE_UART6CLK>; 712 clock-frequency = <1846154>; 713 no-loopback-test; 714 status = "disabled"; 715 }; 716 717 uart7: serial@1e790100 { 718 compatible = "ns16550a"; 719 reg = <0x1e790100 0x20>; 720 reg-shift = <2>; 721 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 722 clocks = <&scu ASPEED_CLK_GATE_UART7CLK>; 723 clock-frequency = <1846154>; 724 no-loopback-test; 725 status = "disabled"; 726 }; 727 728 uart8: serial@1e790200 { 729 compatible = "ns16550a"; 730 reg = <0x1e790200 0x20>; 731 reg-shift = <2>; 732 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 733 clocks = <&scu ASPEED_CLK_GATE_UART8CLK>; 734 clock-frequency = <1846154>; 735 no-loopback-test; 736 status = "disabled"; 737 }; 738 739 uart9: serial@1e790300 { 740 compatible = "ns16550a"; 741 reg = <0x1e790300 0x20>; 742 reg-shift = <2>; 743 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 744 clocks = <&scu ASPEED_CLK_GATE_UART9CLK>; 745 clock-frequency = <1846154>; 746 no-loopback-test; 747 status = "disabled"; 748 }; 749 750 uart10: serial@1e790400 { 751 compatible = "ns16550a"; 752 reg = <0x1e790400 0x20>; 753 reg-shift = <2>; 754 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 755 clocks = <&scu ASPEED_CLK_GATE_UART10CLK>; 756 clock-frequency = <1846154>; 757 no-loopback-test; 758 status = "disabled"; 759 }; 760 761 uart11: serial@1e790500 { 762 compatible = "ns16550a"; 763 reg = <0x1e790400 0x20>; 764 reg-shift = <2>; 765 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 766 clocks = <&scu ASPEED_CLK_GATE_UART11CLK>; 767 clock-frequency = <1846154>; 768 no-loopback-test; 769 status = "disabled"; 770 }; 771 772 uart12: serial@1e790600 { 773 compatible = "ns16550a"; 774 reg = <0x1e790600 0x20>; 775 reg-shift = <2>; 776 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 777 clocks = <&scu ASPEED_CLK_GATE_UART12CLK>; 778 clock-frequency = <1846154>; 779 no-loopback-test; 780 status = "disabled"; 781 }; 782 783 uart13: serial@1e790700 { 784 compatible = "ns16550a"; 785 reg = <0x1e790700 0x20>; 786 reg-shift = <2>; 787 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 788 clocks = <&scu ASPEED_CLK_GATE_UART13CLK>; 789 clock-frequency = <1846154>; 790 no-loopback-test; 791 status = "disabled"; 792 }; 793 794 display_port: dp@1e6eb000 { 795 compatible = "aspeed,ast2600-displayport"; 796 reg = <0x1e6eb000 0x200>; 797 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 798 resets = <&rst ASPEED_RESET_DP> ,<&rst ASPEED_RESET_DP_MCU>; 799 status = "disabled"; 800 }; 801 802 }; 803 804 }; 805 806}; 807 808&i2c { 809 i2cglobal: i2cg@00 { 810 compatible = "aspeed,ast2600-i2c-global"; 811 reg = <0x0 0x40>; 812 resets = <&rst ASPEED_RESET_I2C>; 813#if 0 814 new-mode; 815#endif 816 }; 817 818 i2c0: i2c@80 { 819 #address-cells = <1>; 820 #size-cells = <0>; 821 #interrupt-cells = <1>; 822 823 reg = <0x80 0x80 0xC00 0x20>; 824 compatible = "aspeed,ast2600-i2c-bus"; 825 bus-frequency = <100000>; 826 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 827 clocks = <&scu ASPEED_CLK_APB2>; 828 status = "disabled"; 829 }; 830 831 i2c1: i2c@100 { 832 #address-cells = <1>; 833 #size-cells = <0>; 834 #interrupt-cells = <1>; 835 836 reg = <0x100 0x80 0xC20 0x20>; 837 compatible = "aspeed,ast2600-i2c-bus"; 838 bus-frequency = <100000>; 839 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 840 clocks = <&scu ASPEED_CLK_APB2>; 841 status = "disabled"; 842 }; 843 844 i2c2: i2c@180 { 845 #address-cells = <1>; 846 #size-cells = <0>; 847 #interrupt-cells = <1>; 848 849 reg = <0x180 0x80 0xC40 0x20>; 850 compatible = "aspeed,ast2600-i2c-bus"; 851 bus-frequency = <100000>; 852 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 853 clocks = <&scu ASPEED_CLK_APB2>; 854 }; 855 856 i2c3: i2c@200 { 857 #address-cells = <1>; 858 #size-cells = <0>; 859 #interrupt-cells = <1>; 860 861 reg = <0x200 0x40 0xC60 0x20>; 862 compatible = "aspeed,ast2600-i2c-bus"; 863 bus-frequency = <100000>; 864 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 865 clocks = <&scu ASPEED_CLK_APB2>; 866 }; 867 868 i2c4: i2c@280 { 869 #address-cells = <1>; 870 #size-cells = <0>; 871 #interrupt-cells = <1>; 872 873 reg = <0x280 0x80 0xC80 0x20>; 874 compatible = "aspeed,ast2600-i2c-bus"; 875 bus-frequency = <100000>; 876 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 877 clocks = <&scu ASPEED_CLK_APB2>; 878 }; 879 880 i2c5: i2c@300 { 881 #address-cells = <1>; 882 #size-cells = <0>; 883 #interrupt-cells = <1>; 884 885 reg = <0x300 0x40 0xCA0 0x20>; 886 compatible = "aspeed,ast2600-i2c-bus"; 887 bus-frequency = <100000>; 888 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 889 clocks = <&scu ASPEED_CLK_APB2>; 890 }; 891 892 i2c6: i2c@380 { 893 #address-cells = <1>; 894 #size-cells = <0>; 895 #interrupt-cells = <1>; 896 897 reg = <0x380 0x80 0xCC0 0x20>; 898 compatible = "aspeed,ast2600-i2c-bus"; 899 bus-frequency = <100000>; 900 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 901 clocks = <&scu ASPEED_CLK_APB2>; 902 }; 903 904 i2c7: i2c@400 { 905 #address-cells = <1>; 906 #size-cells = <0>; 907 #interrupt-cells = <1>; 908 909 reg = <0x400 0x80 0xCE0 0x20>; 910 compatible = "aspeed,ast2600-i2c-bus"; 911 bus-frequency = <100000>; 912 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 913 clocks = <&scu ASPEED_CLK_APB2>; 914 }; 915 916 i2c8: i2c@480 { 917 #address-cells = <1>; 918 #size-cells = <0>; 919 #interrupt-cells = <1>; 920 921 reg = <0x480 0x80 0xD00 0x20>; 922 compatible = "aspeed,ast2600-i2c-bus"; 923 bus-frequency = <100000>; 924 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 925 clocks = <&scu ASPEED_CLK_APB2>; 926 }; 927 928 i2c9: i2c@500 { 929 #address-cells = <1>; 930 #size-cells = <0>; 931 #interrupt-cells = <1>; 932 933 reg = <0x500 0x80 0xD20 0x20>; 934 compatible = "aspeed,ast2600-i2c-bus"; 935 bus-frequency = <100000>; 936 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 937 clocks = <&scu ASPEED_CLK_APB2>; 938 status = "disabled"; 939 }; 940 941 i2c10: i2c@580 { 942 #address-cells = <1>; 943 #size-cells = <0>; 944 #interrupt-cells = <1>; 945 946 reg = <0x580 0x80 0xD40 0x20>; 947 compatible = "aspeed,ast2600-i2c-bus"; 948 bus-frequency = <100000>; 949 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 950 clocks = <&scu ASPEED_CLK_APB2>; 951 status = "disabled"; 952 }; 953 954 i2c11: i2c@600 { 955 #address-cells = <1>; 956 #size-cells = <0>; 957 #interrupt-cells = <1>; 958 959 reg = <0x600 0x80 0xD60 0x20>; 960 compatible = "aspeed,ast2600-i2c-bus"; 961 bus-frequency = <100000>; 962 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 963 clocks = <&scu ASPEED_CLK_APB2>; 964 status = "disabled"; 965 }; 966 967 i2c12: i2c@680 { 968 #address-cells = <1>; 969 #size-cells = <0>; 970 #interrupt-cells = <1>; 971 972 reg = <0x680 0x80 0xD80 0x20>; 973 compatible = "aspeed,ast2600-i2c-bus"; 974 bus-frequency = <100000>; 975 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 976 clocks = <&scu ASPEED_CLK_APB2>; 977 status = "disabled"; 978 }; 979 980 i2c13: i2c@700 { 981 #address-cells = <1>; 982 #size-cells = <0>; 983 #interrupt-cells = <1>; 984 985 reg = <0x700 0x80 0xDA0 0x20>; 986 compatible = "aspeed,ast2600-i2c-bus"; 987 bus-frequency = <100000>; 988 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 989 clocks = <&scu ASPEED_CLK_APB2>; 990 status = "disabled"; 991 }; 992 993 i2c14: i2c@780 { 994 #address-cells = <1>; 995 #size-cells = <0>; 996 #interrupt-cells = <1>; 997 998 reg = <0x780 0x80 0xDC0 0x20>; 999 compatible = "aspeed,ast2600-i2c-bus"; 1000 bus-frequency = <100000>; 1001 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 1002 clocks = <&scu ASPEED_CLK_APB2>; 1003 status = "disabled"; 1004 }; 1005 1006 i2c15: i2c@800 { 1007 #address-cells = <1>; 1008 #size-cells = <0>; 1009 #interrupt-cells = <1>; 1010 1011 reg = <0x800 0x80 0xDE0 0x20>; 1012 compatible = "aspeed,ast2600-i2c-bus"; 1013 bus-frequency = <100000>; 1014 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 1015 clocks = <&scu ASPEED_CLK_APB2>; 1016 status = "disabled"; 1017 }; 1018 1019}; 1020 1021&pinctrl { 1022 u-boot,dm-pre-reloc; 1023 1024 pinctrl_fmcquad_default: fmcquad_default { 1025 function = "FMCQUAD"; 1026 groups = "FMCQUAD"; 1027 }; 1028 1029 pinctrl_spi1_default: spi1_default { 1030 function = "SPI1"; 1031 groups = "SPI1"; 1032 }; 1033 1034 pinctrl_spi1abr_default: spi1abr_default { 1035 function = "SPI1ABR"; 1036 groups = "SPI1ABR"; 1037 }; 1038 1039 pinctrl_spi1cs1_default: spi1cs1_default { 1040 function = "SPI1CS1"; 1041 groups = "SPI1CS1"; 1042 }; 1043 1044 pinctrl_spi1wp_default: spi1wp_default { 1045 function = "SPI1WP"; 1046 groups = "SPI1WP"; 1047 }; 1048 1049 pinctrl_spi1quad_default: spi1quad_default { 1050 function = "SPI1QUAD"; 1051 groups = "SPI1QUAD"; 1052 }; 1053 1054 pinctrl_spi2_default: spi2_default { 1055 function = "SPI2"; 1056 groups = "SPI2"; 1057 }; 1058 1059 pinctrl_spi2cs1_default: spi2cs1_default { 1060 function = "SPI2CS1"; 1061 groups = "SPI2CS1"; 1062 }; 1063 1064 pinctrl_spi2cs2_default: spi2cs2_default { 1065 function = "SPI2CS2"; 1066 groups = "SPI2CS2"; 1067 }; 1068 1069 pinctrl_spi2quad_default: spi2quad_default { 1070 function = "SPI2QUAD"; 1071 groups = "SPI2QUAD"; 1072 }; 1073 1074 pinctrl_acpi_default: acpi_default { 1075 function = "ACPI"; 1076 groups = "ACPI"; 1077 }; 1078 1079 pinctrl_adc0_default: adc0_default { 1080 function = "ADC0"; 1081 groups = "ADC0"; 1082 }; 1083 1084 pinctrl_adc1_default: adc1_default { 1085 function = "ADC1"; 1086 groups = "ADC1"; 1087 }; 1088 1089 pinctrl_adc10_default: adc10_default { 1090 function = "ADC10"; 1091 groups = "ADC10"; 1092 }; 1093 1094 pinctrl_adc11_default: adc11_default { 1095 function = "ADC11"; 1096 groups = "ADC11"; 1097 }; 1098 1099 pinctrl_adc12_default: adc12_default { 1100 function = "ADC12"; 1101 groups = "ADC12"; 1102 }; 1103 1104 pinctrl_adc13_default: adc13_default { 1105 function = "ADC13"; 1106 groups = "ADC13"; 1107 }; 1108 1109 pinctrl_adc14_default: adc14_default { 1110 function = "ADC14"; 1111 groups = "ADC14"; 1112 }; 1113 1114 pinctrl_adc15_default: adc15_default { 1115 function = "ADC15"; 1116 groups = "ADC15"; 1117 }; 1118 1119 pinctrl_adc2_default: adc2_default { 1120 function = "ADC2"; 1121 groups = "ADC2"; 1122 }; 1123 1124 pinctrl_adc3_default: adc3_default { 1125 function = "ADC3"; 1126 groups = "ADC3"; 1127 }; 1128 1129 pinctrl_adc4_default: adc4_default { 1130 function = "ADC4"; 1131 groups = "ADC4"; 1132 }; 1133 1134 pinctrl_adc5_default: adc5_default { 1135 function = "ADC5"; 1136 groups = "ADC5"; 1137 }; 1138 1139 pinctrl_adc6_default: adc6_default { 1140 function = "ADC6"; 1141 groups = "ADC6"; 1142 }; 1143 1144 pinctrl_adc7_default: adc7_default { 1145 function = "ADC7"; 1146 groups = "ADC7"; 1147 }; 1148 1149 pinctrl_adc8_default: adc8_default { 1150 function = "ADC8"; 1151 groups = "ADC8"; 1152 }; 1153 1154 pinctrl_adc9_default: adc9_default { 1155 function = "ADC9"; 1156 groups = "ADC9"; 1157 }; 1158 1159 pinctrl_bmcint_default: bmcint_default { 1160 function = "BMCINT"; 1161 groups = "BMCINT"; 1162 }; 1163 1164 pinctrl_ddcclk_default: ddcclk_default { 1165 function = "DDCCLK"; 1166 groups = "DDCCLK"; 1167 }; 1168 1169 pinctrl_ddcdat_default: ddcdat_default { 1170 function = "DDCDAT"; 1171 groups = "DDCDAT"; 1172 }; 1173 1174 pinctrl_espi_default: espi_default { 1175 function = "ESPI"; 1176 groups = "ESPI"; 1177 }; 1178 1179 pinctrl_fsi1_default: fsi1_default { 1180 function = "FSI1"; 1181 groups = "FSI1"; 1182 }; 1183 1184 pinctrl_fsi2_default: fsi2_default { 1185 function = "FSI2"; 1186 groups = "FSI2"; 1187 }; 1188 1189 pinctrl_fwspics1_default: fwspics1_default { 1190 function = "FWSPICS1"; 1191 groups = "FWSPICS1"; 1192 }; 1193 1194 pinctrl_fwspics2_default: fwspics2_default { 1195 function = "FWSPICS2"; 1196 groups = "FWSPICS2"; 1197 }; 1198 1199 pinctrl_gpid0_default: gpid0_default { 1200 function = "GPID0"; 1201 groups = "GPID0"; 1202 }; 1203 1204 pinctrl_gpid2_default: gpid2_default { 1205 function = "GPID2"; 1206 groups = "GPID2"; 1207 }; 1208 1209 pinctrl_gpid4_default: gpid4_default { 1210 function = "GPID4"; 1211 groups = "GPID4"; 1212 }; 1213 1214 pinctrl_gpid6_default: gpid6_default { 1215 function = "GPID6"; 1216 groups = "GPID6"; 1217 }; 1218 1219 pinctrl_gpie0_default: gpie0_default { 1220 function = "GPIE0"; 1221 groups = "GPIE0"; 1222 }; 1223 1224 pinctrl_gpie2_default: gpie2_default { 1225 function = "GPIE2"; 1226 groups = "GPIE2"; 1227 }; 1228 1229 pinctrl_gpie4_default: gpie4_default { 1230 function = "GPIE4"; 1231 groups = "GPIE4"; 1232 }; 1233 1234 pinctrl_gpie6_default: gpie6_default { 1235 function = "GPIE6"; 1236 groups = "GPIE6"; 1237 }; 1238 1239 pinctrl_i2c1_default: i2c1_default { 1240 function = "I2C1"; 1241 groups = "I2C1"; 1242 }; 1243 pinctrl_i2c2_default: i2c2_default { 1244 function = "I2C2"; 1245 groups = "I2C2"; 1246 }; 1247 1248 pinctrl_i2c3_default: i2c3_default { 1249 function = "I2C3"; 1250 groups = "I2C3"; 1251 }; 1252 1253 pinctrl_i2c4_default: i2c4_default { 1254 function = "I2C4"; 1255 groups = "I2C4"; 1256 }; 1257 1258 pinctrl_i2c5_default: i2c5_default { 1259 function = "I2C5"; 1260 groups = "I2C5"; 1261 }; 1262 1263 pinctrl_i2c6_default: i2c6_default { 1264 function = "I2C6"; 1265 groups = "I2C6"; 1266 }; 1267 1268 pinctrl_i2c7_default: i2c7_default { 1269 function = "I2C7"; 1270 groups = "I2C7"; 1271 }; 1272 1273 pinctrl_i2c8_default: i2c8_default { 1274 function = "I2C8"; 1275 groups = "I2C8"; 1276 }; 1277 1278 pinctrl_i2c9_default: i2c9_default { 1279 function = "I2C9"; 1280 groups = "I2C9"; 1281 }; 1282 1283 pinctrl_i2c10_default: i2c10_default { 1284 function = "I2C10"; 1285 groups = "I2C10"; 1286 }; 1287 1288 pinctrl_i2c11_default: i2c11_default { 1289 function = "I2C11"; 1290 groups = "I2C11"; 1291 }; 1292 1293 pinctrl_i2c12_default: i2c12_default { 1294 function = "I2C12"; 1295 groups = "I2C12"; 1296 }; 1297 1298 pinctrl_i2c13_default: i2c13_default { 1299 function = "I2C13"; 1300 groups = "I2C13"; 1301 }; 1302 1303 pinctrl_i2c14_default: i2c14_default { 1304 function = "I2C14"; 1305 groups = "I2C14"; 1306 }; 1307 1308 pinctrl_i2c15_default: i2c15_default { 1309 function = "I2C15"; 1310 groups = "I2C15"; 1311 }; 1312 1313 pinctrl_i2c16_default: i2c16_default { 1314 function = "I2C16"; 1315 groups = "I2C16"; 1316 }; 1317 1318 pinctrl_lad0_default: lad0_default { 1319 function = "LAD0"; 1320 groups = "LAD0"; 1321 }; 1322 1323 pinctrl_lad1_default: lad1_default { 1324 function = "LAD1"; 1325 groups = "LAD1"; 1326 }; 1327 1328 pinctrl_lad2_default: lad2_default { 1329 function = "LAD2"; 1330 groups = "LAD2"; 1331 }; 1332 1333 pinctrl_lad3_default: lad3_default { 1334 function = "LAD3"; 1335 groups = "LAD3"; 1336 }; 1337 1338 pinctrl_lclk_default: lclk_default { 1339 function = "LCLK"; 1340 groups = "LCLK"; 1341 }; 1342 1343 pinctrl_lframe_default: lframe_default { 1344 function = "LFRAME"; 1345 groups = "LFRAME"; 1346 }; 1347 1348 pinctrl_lpchc_default: lpchc_default { 1349 function = "LPCHC"; 1350 groups = "LPCHC"; 1351 }; 1352 1353 pinctrl_lpcpd_default: lpcpd_default { 1354 function = "LPCPD"; 1355 groups = "LPCPD"; 1356 }; 1357 1358 pinctrl_lpcplus_default: lpcplus_default { 1359 function = "LPCPLUS"; 1360 groups = "LPCPLUS"; 1361 }; 1362 1363 pinctrl_lpcpme_default: lpcpme_default { 1364 function = "LPCPME"; 1365 groups = "LPCPME"; 1366 }; 1367 1368 pinctrl_lpcrst_default: lpcrst_default { 1369 function = "LPCRST"; 1370 groups = "LPCRST"; 1371 }; 1372 1373 pinctrl_lpcsmi_default: lpcsmi_default { 1374 function = "LPCSMI"; 1375 groups = "LPCSMI"; 1376 }; 1377 1378 pinctrl_lsirq_default: lsirq_default { 1379 function = "LSIRQ"; 1380 groups = "LSIRQ"; 1381 }; 1382 1383 pinctrl_mac1link_default: mac1link_default { 1384 function = "MAC1LINK"; 1385 groups = "MAC1LINK"; 1386 }; 1387 1388 pinctrl_mac2link_default: mac2link_default { 1389 function = "MAC2LINK"; 1390 groups = "MAC2LINK"; 1391 }; 1392 1393 pinctrl_mac3link_default: mac3link_default { 1394 function = "MAC3LINK"; 1395 groups = "MAC3LINK"; 1396 }; 1397 1398 pinctrl_mac4link_default: mac4link_default { 1399 function = "MAC4LINK"; 1400 groups = "MAC4LINK"; 1401 }; 1402 1403 pinctrl_mdio1_default: mdio1_default { 1404 function = "MDIO1"; 1405 groups = "MDIO1"; 1406 }; 1407 1408 pinctrl_mdio2_default: mdio2_default { 1409 function = "MDIO2"; 1410 groups = "MDIO2"; 1411 }; 1412 1413 pinctrl_mdio3_default: mdio3_default { 1414 function = "MDIO3"; 1415 groups = "MDIO3"; 1416 }; 1417 1418 pinctrl_mdio4_default: mdio4_default { 1419 function = "MDIO4"; 1420 groups = "MDIO4"; 1421 }; 1422 1423 pinctrl_rmii1_default: rmii1_default { 1424 function = "RMII1"; 1425 groups = "RMII1"; 1426 }; 1427 1428 pinctrl_rmii2_default: rmii2_default { 1429 function = "RMII2"; 1430 groups = "RMII2"; 1431 }; 1432 1433 pinctrl_rmii3_default: rmii3_default { 1434 function = "RMII3"; 1435 groups = "RMII3"; 1436 }; 1437 1438 pinctrl_rmii4_default: rmii4_default { 1439 function = "RMII4"; 1440 groups = "RMII4"; 1441 }; 1442 1443 pinctrl_rmii1rclk_default: rmii1rclk_default { 1444 function = "RMII1RCLK"; 1445 groups = "RMII1RCLK"; 1446 }; 1447 1448 pinctrl_rmii2rclk_default: rmii2rclk_default { 1449 function = "RMII2RCLK"; 1450 groups = "RMII2RCLK"; 1451 }; 1452 1453 pinctrl_rmii3rclk_default: rmii3rclk_default { 1454 function = "RMII3RCLK"; 1455 groups = "RMII3RCLK"; 1456 }; 1457 1458 pinctrl_rmii4rclk_default: rmii4rclk_default { 1459 function = "RMII4RCLK"; 1460 groups = "RMII4RCLK"; 1461 }; 1462 1463 pinctrl_ncts1_default: ncts1_default { 1464 function = "NCTS1"; 1465 groups = "NCTS1"; 1466 }; 1467 1468 pinctrl_ncts2_default: ncts2_default { 1469 function = "NCTS2"; 1470 groups = "NCTS2"; 1471 }; 1472 1473 pinctrl_ncts3_default: ncts3_default { 1474 function = "NCTS3"; 1475 groups = "NCTS3"; 1476 }; 1477 1478 pinctrl_ncts4_default: ncts4_default { 1479 function = "NCTS4"; 1480 groups = "NCTS4"; 1481 }; 1482 1483 pinctrl_ndcd1_default: ndcd1_default { 1484 function = "NDCD1"; 1485 groups = "NDCD1"; 1486 }; 1487 1488 pinctrl_ndcd2_default: ndcd2_default { 1489 function = "NDCD2"; 1490 groups = "NDCD2"; 1491 }; 1492 1493 pinctrl_ndcd3_default: ndcd3_default { 1494 function = "NDCD3"; 1495 groups = "NDCD3"; 1496 }; 1497 1498 pinctrl_ndcd4_default: ndcd4_default { 1499 function = "NDCD4"; 1500 groups = "NDCD4"; 1501 }; 1502 1503 pinctrl_ndsr1_default: ndsr1_default { 1504 function = "NDSR1"; 1505 groups = "NDSR1"; 1506 }; 1507 1508 pinctrl_ndsr2_default: ndsr2_default { 1509 function = "NDSR2"; 1510 groups = "NDSR2"; 1511 }; 1512 1513 pinctrl_ndsr3_default: ndsr3_default { 1514 function = "NDSR3"; 1515 groups = "NDSR3"; 1516 }; 1517 1518 pinctrl_ndsr4_default: ndsr4_default { 1519 function = "NDSR4"; 1520 groups = "NDSR4"; 1521 }; 1522 1523 pinctrl_ndtr1_default: ndtr1_default { 1524 function = "NDTR1"; 1525 groups = "NDTR1"; 1526 }; 1527 1528 pinctrl_ndtr2_default: ndtr2_default { 1529 function = "NDTR2"; 1530 groups = "NDTR2"; 1531 }; 1532 1533 pinctrl_ndtr3_default: ndtr3_default { 1534 function = "NDTR3"; 1535 groups = "NDTR3"; 1536 }; 1537 1538 pinctrl_ndtr4_default: ndtr4_default { 1539 function = "NDTR4"; 1540 groups = "NDTR4"; 1541 }; 1542 1543 pinctrl_nri1_default: nri1_default { 1544 function = "NRI1"; 1545 groups = "NRI1"; 1546 }; 1547 1548 pinctrl_nri2_default: nri2_default { 1549 function = "NRI2"; 1550 groups = "NRI2"; 1551 }; 1552 1553 pinctrl_nri3_default: nri3_default { 1554 function = "NRI3"; 1555 groups = "NRI3"; 1556 }; 1557 1558 pinctrl_nri4_default: nri4_default { 1559 function = "NRI4"; 1560 groups = "NRI4"; 1561 }; 1562 1563 pinctrl_nrts1_default: nrts1_default { 1564 function = "NRTS1"; 1565 groups = "NRTS1"; 1566 }; 1567 1568 pinctrl_nrts2_default: nrts2_default { 1569 function = "NRTS2"; 1570 groups = "NRTS2"; 1571 }; 1572 1573 pinctrl_nrts3_default: nrts3_default { 1574 function = "NRTS3"; 1575 groups = "NRTS3"; 1576 }; 1577 1578 pinctrl_nrts4_default: nrts4_default { 1579 function = "NRTS4"; 1580 groups = "NRTS4"; 1581 }; 1582 1583 pinctrl_oscclk_default: oscclk_default { 1584 function = "OSCCLK"; 1585 groups = "OSCCLK"; 1586 }; 1587 1588 pinctrl_pewake_default: pewake_default { 1589 function = "PEWAKE"; 1590 groups = "PEWAKE"; 1591 }; 1592 1593 pinctrl_pnor_default: pnor_default { 1594 function = "PNOR"; 1595 groups = "PNOR"; 1596 }; 1597 1598 pinctrl_pwm0_default: pwm0_default { 1599 function = "PWM0"; 1600 groups = "PWM0"; 1601 }; 1602 1603 pinctrl_pwm1_default: pwm1_default { 1604 function = "PWM1"; 1605 groups = "PWM1"; 1606 }; 1607 1608 pinctrl_pwm2_default: pwm2_default { 1609 function = "PWM2"; 1610 groups = "PWM2"; 1611 }; 1612 1613 pinctrl_pwm3_default: pwm3_default { 1614 function = "PWM3"; 1615 groups = "PWM3"; 1616 }; 1617 1618 pinctrl_pwm4_default: pwm4_default { 1619 function = "PWM4"; 1620 groups = "PWM4"; 1621 }; 1622 1623 pinctrl_pwm5_default: pwm5_default { 1624 function = "PWM5"; 1625 groups = "PWM5"; 1626 }; 1627 1628 pinctrl_pwm6_default: pwm6_default { 1629 function = "PWM6"; 1630 groups = "PWM6"; 1631 }; 1632 1633 pinctrl_pwm7_default: pwm7_default { 1634 function = "PWM7"; 1635 groups = "PWM7"; 1636 }; 1637 1638 pinctrl_rgmii1_default: rgmii1_default { 1639 function = "RGMII1"; 1640 groups = "RGMII1"; 1641 }; 1642 1643 pinctrl_rgmii2_default: rgmii2_default { 1644 function = "RGMII2"; 1645 groups = "RGMII2"; 1646 }; 1647 1648 pinctrl_rgmii3_default: rgmii3_default { 1649 function = "RGMII3"; 1650 groups = "RGMII3"; 1651 }; 1652 1653 pinctrl_rgmii4_default: rgmii4_default { 1654 function = "RGMII4"; 1655 groups = "RGMII4"; 1656 }; 1657 1658 pinctrl_rmii1_default: rmii1_default { 1659 function = "RMII1"; 1660 groups = "RMII1"; 1661 }; 1662 1663 pinctrl_rmii2_default: rmii2_default { 1664 function = "RMII2"; 1665 groups = "RMII2"; 1666 }; 1667 1668 pinctrl_rxd1_default: rxd1_default { 1669 function = "RXD1"; 1670 groups = "RXD1"; 1671 u-boot,dm-pre-reloc; 1672 }; 1673 1674 pinctrl_rxd2_default: rxd2_default { 1675 function = "RXD2"; 1676 groups = "RXD2"; 1677 u-boot,dm-pre-reloc; 1678 }; 1679 1680 pinctrl_rxd3_default: rxd3_default { 1681 function = "RXD3"; 1682 groups = "RXD3"; 1683 u-boot,dm-pre-reloc; 1684 }; 1685 1686 pinctrl_rxd4_default: rxd4_default { 1687 function = "RXD4"; 1688 groups = "RXD4"; 1689 u-boot,dm-pre-reloc; 1690 }; 1691 1692 pinctrl_salt1_default: salt1_default { 1693 function = "SALT1"; 1694 groups = "SALT1"; 1695 }; 1696 1697 pinctrl_salt10_default: salt10_default { 1698 function = "SALT10"; 1699 groups = "SALT10"; 1700 }; 1701 1702 pinctrl_salt11_default: salt11_default { 1703 function = "SALT11"; 1704 groups = "SALT11"; 1705 }; 1706 1707 pinctrl_salt12_default: salt12_default { 1708 function = "SALT12"; 1709 groups = "SALT12"; 1710 }; 1711 1712 pinctrl_salt13_default: salt13_default { 1713 function = "SALT13"; 1714 groups = "SALT13"; 1715 }; 1716 1717 pinctrl_salt14_default: salt14_default { 1718 function = "SALT14"; 1719 groups = "SALT14"; 1720 }; 1721 1722 pinctrl_salt2_default: salt2_default { 1723 function = "SALT2"; 1724 groups = "SALT2"; 1725 }; 1726 1727 pinctrl_salt3_default: salt3_default { 1728 function = "SALT3"; 1729 groups = "SALT3"; 1730 }; 1731 1732 pinctrl_salt4_default: salt4_default { 1733 function = "SALT4"; 1734 groups = "SALT4"; 1735 }; 1736 1737 pinctrl_salt5_default: salt5_default { 1738 function = "SALT5"; 1739 groups = "SALT5"; 1740 }; 1741 1742 pinctrl_salt6_default: salt6_default { 1743 function = "SALT6"; 1744 groups = "SALT6"; 1745 }; 1746 1747 pinctrl_salt7_default: salt7_default { 1748 function = "SALT7"; 1749 groups = "SALT7"; 1750 }; 1751 1752 pinctrl_salt8_default: salt8_default { 1753 function = "SALT8"; 1754 groups = "SALT8"; 1755 }; 1756 1757 pinctrl_salt9_default: salt9_default { 1758 function = "SALT9"; 1759 groups = "SALT9"; 1760 }; 1761 1762 pinctrl_scl1_default: scl1_default { 1763 function = "SCL1"; 1764 groups = "SCL1"; 1765 }; 1766 1767 pinctrl_scl2_default: scl2_default { 1768 function = "SCL2"; 1769 groups = "SCL2"; 1770 }; 1771 1772 pinctrl_sd1_default: sd1_default { 1773 function = "SD1"; 1774 groups = "SD1"; 1775 }; 1776 1777 pinctrl_sd2_default: sd2_default { 1778 function = "SD2"; 1779 groups = "SD2"; 1780 }; 1781 1782 pinctrl_emmc_default: emmc_default { 1783 function = "EMMC"; 1784 groups = "EMMC"; 1785 }; 1786 1787 pinctrl_emmcg8_default: emmcg8_default { 1788 function = "EMMCG8"; 1789 groups = "EMMCG8"; 1790 }; 1791 1792 pinctrl_sda1_default: sda1_default { 1793 function = "SDA1"; 1794 groups = "SDA1"; 1795 }; 1796 1797 pinctrl_sda2_default: sda2_default { 1798 function = "SDA2"; 1799 groups = "SDA2"; 1800 }; 1801 1802 pinctrl_sgps1_default: sgps1_default { 1803 function = "SGPS1"; 1804 groups = "SGPS1"; 1805 }; 1806 1807 pinctrl_sgps2_default: sgps2_default { 1808 function = "SGPS2"; 1809 groups = "SGPS2"; 1810 }; 1811 1812 pinctrl_sioonctrl_default: sioonctrl_default { 1813 function = "SIOONCTRL"; 1814 groups = "SIOONCTRL"; 1815 }; 1816 1817 pinctrl_siopbi_default: siopbi_default { 1818 function = "SIOPBI"; 1819 groups = "SIOPBI"; 1820 }; 1821 1822 pinctrl_siopbo_default: siopbo_default { 1823 function = "SIOPBO"; 1824 groups = "SIOPBO"; 1825 }; 1826 1827 pinctrl_siopwreq_default: siopwreq_default { 1828 function = "SIOPWREQ"; 1829 groups = "SIOPWREQ"; 1830 }; 1831 1832 pinctrl_siopwrgd_default: siopwrgd_default { 1833 function = "SIOPWRGD"; 1834 groups = "SIOPWRGD"; 1835 }; 1836 1837 pinctrl_sios3_default: sios3_default { 1838 function = "SIOS3"; 1839 groups = "SIOS3"; 1840 }; 1841 1842 pinctrl_sios5_default: sios5_default { 1843 function = "SIOS5"; 1844 groups = "SIOS5"; 1845 }; 1846 1847 pinctrl_siosci_default: siosci_default { 1848 function = "SIOSCI"; 1849 groups = "SIOSCI"; 1850 }; 1851 1852 pinctrl_spi1_default: spi1_default { 1853 function = "SPI1"; 1854 groups = "SPI1"; 1855 }; 1856 1857 pinctrl_spi1cs1_default: spi1cs1_default { 1858 function = "SPI1CS1"; 1859 groups = "SPI1CS1"; 1860 }; 1861 1862 pinctrl_spi1debug_default: spi1debug_default { 1863 function = "SPI1DEBUG"; 1864 groups = "SPI1DEBUG"; 1865 }; 1866 1867 pinctrl_spi1passthru_default: spi1passthru_default { 1868 function = "SPI1PASSTHRU"; 1869 groups = "SPI1PASSTHRU"; 1870 }; 1871 1872 pinctrl_spi2ck_default: spi2ck_default { 1873 function = "SPI2CK"; 1874 groups = "SPI2CK"; 1875 }; 1876 1877 pinctrl_spi2cs0_default: spi2cs0_default { 1878 function = "SPI2CS0"; 1879 groups = "SPI2CS0"; 1880 }; 1881 1882 pinctrl_spi2cs1_default: spi2cs1_default { 1883 function = "SPI2CS1"; 1884 groups = "SPI2CS1"; 1885 }; 1886 1887 pinctrl_spi2miso_default: spi2miso_default { 1888 function = "SPI2MISO"; 1889 groups = "SPI2MISO"; 1890 }; 1891 1892 pinctrl_spi2mosi_default: spi2mosi_default { 1893 function = "SPI2MOSI"; 1894 groups = "SPI2MOSI"; 1895 }; 1896 1897 pinctrl_timer3_default: timer3_default { 1898 function = "TIMER3"; 1899 groups = "TIMER3"; 1900 }; 1901 1902 pinctrl_timer4_default: timer4_default { 1903 function = "TIMER4"; 1904 groups = "TIMER4"; 1905 }; 1906 1907 pinctrl_timer5_default: timer5_default { 1908 function = "TIMER5"; 1909 groups = "TIMER5"; 1910 }; 1911 1912 pinctrl_timer6_default: timer6_default { 1913 function = "TIMER6"; 1914 groups = "TIMER6"; 1915 }; 1916 1917 pinctrl_timer7_default: timer7_default { 1918 function = "TIMER7"; 1919 groups = "TIMER7"; 1920 }; 1921 1922 pinctrl_timer8_default: timer8_default { 1923 function = "TIMER8"; 1924 groups = "TIMER8"; 1925 }; 1926 1927 pinctrl_txd1_default: txd1_default { 1928 function = "TXD1"; 1929 groups = "TXD1"; 1930 u-boot,dm-pre-reloc; 1931 }; 1932 1933 pinctrl_txd2_default: txd2_default { 1934 function = "TXD2"; 1935 groups = "TXD2"; 1936 u-boot,dm-pre-reloc; 1937 }; 1938 1939 pinctrl_txd3_default: txd3_default { 1940 function = "TXD3"; 1941 groups = "TXD3"; 1942 u-boot,dm-pre-reloc; 1943 }; 1944 1945 pinctrl_txd4_default: txd4_default { 1946 function = "TXD4"; 1947 groups = "TXD4"; 1948 u-boot,dm-pre-reloc; 1949 }; 1950 1951 pinctrl_uart6_default: uart6_default { 1952 function = "UART6"; 1953 groups = "UART6"; 1954 }; 1955 1956 pinctrl_usbcki_default: usbcki_default { 1957 function = "USBCKI"; 1958 groups = "USBCKI"; 1959 }; 1960 1961 pinctrl_usb2ad_default: usb2ad_default { 1962 function = "USB2AD"; 1963 groups = "USB2AD"; 1964 }; 1965 1966 pinctrl_usb2ah_default: usb2ah_default { 1967 function = "USB2AH"; 1968 groups = "USB2AH"; 1969 }; 1970 1971 pinctrl_usb11bhid_default: usb11bhid_default { 1972 function = "USB11BHID"; 1973 groups = "USB11BHID"; 1974 }; 1975 1976 pinctrl_usb2bh_default: usb2bh_default { 1977 function = "USB2BH"; 1978 groups = "USB2BH"; 1979 }; 1980 1981 pinctrl_vgabiosrom_default: vgabiosrom_default { 1982 function = "VGABIOSROM"; 1983 groups = "VGABIOSROM"; 1984 }; 1985 1986 pinctrl_vgahs_default: vgahs_default { 1987 function = "VGAHS"; 1988 groups = "VGAHS"; 1989 }; 1990 1991 pinctrl_vgavs_default: vgavs_default { 1992 function = "VGAVS"; 1993 groups = "VGAVS"; 1994 }; 1995 1996 pinctrl_vpi24_default: vpi24_default { 1997 function = "VPI24"; 1998 groups = "VPI24"; 1999 }; 2000 2001 pinctrl_vpo_default: vpo_default { 2002 function = "VPO"; 2003 groups = "VPO"; 2004 }; 2005 2006 pinctrl_wdtrst1_default: wdtrst1_default { 2007 function = "WDTRST1"; 2008 groups = "WDTRST1"; 2009 }; 2010 2011 pinctrl_wdtrst2_default: wdtrst2_default { 2012 function = "WDTRST2"; 2013 groups = "WDTRST2"; 2014 }; 2015 2016 pinctrl_pcie0rc_default: pcie0rc_default { 2017 function = "PCIE0RC"; 2018 groups = "PCIE0RC"; 2019 }; 2020 2021 pinctrl_pcie1rc_default: pcie1rc_default { 2022 function = "PCIE1RC"; 2023 groups = "PCIE1RC"; 2024 }; 2025}; 2026