1// SPDX-License-Identifier: GPL-2.0+ 2#include <dt-bindings/interrupt-controller/arm-gic.h> 3#include <dt-bindings/gpio/aspeed-gpio.h> 4#include "skeleton.dtsi" 5 6/ { 7 model = "Aspeed BMC"; 8 compatible = "aspeed,ast2600"; 9 #address-cells = <1>; 10 #size-cells = <1>; 11 interrupt-parent = <&gic>; 12 13 aliases { 14 i2c0 = &i2c0; 15 i2c1 = &i2c1; 16 i2c2 = &i2c2; 17 i2c3 = &i2c3; 18 i2c4 = &i2c4; 19 i2c5 = &i2c5; 20 i2c6 = &i2c6; 21 i2c7 = &i2c7; 22 i2c8 = &i2c8; 23 i2c9 = &i2c9; 24 i2c10 = &i2c10; 25 i2c11 = &i2c11; 26 i2c12 = &i2c12; 27 i2c13 = &i2c13; 28 i2c14 = &i2c14; 29 i2c15 = &i2c15; 30 serial0 = &uart1; 31 serial1 = &uart2; 32 serial2 = &uart3; 33 serial3 = &uart4; 34 serial4 = &uart5; 35 serial5 = &uart6; 36 serial6 = &uart7; 37 serial7 = &uart8; 38 serial8 = &uart9; 39 serial9 = &uart10; 40 serial10 = &uart11; 41 serial11 = &uart12; 42 serial12 = &uart13; 43 }; 44 45 cpus { 46 #address-cells = <1>; 47 #size-cells = <0>; 48 enable-method = "aspeed,ast2600-smp"; 49 50 cpu@0 { 51 compatible = "arm,cortex-a7"; 52 device_type = "cpu"; 53 reg = <0>; 54 }; 55 56 cpu@1 { 57 compatible = "arm,cortex-a7"; 58 device_type = "cpu"; 59 reg = <1>; 60 }; 61 62 }; 63 64 timer { 65 compatible = "arm,armv7-timer"; 66 interrupt-parent = <&gic>; 67 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 68 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 69 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 70 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 71 }; 72 73 reserved-memory { 74 #address-cells = <1>; 75 #size-cells = <1>; 76 ranges; 77 78 gfx_memory: framebuffer { 79 size = <0x01000000>; 80 alignment = <0x01000000>; 81 compatible = "shared-dma-pool"; 82 reusable; 83 }; 84 85 video_memory: video { 86 size = <0x04000000>; 87 alignment = <0x01000000>; 88 compatible = "shared-dma-pool"; 89 no-map; 90 }; 91 }; 92 93 ahb { 94 compatible = "simple-bus"; 95 #address-cells = <1>; 96 #size-cells = <1>; 97 device_type = "soc"; 98 ranges; 99 100 gic: interrupt-controller@40461000 { 101 compatible = "arm,cortex-a7-gic"; 102 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 103 #interrupt-cells = <3>; 104 interrupt-controller; 105 interrupt-parent = <&gic>; 106 reg = <0x40461000 0x1000>, 107 <0x40462000 0x1000>, 108 <0x40464000 0x2000>, 109 <0x40466000 0x2000>; 110 }; 111 112 ahbc: ahbc@1e600000 { 113 compatible = "aspeed,aspeed-ahbc"; 114 reg = < 0x1e600000 0x100>; 115 }; 116 117 fmc: flash-controller@1e620000 { 118 reg = < 0x1e620000 0xc4 119 0x20000000 0x10000000 >; 120 #address-cells = <1>; 121 #size-cells = <0>; 122 compatible = "aspeed,ast2600-fmc"; 123 status = "disabled"; 124 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 125 clocks = <&scu ASPEED_CLK_AHB>; 126 num-cs = <3>; 127 flash@0 { 128 reg = < 0 >; 129 compatible = "jedec,spi-nor"; 130 status = "disabled"; 131 }; 132 flash@1 { 133 reg = < 1 >; 134 compatible = "jedec,spi-nor"; 135 status = "disabled"; 136 }; 137 flash@2 { 138 reg = < 2 >; 139 compatible = "jedec,spi-nor"; 140 status = "disabled"; 141 }; 142 }; 143 144 spi1: flash-controller@1e630000 { 145 reg = < 0x1e630000 0xc4 146 0x30000000 0x08000000 >; 147 #address-cells = <1>; 148 #size-cells = <0>; 149 compatible = "aspeed,ast2600-spi"; 150 clocks = <&scu ASPEED_CLK_AHB>; 151 num-cs = <2>; 152 status = "disabled"; 153 flash@0 { 154 reg = < 0 >; 155 compatible = "jedec,spi-nor"; 156 status = "disabled"; 157 }; 158 flash@1 { 159 reg = < 1 >; 160 compatible = "jedec,spi-nor"; 161 status = "disabled"; 162 }; 163 }; 164 165 spi2: flash-controller@1e631000 { 166 reg = < 0x1e631000 0xc4 167 0x50000000 0x08000000 >; 168 #address-cells = <1>; 169 #size-cells = <0>; 170 compatible = "aspeed,ast2600-spi"; 171 clocks = <&scu ASPEED_CLK_AHB>; 172 num-cs = <3>; 173 status = "disabled"; 174 flash@0 { 175 reg = < 0 >; 176 compatible = "jedec,spi-nor"; 177 status = "disabled"; 178 }; 179 flash@1 { 180 reg = < 1 >; 181 compatible = "jedec,spi-nor"; 182 status = "disabled"; 183 }; 184 flash@2 { 185 reg = < 2 >; 186 compatible = "jedec,spi-nor"; 187 status = "disabled"; 188 }; 189 }; 190 191 edac: sdram@1e6e0000 { 192 compatible = "aspeed,ast2600-sdram-edac"; 193 reg = <0x1e6e0000 0x174>; 194 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 195 }; 196 197 mdio: ethernet@1e650000 { 198 compatible = "aspeed,aspeed-mdio"; 199 reg = <0x1e650000 0x40>; 200 resets = <&rst ASPEED_RESET_MII>; 201 status = "disabled"; 202 }; 203 204 mac0: ftgmac@1e660000 { 205 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 206 reg = <0x1e660000 0x180>, <0x1e650000 0x4>; 207 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 208 clocks = <&scu ASPEED_CLK_GATE_MAC1CLK>; 209 status = "disabled"; 210 }; 211 212 mac1: ftgmac@1e680000 { 213 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 214 reg = <0x1e680000 0x180>, <0x1e650008 0x4>; 215 #address-cells = <1>; 216 #size-cells = <0>; 217 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 218 clocks = <&scu ASPEED_CLK_GATE_MAC2CLK>; 219 status = "disabled"; 220 }; 221 222 mac2: ftgmac@1e670000 { 223 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 224 reg = <0x1e670000 0x180>, <0x1e650010 0x4>; 225 #address-cells = <1>; 226 #size-cells = <0>; 227 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 228 clocks = <&scu ASPEED_CLK_GATE_MAC3CLK>; 229 status = "disabled"; 230 }; 231 232 mac3: ftgmac@1e690000 { 233 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 234 reg = <0x1e690000 0x180>, <0x1e650018 0x4>; 235 #address-cells = <1>; 236 #size-cells = <0>; 237 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 238 clocks = <&scu ASPEED_CLK_GATE_MAC4CLK>; 239 status = "disabled"; 240 }; 241 242 ehci0: usb@1e6a1000 { 243 compatible = "aspeed,aspeed-ehci", "usb-ehci"; 244 reg = <0x1e6a1000 0x100>; 245 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 246 clocks = <&scu ASPEED_CLK_GATE_USBPORT1CLK>; 247 pinctrl-names = "default"; 248 pinctrl-0 = <&pinctrl_usb2ah_default>; 249 status = "disabled"; 250 }; 251 252 ehci1: usb@1e6a3000 { 253 compatible = "aspeed,aspeed-ehci", "usb-ehci"; 254 reg = <0x1e6a3000 0x100>; 255 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 256 clocks = <&scu ASPEED_CLK_GATE_USBPORT2CLK>; 257 pinctrl-names = "default"; 258 pinctrl-0 = <&pinctrl_usb2bh_default>; 259 status = "disabled"; 260 }; 261 262 apb { 263 compatible = "simple-bus"; 264 #address-cells = <1>; 265 #size-cells = <1>; 266 ranges; 267 268 syscon: syscon@1e6e2000 { 269 compatible = "aspeed,g6-scu", "syscon", "simple-mfd"; 270 reg = <0x1e6e2000 0x1000>; 271 #address-cells = <1>; 272 #size-cells = <1>; 273 #clock-cells = <1>; 274 #reset-cells = <1>; 275 ranges = <0 0x1e6e2000 0x1000>; 276 277 pinctrl: pinctrl { 278 compatible = "aspeed,g6-pinctrl"; 279 aspeed,external-nodes = <&gfx &lhc>; 280 281 }; 282 283 vga_scratch: scratch { 284 compatible = "aspeed,bmc-misc"; 285 }; 286 287 scu_ic0: interrupt-controller@0 { 288 #interrupt-cells = <1>; 289 compatible = "aspeed,ast2600-scu-ic"; 290 reg = <0x560 0x10>; 291 interrupt-parent = <&gic>; 292 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 293 interrupt-controller; 294 }; 295 296 scu_ic1: interrupt-controller@1 { 297 #interrupt-cells = <1>; 298 compatible = "aspeed,ast2600-scu-ic"; 299 reg = <0x570 0x10>; 300 interrupt-parent = <&gic>; 301 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 302 interrupt-controller; 303 }; 304 305 }; 306 307 hace: hace@1e6d0000 { 308 compatible = "aspeed,ast2600-hace"; 309 reg = <0x1e6d0000 0x200>; 310 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 311 clocks = <&scu ASPEED_CLK_GATE_YCLK>; 312 clock-names = "yclk"; 313 status = "disabled"; 314 }; 315 316 smp-memram@0 { 317 compatible = "aspeed,ast2600-smpmem", "syscon"; 318 reg = <0x1e6e2180 0x40>; 319 }; 320 321 gfx: display@1e6e6000 { 322 compatible = "aspeed,ast2500-gfx", "syscon"; 323 reg = <0x1e6e6000 0x1000>; 324 reg-io-width = <4>; 325 }; 326 327 pcie_bridge0: pcie@1e6ed000 { 328 compatible = "aspeed,ast2600-pcie"; 329 #address-cells = <3>; 330 #size-cells = <2>; 331 reg = <0x1e6ed000 0x100>; 332 ranges = <0x81000000 0x0 0x0 0x0 0x0 0x10000 /* downstream I/O */ 333 0x82000000 0x0 0x60000000 0x60000000 0x0 0x10000000>; /* non-prefetchable memory */ 334 device_type = "pci"; 335 bus-range = <0x00 0xff>; 336 resets = <&rst ASPEED_RESET_PCIE_DEV_O>; 337 cfg-handle = <&pcie_cfg0>; 338 pinctrl-names = "default"; 339 pinctrl-0 = <&pinctrl_pcie0rc_default>; 340 341 status = "disabled"; 342 }; 343 344 pcie_bridge1: pcie@1e6ed200 { 345 compatible = "aspeed,ast2600-pcie"; 346 #address-cells = <3>; 347 #size-cells = <2>; 348 reg = <0x1e6ed200 0x100>; 349 ranges = <0x81000000 0x0 0x0 0x10000 0x00 0x10000 /* downstream I/O */ 350 0x82000000 0x0 0x70000000 0x70000000 0x0 0x10000000>; /* non-prefetchable memory */ 351 device_type = "pci"; 352 bus-range = <0x00 0xff>; 353 resets = <&rst ASPEED_RESET_PCIE_RC_O>; 354 cfg-handle = <&pcie_cfg1>; 355 pinctrl-names = "default"; 356 pinctrl-0 = <&pinctrl_pcie1rc_default>; 357 358 status = "disabled"; 359 }; 360 361 sdhci: sdhci@1e740000 { 362 #interrupt-cells = <1>; 363 compatible = "aspeed,aspeed-sdhci-irq", "simple-mfd"; 364 reg = <0x1e740000 0x1000>; 365 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 366 interrupt-controller; 367 clocks = <&scu ASPEED_CLK_GATE_SDCLK>, <&scu ASPEED_CLK_GATE_SDEXTCLK>; 368 clock-names = "ctrlclk", "extclk"; 369 #address-cells = <1>; 370 #size-cells = <1>; 371 ranges = <0x0 0x1e740000 0x1000>; 372 373 sdhci_slot0: sdhci_slot0@100 { 374 compatible = "aspeed,sdhci-ast2600"; 375 reg = <0x100 0x100>; 376 interrupts = <0>; 377 interrupt-parent = <&sdhci>; 378 sdhci,auto-cmd12; 379 clocks = <&scu ASPEED_CLK_SDIO>; 380 status = "disabled"; 381 }; 382 383 sdhci_slot1: sdhci_slot1@200 { 384 compatible = "aspeed,sdhci-ast2600"; 385 reg = <0x200 0x100>; 386 interrupts = <1>; 387 interrupt-parent = <&sdhci>; 388 sdhci,auto-cmd12; 389 clocks = <&scu ASPEED_CLK_SDIO>; 390 status = "disabled"; 391 }; 392 }; 393 394 emmc: emmc@1e750000 { 395 #interrupt-cells = <1>; 396 compatible = "aspeed,aspeed-emmc-irq", "simple-mfd"; 397 reg = <0x1e750000 0x1000>; 398 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 399 interrupt-controller; 400 clocks = <&scu ASPEED_CLK_GATE_EMMCCLK>, <&scu ASPEED_CLK_GATE_EMMCEXTCLK>; 401 clock-names = "ctrlclk", "extclk"; 402 #address-cells = <1>; 403 #size-cells = <1>; 404 ranges = <0x0 0x1e750000 0x1000>; 405 406 emmc_slot0: emmc_slot0@100 { 407 compatible = "aspeed,emmc-ast2600"; 408 reg = <0x100 0x100>; 409 interrupts = <0>; 410 interrupt-parent = <&emmc>; 411 clocks = <&scu ASPEED_CLK_EMMC>; 412 status = "disabled"; 413 }; 414 }; 415 416 h2x: h2x@1e770000 { 417 compatible = "aspeed,ast2600-h2x"; 418 reg = <0x1e770000 0x100>; 419 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 420 resets = <&rst ASPEED_RESET_H2X>; 421 #address-cells = <1>; 422 #size-cells = <1>; 423 ranges = <0x0 0x1e770000 0x100>; 424 425 status = "disabled"; 426 427 pcie_cfg0: cfg0@80 { 428 reg = <0x80 0x80>; 429 compatible = "aspeed,ast2600-pcie-cfg"; 430 }; 431 432 pcie_cfg1: cfg1@C0 { 433 compatible = "aspeed,ast2600-pcie-cfg"; 434 reg = <0xC0 0x80>; 435 }; 436 }; 437 438 gpio0: gpio@1e780000 { 439 compatible = "aspeed,ast2600-gpio"; 440 reg = <0x1e780000 0x400>; 441 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 442 #gpio-cells = <2>; 443 gpio-controller; 444 interrupt-controller; 445 gpio-ranges = <&pinctrl 0 0 208>; 446 ngpios = <208>; 447 }; 448 449 gpio1: gpio@1e780800 { 450 compatible = "aspeed,ast2600-gpio"; 451 reg = <0x1e780800 0x800>; 452 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 453 #gpio-cells = <2>; 454 gpio-controller; 455 interrupt-controller; 456 gpio-ranges = <&pinctrl 0 208 36>; 457 ngpios = <36>; 458 }; 459 460 uart1: serial@1e783000 { 461 compatible = "ns16550a"; 462 reg = <0x1e783000 0x20>; 463 reg-shift = <2>; 464 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 465 clocks = <&scu ASPEED_CLK_GATE_UART1CLK>; 466 clock-frequency = <1846154>; 467 no-loopback-test; 468 status = "disabled"; 469 }; 470 471 uart5: serial@1e784000 { 472 compatible = "ns16550a"; 473 reg = <0x1e784000 0x1000>; 474 reg-shift = <2>; 475 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 476 clocks = <&scu ASPEED_CLK_GATE_UART5CLK>; 477 clock-frequency = <1846154>; 478 no-loopback-test; 479 status = "disabled"; 480 }; 481 482 wdt1: watchdog@1e785000 { 483 compatible = "aspeed,ast2600-wdt"; 484 reg = <0x1e785000 0x40>; 485 }; 486 487 wdt2: watchdog@1e785040 { 488 compatible = "aspeed,ast2600-wdt"; 489 reg = <0x1e785040 0x40>; 490 }; 491 492 wdt3: watchdog@1e785080 { 493 compatible = "aspeed,ast2600-wdt"; 494 reg = <0x1e785080 0x40>; 495 }; 496 497 wdt4: watchdog@1e7850C0 { 498 compatible = "aspeed,ast2600-wdt"; 499 reg = <0x1e7850C0 0x40>; 500 }; 501 502 lpc: lpc@1e789000 { 503 compatible = "aspeed,ast-lpc", "simple-mfd", "syscon"; 504 reg = <0x1e789000 0x200>; 505 506 #address-cells = <1>; 507 #size-cells = <1>; 508 ranges = <0x0 0x1e789000 0x1000>; 509 510 lpc_bmc: lpc-bmc@0 { 511 compatible = "aspeed,ast2600-lpc-bmc", "simple-mfd", "syscon"; 512 reg = <0x0 0x80>; 513 reg-io-width = <4>; 514 #address-cells = <1>; 515 #size-cells = <1>; 516 ranges = <0x0 0x0 0x80>; 517 518 kcs1: kcs1@0 { 519 compatible = "aspeed,ast2600-kcs-bmc"; 520 reg = <0x0 0x80>; 521 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 522 kcs_chan = <1>; 523 kcs_addr = <0xCA0>; 524 status = "disabled"; 525 }; 526 527 kcs2: kcs2@0 { 528 compatible = "aspeed,ast2600-kcs-bmc"; 529 reg = <0x0 0x80>; 530 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 531 kcs_chan = <2>; 532 kcs_addr = <0xCA8>; 533 status = "disabled"; 534 }; 535 536 kcs3: kcs3@0 { 537 compatible = "aspeed,ast2600-kcs-bmc"; 538 reg = <0x0 0x80>; 539 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 540 kcs_chan = <3>; 541 kcs_addr = <0xCA2>; 542 }; 543 544 kcs4: kcs4@0 { 545 compatible = "aspeed,ast2600-kcs-bmc"; 546 reg = <0x0 0x120>; 547 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 548 kcs_chan = <4>; 549 kcs_addr = <0xCA4>; 550 status = "disabled"; 551 }; 552 553 }; 554 555 lpc_host: lpc-host@80 { 556 compatible = "aspeed,ast2600-lpc-host", "simple-mfd", "syscon"; 557 reg = <0x80 0x1e0>; 558 reg-io-width = <4>; 559 560 #address-cells = <1>; 561 #size-cells = <1>; 562 ranges = <0x0 0x80 0x1e0>; 563 564 lpc_ctrl: lpc-ctrl@0 { 565 compatible = "aspeed,ast2600-lpc-ctrl"; 566 reg = <0x0 0x80>; 567 status = "disabled"; 568 }; 569 570 lpc_snoop: lpc-snoop@0 { 571 compatible = "aspeed,ast2600-lpc-snoop"; 572 reg = <0x0 0x80>; 573 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 574 snoop-ports = <0x80>; 575 status = "disabled"; 576 }; 577 578 lhc: lhc@20 { 579 compatible = "aspeed,ast2600-lhc"; 580 reg = <0x20 0x24 0x48 0x8>; 581 }; 582 583 lpc_reset: reset-controller@18 { 584 compatible = "aspeed,ast2600-lpc-reset"; 585 reg = <0x18 0x4>; 586 #reset-cells = <1>; 587 status = "disabled"; 588 }; 589 590 ibt: ibt@c0 { 591 compatible = "aspeed,ast2600-ibt-bmc"; 592 reg = <0xc0 0x18>; 593 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 594 status = "disabled"; 595 }; 596 597 sio_regs: regs { 598 compatible = "aspeed,bmc-misc"; 599 }; 600 601 mbox: mbox@180 { 602 compatible = "aspeed,ast2600-mbox"; 603 reg = <0x180 0x5c>; 604 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 605 #mbox-cells = <1>; 606 status = "disabled"; 607 }; 608 }; 609 }; 610 611 uart2: serial@1e78d000 { 612 compatible = "ns16550a"; 613 reg = <0x1e78d000 0x20>; 614 reg-shift = <2>; 615 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 616 clocks = <&scu ASPEED_CLK_GATE_UART2CLK>; 617 clock-frequency = <1846154>; 618 no-loopback-test; 619 status = "disabled"; 620 }; 621 622 uart3: serial@1e78e000 { 623 compatible = "ns16550a"; 624 reg = <0x1e78e000 0x20>; 625 reg-shift = <2>; 626 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 627 clocks = <&scu ASPEED_CLK_GATE_UART3CLK>; 628 clock-frequency = <1846154>; 629 no-loopback-test; 630 status = "disabled"; 631 }; 632 633 uart4: serial@1e78f000 { 634 compatible = "ns16550a"; 635 reg = <0x1e78f000 0x20>; 636 reg-shift = <2>; 637 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 638 clocks = <&scu ASPEED_CLK_GATE_UART4CLK>; 639 clock-frequency = <1846154>; 640 no-loopback-test; 641 status = "disabled"; 642 }; 643 644 i2c: bus@1e78a000 { 645 compatible = "simple-bus"; 646 #address-cells = <1>; 647 #size-cells = <1>; 648 ranges = <0 0x1e78a000 0x1000>; 649 }; 650 651 fsim0: fsi@1e79b000 { 652 compatible = "aspeed,ast2600-fsi-master", "fsi-master"; 653 reg = <0x1e79b000 0x94>; 654 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 655 pinctrl-names = "default"; 656 pinctrl-0 = <&pinctrl_fsi1_default>; 657 clocks = <&scu ASPEED_CLK_GATE_FSICLK>; 658 status = "disabled"; 659 }; 660 661 fsim1: fsi@1e79b100 { 662 compatible = "aspeed,ast2600-fsi-master", "fsi-master"; 663 reg = <0x1e79b100 0x94>; 664 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 665 pinctrl-names = "default"; 666 pinctrl-0 = <&pinctrl_fsi2_default>; 667 clocks = <&scu ASPEED_CLK_GATE_FSICLK>; 668 status = "disabled"; 669 }; 670 671 uart6: serial@1e790000 { 672 compatible = "ns16550a"; 673 reg = <0x1e790000 0x20>; 674 reg-shift = <2>; 675 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 676 clocks = <&scu ASPEED_CLK_GATE_UART6CLK>; 677 clock-frequency = <1846154>; 678 no-loopback-test; 679 status = "disabled"; 680 }; 681 682 uart7: serial@1e790100 { 683 compatible = "ns16550a"; 684 reg = <0x1e790100 0x20>; 685 reg-shift = <2>; 686 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 687 clocks = <&scu ASPEED_CLK_GATE_UART7CLK>; 688 clock-frequency = <1846154>; 689 no-loopback-test; 690 status = "disabled"; 691 }; 692 693 uart8: serial@1e790200 { 694 compatible = "ns16550a"; 695 reg = <0x1e790200 0x20>; 696 reg-shift = <2>; 697 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 698 clocks = <&scu ASPEED_CLK_GATE_UART8CLK>; 699 clock-frequency = <1846154>; 700 no-loopback-test; 701 status = "disabled"; 702 }; 703 704 uart9: serial@1e790300 { 705 compatible = "ns16550a"; 706 reg = <0x1e790300 0x20>; 707 reg-shift = <2>; 708 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 709 clocks = <&scu ASPEED_CLK_GATE_UART9CLK>; 710 clock-frequency = <1846154>; 711 no-loopback-test; 712 status = "disabled"; 713 }; 714 715 uart10: serial@1e790400 { 716 compatible = "ns16550a"; 717 reg = <0x1e790400 0x20>; 718 reg-shift = <2>; 719 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 720 clocks = <&scu ASPEED_CLK_GATE_UART10CLK>; 721 clock-frequency = <1846154>; 722 no-loopback-test; 723 status = "disabled"; 724 }; 725 726 uart11: serial@1e790500 { 727 compatible = "ns16550a"; 728 reg = <0x1e790400 0x20>; 729 reg-shift = <2>; 730 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 731 clocks = <&scu ASPEED_CLK_GATE_UART11CLK>; 732 clock-frequency = <1846154>; 733 no-loopback-test; 734 status = "disabled"; 735 }; 736 737 uart12: serial@1e790600 { 738 compatible = "ns16550a"; 739 reg = <0x1e790600 0x20>; 740 reg-shift = <2>; 741 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 742 clocks = <&scu ASPEED_CLK_GATE_UART12CLK>; 743 clock-frequency = <1846154>; 744 no-loopback-test; 745 status = "disabled"; 746 }; 747 748 uart13: serial@1e790700 { 749 compatible = "ns16550a"; 750 reg = <0x1e790700 0x20>; 751 reg-shift = <2>; 752 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 753 clocks = <&scu ASPEED_CLK_GATE_UART13CLK>; 754 clock-frequency = <1846154>; 755 no-loopback-test; 756 status = "disabled"; 757 }; 758 759 display_port: dp@1e6eb000 { 760 compatible = "aspeed,ast2600-displayport"; 761 reg = <0x1e6eb000 0x200>; 762 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 763 resets = <&rst ASPEED_RESET_DP> ,<&rst ASPEED_RESET_DP_MCU>; 764 status = "disabled"; 765 }; 766 767 }; 768 769 }; 770 771}; 772 773&i2c { 774 i2cglobal: i2cg@00 { 775 compatible = "aspeed,ast2600-i2c-global"; 776 reg = <0x0 0x40>; 777 resets = <&rst ASPEED_RESET_I2C>; 778#if 0 779 new-mode; 780#endif 781 }; 782 783 i2c0: i2c@80 { 784 #address-cells = <1>; 785 #size-cells = <0>; 786 #interrupt-cells = <1>; 787 788 reg = <0x80 0x80 0xC00 0x20>; 789 compatible = "aspeed,ast2600-i2c-bus"; 790 bus-frequency = <100000>; 791 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 792 clocks = <&scu ASPEED_CLK_APB2>; 793 status = "disabled"; 794 }; 795 796 i2c1: i2c@100 { 797 #address-cells = <1>; 798 #size-cells = <0>; 799 #interrupt-cells = <1>; 800 801 reg = <0x100 0x80 0xC20 0x20>; 802 compatible = "aspeed,ast2600-i2c-bus"; 803 bus-frequency = <100000>; 804 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 805 clocks = <&scu ASPEED_CLK_APB2>; 806 status = "disabled"; 807 }; 808 809 i2c2: i2c@180 { 810 #address-cells = <1>; 811 #size-cells = <0>; 812 #interrupt-cells = <1>; 813 814 reg = <0x180 0x80 0xC40 0x20>; 815 compatible = "aspeed,ast2600-i2c-bus"; 816 bus-frequency = <100000>; 817 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 818 clocks = <&scu ASPEED_CLK_APB2>; 819 }; 820 821 i2c3: i2c@200 { 822 #address-cells = <1>; 823 #size-cells = <0>; 824 #interrupt-cells = <1>; 825 826 reg = <0x200 0x40 0xC60 0x20>; 827 compatible = "aspeed,ast2600-i2c-bus"; 828 bus-frequency = <100000>; 829 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 830 clocks = <&scu ASPEED_CLK_APB2>; 831 }; 832 833 i2c4: i2c@280 { 834 #address-cells = <1>; 835 #size-cells = <0>; 836 #interrupt-cells = <1>; 837 838 reg = <0x280 0x80 0xC80 0x20>; 839 compatible = "aspeed,ast2600-i2c-bus"; 840 bus-frequency = <100000>; 841 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 842 clocks = <&scu ASPEED_CLK_APB2>; 843 }; 844 845 i2c5: i2c@300 { 846 #address-cells = <1>; 847 #size-cells = <0>; 848 #interrupt-cells = <1>; 849 850 reg = <0x300 0x40 0xCA0 0x20>; 851 compatible = "aspeed,ast2600-i2c-bus"; 852 bus-frequency = <100000>; 853 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 854 clocks = <&scu ASPEED_CLK_APB2>; 855 }; 856 857 i2c6: i2c@380 { 858 #address-cells = <1>; 859 #size-cells = <0>; 860 #interrupt-cells = <1>; 861 862 reg = <0x380 0x80 0xCC0 0x20>; 863 compatible = "aspeed,ast2600-i2c-bus"; 864 bus-frequency = <100000>; 865 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 866 clocks = <&scu ASPEED_CLK_APB2>; 867 }; 868 869 i2c7: i2c@400 { 870 #address-cells = <1>; 871 #size-cells = <0>; 872 #interrupt-cells = <1>; 873 874 reg = <0x400 0x80 0xCE0 0x20>; 875 compatible = "aspeed,ast2600-i2c-bus"; 876 bus-frequency = <100000>; 877 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 878 clocks = <&scu ASPEED_CLK_APB2>; 879 }; 880 881 i2c8: i2c@480 { 882 #address-cells = <1>; 883 #size-cells = <0>; 884 #interrupt-cells = <1>; 885 886 reg = <0x480 0x80 0xD00 0x20>; 887 compatible = "aspeed,ast2600-i2c-bus"; 888 bus-frequency = <100000>; 889 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 890 clocks = <&scu ASPEED_CLK_APB2>; 891 }; 892 893 i2c9: i2c@500 { 894 #address-cells = <1>; 895 #size-cells = <0>; 896 #interrupt-cells = <1>; 897 898 reg = <0x500 0x80 0xD20 0x20>; 899 compatible = "aspeed,ast2600-i2c-bus"; 900 bus-frequency = <100000>; 901 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 902 clocks = <&scu ASPEED_CLK_APB2>; 903 status = "disabled"; 904 }; 905 906 i2c10: i2c@580 { 907 #address-cells = <1>; 908 #size-cells = <0>; 909 #interrupt-cells = <1>; 910 911 reg = <0x580 0x80 0xD40 0x20>; 912 compatible = "aspeed,ast2600-i2c-bus"; 913 bus-frequency = <100000>; 914 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 915 clocks = <&scu ASPEED_CLK_APB2>; 916 status = "disabled"; 917 }; 918 919 i2c11: i2c@600 { 920 #address-cells = <1>; 921 #size-cells = <0>; 922 #interrupt-cells = <1>; 923 924 reg = <0x600 0x80 0xD60 0x20>; 925 compatible = "aspeed,ast2600-i2c-bus"; 926 bus-frequency = <100000>; 927 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 928 clocks = <&scu ASPEED_CLK_APB2>; 929 status = "disabled"; 930 }; 931 932 i2c12: i2c@680 { 933 #address-cells = <1>; 934 #size-cells = <0>; 935 #interrupt-cells = <1>; 936 937 reg = <0x680 0x80 0xD80 0x20>; 938 compatible = "aspeed,ast2600-i2c-bus"; 939 bus-frequency = <100000>; 940 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 941 clocks = <&scu ASPEED_CLK_APB2>; 942 status = "disabled"; 943 }; 944 945 i2c13: i2c@700 { 946 #address-cells = <1>; 947 #size-cells = <0>; 948 #interrupt-cells = <1>; 949 950 reg = <0x700 0x80 0xDA0 0x20>; 951 compatible = "aspeed,ast2600-i2c-bus"; 952 bus-frequency = <100000>; 953 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 954 clocks = <&scu ASPEED_CLK_APB2>; 955 status = "disabled"; 956 }; 957 958 i2c14: i2c@780 { 959 #address-cells = <1>; 960 #size-cells = <0>; 961 #interrupt-cells = <1>; 962 963 reg = <0x780 0x80 0xDC0 0x20>; 964 compatible = "aspeed,ast2600-i2c-bus"; 965 bus-frequency = <100000>; 966 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 967 clocks = <&scu ASPEED_CLK_APB2>; 968 status = "disabled"; 969 }; 970 971 i2c15: i2c@800 { 972 #address-cells = <1>; 973 #size-cells = <0>; 974 #interrupt-cells = <1>; 975 976 reg = <0x800 0x80 0xDE0 0x20>; 977 compatible = "aspeed,ast2600-i2c-bus"; 978 bus-frequency = <100000>; 979 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 980 clocks = <&scu ASPEED_CLK_APB2>; 981 status = "disabled"; 982 }; 983 984}; 985 986&pinctrl { 987 pinctrl_fmcquad_default: fmcquad_default { 988 function = "FMCQUAD"; 989 groups = "FMCQUAD"; 990 }; 991 992 pinctrl_spi1_default: spi1_default { 993 function = "SPI1"; 994 groups = "SPI1"; 995 }; 996 997 pinctrl_spi1abr_default: spi1abr_default { 998 function = "SPI1ABR"; 999 groups = "SPI1ABR"; 1000 }; 1001 1002 pinctrl_spi1cs1_default: spi1cs1_default { 1003 function = "SPI1CS1"; 1004 groups = "SPI1CS1"; 1005 }; 1006 1007 pinctrl_spi1wp_default: spi1wp_default { 1008 function = "SPI1WP"; 1009 groups = "SPI1WP"; 1010 }; 1011 1012 pinctrl_spi1quad_default: spi1quad_default { 1013 function = "SPI1QUAD"; 1014 groups = "SPI1QUAD"; 1015 }; 1016 1017 pinctrl_spi2_default: spi2_default { 1018 function = "SPI2"; 1019 groups = "SPI2"; 1020 }; 1021 1022 pinctrl_spi2cs1_default: spi2cs1_default { 1023 function = "SPI2CS1"; 1024 groups = "SPI2CS1"; 1025 }; 1026 1027 pinctrl_spi2cs2_default: spi2cs2_default { 1028 function = "SPI2CS2"; 1029 groups = "SPI2CS2"; 1030 }; 1031 1032 pinctrl_spi2quad_default: spi2quad_default { 1033 function = "SPI2QUAD"; 1034 groups = "SPI2QUAD"; 1035 }; 1036 1037 pinctrl_acpi_default: acpi_default { 1038 function = "ACPI"; 1039 groups = "ACPI"; 1040 }; 1041 1042 pinctrl_adc0_default: adc0_default { 1043 function = "ADC0"; 1044 groups = "ADC0"; 1045 }; 1046 1047 pinctrl_adc1_default: adc1_default { 1048 function = "ADC1"; 1049 groups = "ADC1"; 1050 }; 1051 1052 pinctrl_adc10_default: adc10_default { 1053 function = "ADC10"; 1054 groups = "ADC10"; 1055 }; 1056 1057 pinctrl_adc11_default: adc11_default { 1058 function = "ADC11"; 1059 groups = "ADC11"; 1060 }; 1061 1062 pinctrl_adc12_default: adc12_default { 1063 function = "ADC12"; 1064 groups = "ADC12"; 1065 }; 1066 1067 pinctrl_adc13_default: adc13_default { 1068 function = "ADC13"; 1069 groups = "ADC13"; 1070 }; 1071 1072 pinctrl_adc14_default: adc14_default { 1073 function = "ADC14"; 1074 groups = "ADC14"; 1075 }; 1076 1077 pinctrl_adc15_default: adc15_default { 1078 function = "ADC15"; 1079 groups = "ADC15"; 1080 }; 1081 1082 pinctrl_adc2_default: adc2_default { 1083 function = "ADC2"; 1084 groups = "ADC2"; 1085 }; 1086 1087 pinctrl_adc3_default: adc3_default { 1088 function = "ADC3"; 1089 groups = "ADC3"; 1090 }; 1091 1092 pinctrl_adc4_default: adc4_default { 1093 function = "ADC4"; 1094 groups = "ADC4"; 1095 }; 1096 1097 pinctrl_adc5_default: adc5_default { 1098 function = "ADC5"; 1099 groups = "ADC5"; 1100 }; 1101 1102 pinctrl_adc6_default: adc6_default { 1103 function = "ADC6"; 1104 groups = "ADC6"; 1105 }; 1106 1107 pinctrl_adc7_default: adc7_default { 1108 function = "ADC7"; 1109 groups = "ADC7"; 1110 }; 1111 1112 pinctrl_adc8_default: adc8_default { 1113 function = "ADC8"; 1114 groups = "ADC8"; 1115 }; 1116 1117 pinctrl_adc9_default: adc9_default { 1118 function = "ADC9"; 1119 groups = "ADC9"; 1120 }; 1121 1122 pinctrl_bmcint_default: bmcint_default { 1123 function = "BMCINT"; 1124 groups = "BMCINT"; 1125 }; 1126 1127 pinctrl_ddcclk_default: ddcclk_default { 1128 function = "DDCCLK"; 1129 groups = "DDCCLK"; 1130 }; 1131 1132 pinctrl_ddcdat_default: ddcdat_default { 1133 function = "DDCDAT"; 1134 groups = "DDCDAT"; 1135 }; 1136 1137 pinctrl_espi_default: espi_default { 1138 function = "ESPI"; 1139 groups = "ESPI"; 1140 }; 1141 1142 pinctrl_fsi1_default: fsi1_default { 1143 function = "FSI1"; 1144 groups = "FSI1"; 1145 }; 1146 1147 pinctrl_fsi2_default: fsi2_default { 1148 function = "FSI2"; 1149 groups = "FSI2"; 1150 }; 1151 1152 pinctrl_fwspics1_default: fwspics1_default { 1153 function = "FWSPICS1"; 1154 groups = "FWSPICS1"; 1155 }; 1156 1157 pinctrl_fwspics2_default: fwspics2_default { 1158 function = "FWSPICS2"; 1159 groups = "FWSPICS2"; 1160 }; 1161 1162 pinctrl_gpid0_default: gpid0_default { 1163 function = "GPID0"; 1164 groups = "GPID0"; 1165 }; 1166 1167 pinctrl_gpid2_default: gpid2_default { 1168 function = "GPID2"; 1169 groups = "GPID2"; 1170 }; 1171 1172 pinctrl_gpid4_default: gpid4_default { 1173 function = "GPID4"; 1174 groups = "GPID4"; 1175 }; 1176 1177 pinctrl_gpid6_default: gpid6_default { 1178 function = "GPID6"; 1179 groups = "GPID6"; 1180 }; 1181 1182 pinctrl_gpie0_default: gpie0_default { 1183 function = "GPIE0"; 1184 groups = "GPIE0"; 1185 }; 1186 1187 pinctrl_gpie2_default: gpie2_default { 1188 function = "GPIE2"; 1189 groups = "GPIE2"; 1190 }; 1191 1192 pinctrl_gpie4_default: gpie4_default { 1193 function = "GPIE4"; 1194 groups = "GPIE4"; 1195 }; 1196 1197 pinctrl_gpie6_default: gpie6_default { 1198 function = "GPIE6"; 1199 groups = "GPIE6"; 1200 }; 1201 1202 pinctrl_i2c1_default: i2c1_default { 1203 function = "I2C1"; 1204 groups = "I2C1"; 1205 }; 1206 pinctrl_i2c2_default: i2c2_default { 1207 function = "I2C2"; 1208 groups = "I2C2"; 1209 }; 1210 1211 pinctrl_i2c3_default: i2c3_default { 1212 function = "I2C3"; 1213 groups = "I2C3"; 1214 }; 1215 1216 pinctrl_i2c4_default: i2c4_default { 1217 function = "I2C4"; 1218 groups = "I2C4"; 1219 }; 1220 1221 pinctrl_i2c5_default: i2c5_default { 1222 function = "I2C5"; 1223 groups = "I2C5"; 1224 }; 1225 1226 pinctrl_i2c6_default: i2c6_default { 1227 function = "I2C6"; 1228 groups = "I2C6"; 1229 }; 1230 1231 pinctrl_i2c7_default: i2c7_default { 1232 function = "I2C7"; 1233 groups = "I2C7"; 1234 }; 1235 1236 pinctrl_i2c8_default: i2c8_default { 1237 function = "I2C8"; 1238 groups = "I2C8"; 1239 }; 1240 1241 pinctrl_i2c9_default: i2c9_default { 1242 function = "I2C9"; 1243 groups = "I2C9"; 1244 }; 1245 1246 pinctrl_i2c10_default: i2c10_default { 1247 function = "I2C10"; 1248 groups = "I2C10"; 1249 }; 1250 1251 pinctrl_i2c11_default: i2c11_default { 1252 function = "I2C11"; 1253 groups = "I2C11"; 1254 }; 1255 1256 pinctrl_i2c12_default: i2c12_default { 1257 function = "I2C12"; 1258 groups = "I2C12"; 1259 }; 1260 1261 pinctrl_i2c13_default: i2c13_default { 1262 function = "I2C13"; 1263 groups = "I2C13"; 1264 }; 1265 1266 pinctrl_i2c14_default: i2c14_default { 1267 function = "I2C14"; 1268 groups = "I2C14"; 1269 }; 1270 1271 pinctrl_i2c15_default: i2c15_default { 1272 function = "I2C15"; 1273 groups = "I2C15"; 1274 }; 1275 1276 pinctrl_i2c16_default: i2c16_default { 1277 function = "I2C16"; 1278 groups = "I2C16"; 1279 }; 1280 1281 pinctrl_lad0_default: lad0_default { 1282 function = "LAD0"; 1283 groups = "LAD0"; 1284 }; 1285 1286 pinctrl_lad1_default: lad1_default { 1287 function = "LAD1"; 1288 groups = "LAD1"; 1289 }; 1290 1291 pinctrl_lad2_default: lad2_default { 1292 function = "LAD2"; 1293 groups = "LAD2"; 1294 }; 1295 1296 pinctrl_lad3_default: lad3_default { 1297 function = "LAD3"; 1298 groups = "LAD3"; 1299 }; 1300 1301 pinctrl_lclk_default: lclk_default { 1302 function = "LCLK"; 1303 groups = "LCLK"; 1304 }; 1305 1306 pinctrl_lframe_default: lframe_default { 1307 function = "LFRAME"; 1308 groups = "LFRAME"; 1309 }; 1310 1311 pinctrl_lpchc_default: lpchc_default { 1312 function = "LPCHC"; 1313 groups = "LPCHC"; 1314 }; 1315 1316 pinctrl_lpcpd_default: lpcpd_default { 1317 function = "LPCPD"; 1318 groups = "LPCPD"; 1319 }; 1320 1321 pinctrl_lpcplus_default: lpcplus_default { 1322 function = "LPCPLUS"; 1323 groups = "LPCPLUS"; 1324 }; 1325 1326 pinctrl_lpcpme_default: lpcpme_default { 1327 function = "LPCPME"; 1328 groups = "LPCPME"; 1329 }; 1330 1331 pinctrl_lpcrst_default: lpcrst_default { 1332 function = "LPCRST"; 1333 groups = "LPCRST"; 1334 }; 1335 1336 pinctrl_lpcsmi_default: lpcsmi_default { 1337 function = "LPCSMI"; 1338 groups = "LPCSMI"; 1339 }; 1340 1341 pinctrl_lsirq_default: lsirq_default { 1342 function = "LSIRQ"; 1343 groups = "LSIRQ"; 1344 }; 1345 1346 pinctrl_mac1link_default: mac1link_default { 1347 function = "MAC1LINK"; 1348 groups = "MAC1LINK"; 1349 }; 1350 1351 pinctrl_mac2link_default: mac2link_default { 1352 function = "MAC2LINK"; 1353 groups = "MAC2LINK"; 1354 }; 1355 1356 pinctrl_mac3link_default: mac3link_default { 1357 function = "MAC3LINK"; 1358 groups = "MAC3LINK"; 1359 }; 1360 1361 pinctrl_mac4link_default: mac4link_default { 1362 function = "MAC4LINK"; 1363 groups = "MAC4LINK"; 1364 }; 1365 1366 pinctrl_mdio1_default: mdio1_default { 1367 function = "MDIO1"; 1368 groups = "MDIO1"; 1369 }; 1370 1371 pinctrl_mdio2_default: mdio2_default { 1372 function = "MDIO2"; 1373 groups = "MDIO2"; 1374 }; 1375 1376 pinctrl_mdio3_default: mdio3_default { 1377 function = "MDIO3"; 1378 groups = "MDIO3"; 1379 }; 1380 1381 pinctrl_mdio4_default: mdio4_default { 1382 function = "MDIO4"; 1383 groups = "MDIO4"; 1384 }; 1385 1386 pinctrl_rmii1_default: rmii1_default { 1387 function = "RMII1"; 1388 groups = "RMII1"; 1389 }; 1390 1391 pinctrl_rmii2_default: rmii2_default { 1392 function = "RMII2"; 1393 groups = "RMII2"; 1394 }; 1395 1396 pinctrl_rmii3_default: rmii3_default { 1397 function = "RMII3"; 1398 groups = "RMII3"; 1399 }; 1400 1401 pinctrl_rmii4_default: rmii4_default { 1402 function = "RMII4"; 1403 groups = "RMII4"; 1404 }; 1405 1406 pinctrl_rmii1rclk_default: rmii1rclk_default { 1407 function = "RMII1RCLK"; 1408 groups = "RMII1RCLK"; 1409 }; 1410 1411 pinctrl_rmii2rclk_default: rmii2rclk_default { 1412 function = "RMII2RCLK"; 1413 groups = "RMII2RCLK"; 1414 }; 1415 1416 pinctrl_rmii3rclk_default: rmii3rclk_default { 1417 function = "RMII3RCLK"; 1418 groups = "RMII3RCLK"; 1419 }; 1420 1421 pinctrl_rmii4rclk_default: rmii4rclk_default { 1422 function = "RMII4RCLK"; 1423 groups = "RMII4RCLK"; 1424 }; 1425 1426 pinctrl_ncts1_default: ncts1_default { 1427 function = "NCTS1"; 1428 groups = "NCTS1"; 1429 }; 1430 1431 pinctrl_ncts2_default: ncts2_default { 1432 function = "NCTS2"; 1433 groups = "NCTS2"; 1434 }; 1435 1436 pinctrl_ncts3_default: ncts3_default { 1437 function = "NCTS3"; 1438 groups = "NCTS3"; 1439 }; 1440 1441 pinctrl_ncts4_default: ncts4_default { 1442 function = "NCTS4"; 1443 groups = "NCTS4"; 1444 }; 1445 1446 pinctrl_ndcd1_default: ndcd1_default { 1447 function = "NDCD1"; 1448 groups = "NDCD1"; 1449 }; 1450 1451 pinctrl_ndcd2_default: ndcd2_default { 1452 function = "NDCD2"; 1453 groups = "NDCD2"; 1454 }; 1455 1456 pinctrl_ndcd3_default: ndcd3_default { 1457 function = "NDCD3"; 1458 groups = "NDCD3"; 1459 }; 1460 1461 pinctrl_ndcd4_default: ndcd4_default { 1462 function = "NDCD4"; 1463 groups = "NDCD4"; 1464 }; 1465 1466 pinctrl_ndsr1_default: ndsr1_default { 1467 function = "NDSR1"; 1468 groups = "NDSR1"; 1469 }; 1470 1471 pinctrl_ndsr2_default: ndsr2_default { 1472 function = "NDSR2"; 1473 groups = "NDSR2"; 1474 }; 1475 1476 pinctrl_ndsr3_default: ndsr3_default { 1477 function = "NDSR3"; 1478 groups = "NDSR3"; 1479 }; 1480 1481 pinctrl_ndsr4_default: ndsr4_default { 1482 function = "NDSR4"; 1483 groups = "NDSR4"; 1484 }; 1485 1486 pinctrl_ndtr1_default: ndtr1_default { 1487 function = "NDTR1"; 1488 groups = "NDTR1"; 1489 }; 1490 1491 pinctrl_ndtr2_default: ndtr2_default { 1492 function = "NDTR2"; 1493 groups = "NDTR2"; 1494 }; 1495 1496 pinctrl_ndtr3_default: ndtr3_default { 1497 function = "NDTR3"; 1498 groups = "NDTR3"; 1499 }; 1500 1501 pinctrl_ndtr4_default: ndtr4_default { 1502 function = "NDTR4"; 1503 groups = "NDTR4"; 1504 }; 1505 1506 pinctrl_nri1_default: nri1_default { 1507 function = "NRI1"; 1508 groups = "NRI1"; 1509 }; 1510 1511 pinctrl_nri2_default: nri2_default { 1512 function = "NRI2"; 1513 groups = "NRI2"; 1514 }; 1515 1516 pinctrl_nri3_default: nri3_default { 1517 function = "NRI3"; 1518 groups = "NRI3"; 1519 }; 1520 1521 pinctrl_nri4_default: nri4_default { 1522 function = "NRI4"; 1523 groups = "NRI4"; 1524 }; 1525 1526 pinctrl_nrts1_default: nrts1_default { 1527 function = "NRTS1"; 1528 groups = "NRTS1"; 1529 }; 1530 1531 pinctrl_nrts2_default: nrts2_default { 1532 function = "NRTS2"; 1533 groups = "NRTS2"; 1534 }; 1535 1536 pinctrl_nrts3_default: nrts3_default { 1537 function = "NRTS3"; 1538 groups = "NRTS3"; 1539 }; 1540 1541 pinctrl_nrts4_default: nrts4_default { 1542 function = "NRTS4"; 1543 groups = "NRTS4"; 1544 }; 1545 1546 pinctrl_oscclk_default: oscclk_default { 1547 function = "OSCCLK"; 1548 groups = "OSCCLK"; 1549 }; 1550 1551 pinctrl_pewake_default: pewake_default { 1552 function = "PEWAKE"; 1553 groups = "PEWAKE"; 1554 }; 1555 1556 pinctrl_pnor_default: pnor_default { 1557 function = "PNOR"; 1558 groups = "PNOR"; 1559 }; 1560 1561 pinctrl_pwm0_default: pwm0_default { 1562 function = "PWM0"; 1563 groups = "PWM0"; 1564 }; 1565 1566 pinctrl_pwm1_default: pwm1_default { 1567 function = "PWM1"; 1568 groups = "PWM1"; 1569 }; 1570 1571 pinctrl_pwm2_default: pwm2_default { 1572 function = "PWM2"; 1573 groups = "PWM2"; 1574 }; 1575 1576 pinctrl_pwm3_default: pwm3_default { 1577 function = "PWM3"; 1578 groups = "PWM3"; 1579 }; 1580 1581 pinctrl_pwm4_default: pwm4_default { 1582 function = "PWM4"; 1583 groups = "PWM4"; 1584 }; 1585 1586 pinctrl_pwm5_default: pwm5_default { 1587 function = "PWM5"; 1588 groups = "PWM5"; 1589 }; 1590 1591 pinctrl_pwm6_default: pwm6_default { 1592 function = "PWM6"; 1593 groups = "PWM6"; 1594 }; 1595 1596 pinctrl_pwm7_default: pwm7_default { 1597 function = "PWM7"; 1598 groups = "PWM7"; 1599 }; 1600 1601 pinctrl_rgmii1_default: rgmii1_default { 1602 function = "RGMII1"; 1603 groups = "RGMII1"; 1604 }; 1605 1606 pinctrl_rgmii2_default: rgmii2_default { 1607 function = "RGMII2"; 1608 groups = "RGMII2"; 1609 }; 1610 1611 pinctrl_rgmii3_default: rgmii3_default { 1612 function = "RGMII3"; 1613 groups = "RGMII3"; 1614 }; 1615 1616 pinctrl_rgmii4_default: rgmii4_default { 1617 function = "RGMII4"; 1618 groups = "RGMII4"; 1619 }; 1620 1621 pinctrl_rmii1_default: rmii1_default { 1622 function = "RMII1"; 1623 groups = "RMII1"; 1624 }; 1625 1626 pinctrl_rmii2_default: rmii2_default { 1627 function = "RMII2"; 1628 groups = "RMII2"; 1629 }; 1630 1631 pinctrl_rxd1_default: rxd1_default { 1632 function = "RXD1"; 1633 groups = "RXD1"; 1634 }; 1635 1636 pinctrl_rxd2_default: rxd2_default { 1637 function = "RXD2"; 1638 groups = "RXD2"; 1639 }; 1640 1641 pinctrl_rxd3_default: rxd3_default { 1642 function = "RXD3"; 1643 groups = "RXD3"; 1644 }; 1645 1646 pinctrl_rxd4_default: rxd4_default { 1647 function = "RXD4"; 1648 groups = "RXD4"; 1649 }; 1650 1651 pinctrl_salt1_default: salt1_default { 1652 function = "SALT1"; 1653 groups = "SALT1"; 1654 }; 1655 1656 pinctrl_salt10_default: salt10_default { 1657 function = "SALT10"; 1658 groups = "SALT10"; 1659 }; 1660 1661 pinctrl_salt11_default: salt11_default { 1662 function = "SALT11"; 1663 groups = "SALT11"; 1664 }; 1665 1666 pinctrl_salt12_default: salt12_default { 1667 function = "SALT12"; 1668 groups = "SALT12"; 1669 }; 1670 1671 pinctrl_salt13_default: salt13_default { 1672 function = "SALT13"; 1673 groups = "SALT13"; 1674 }; 1675 1676 pinctrl_salt14_default: salt14_default { 1677 function = "SALT14"; 1678 groups = "SALT14"; 1679 }; 1680 1681 pinctrl_salt2_default: salt2_default { 1682 function = "SALT2"; 1683 groups = "SALT2"; 1684 }; 1685 1686 pinctrl_salt3_default: salt3_default { 1687 function = "SALT3"; 1688 groups = "SALT3"; 1689 }; 1690 1691 pinctrl_salt4_default: salt4_default { 1692 function = "SALT4"; 1693 groups = "SALT4"; 1694 }; 1695 1696 pinctrl_salt5_default: salt5_default { 1697 function = "SALT5"; 1698 groups = "SALT5"; 1699 }; 1700 1701 pinctrl_salt6_default: salt6_default { 1702 function = "SALT6"; 1703 groups = "SALT6"; 1704 }; 1705 1706 pinctrl_salt7_default: salt7_default { 1707 function = "SALT7"; 1708 groups = "SALT7"; 1709 }; 1710 1711 pinctrl_salt8_default: salt8_default { 1712 function = "SALT8"; 1713 groups = "SALT8"; 1714 }; 1715 1716 pinctrl_salt9_default: salt9_default { 1717 function = "SALT9"; 1718 groups = "SALT9"; 1719 }; 1720 1721 pinctrl_scl1_default: scl1_default { 1722 function = "SCL1"; 1723 groups = "SCL1"; 1724 }; 1725 1726 pinctrl_scl2_default: scl2_default { 1727 function = "SCL2"; 1728 groups = "SCL2"; 1729 }; 1730 1731 pinctrl_sd1_default: sd1_default { 1732 function = "SD1"; 1733 groups = "SD1"; 1734 }; 1735 1736 pinctrl_sd2_default: sd2_default { 1737 function = "SD2"; 1738 groups = "SD2"; 1739 }; 1740 1741 pinctrl_emmc_default: emmc_default { 1742 function = "EMMC"; 1743 groups = "EMMC"; 1744 }; 1745 1746 pinctrl_emmcg8_default: emmcg8_default { 1747 function = "EMMCG8"; 1748 groups = "EMMCG8"; 1749 }; 1750 1751 pinctrl_sda1_default: sda1_default { 1752 function = "SDA1"; 1753 groups = "SDA1"; 1754 }; 1755 1756 pinctrl_sda2_default: sda2_default { 1757 function = "SDA2"; 1758 groups = "SDA2"; 1759 }; 1760 1761 pinctrl_sgps1_default: sgps1_default { 1762 function = "SGPS1"; 1763 groups = "SGPS1"; 1764 }; 1765 1766 pinctrl_sgps2_default: sgps2_default { 1767 function = "SGPS2"; 1768 groups = "SGPS2"; 1769 }; 1770 1771 pinctrl_sioonctrl_default: sioonctrl_default { 1772 function = "SIOONCTRL"; 1773 groups = "SIOONCTRL"; 1774 }; 1775 1776 pinctrl_siopbi_default: siopbi_default { 1777 function = "SIOPBI"; 1778 groups = "SIOPBI"; 1779 }; 1780 1781 pinctrl_siopbo_default: siopbo_default { 1782 function = "SIOPBO"; 1783 groups = "SIOPBO"; 1784 }; 1785 1786 pinctrl_siopwreq_default: siopwreq_default { 1787 function = "SIOPWREQ"; 1788 groups = "SIOPWREQ"; 1789 }; 1790 1791 pinctrl_siopwrgd_default: siopwrgd_default { 1792 function = "SIOPWRGD"; 1793 groups = "SIOPWRGD"; 1794 }; 1795 1796 pinctrl_sios3_default: sios3_default { 1797 function = "SIOS3"; 1798 groups = "SIOS3"; 1799 }; 1800 1801 pinctrl_sios5_default: sios5_default { 1802 function = "SIOS5"; 1803 groups = "SIOS5"; 1804 }; 1805 1806 pinctrl_siosci_default: siosci_default { 1807 function = "SIOSCI"; 1808 groups = "SIOSCI"; 1809 }; 1810 1811 pinctrl_spi1_default: spi1_default { 1812 function = "SPI1"; 1813 groups = "SPI1"; 1814 }; 1815 1816 pinctrl_spi1cs1_default: spi1cs1_default { 1817 function = "SPI1CS1"; 1818 groups = "SPI1CS1"; 1819 }; 1820 1821 pinctrl_spi1debug_default: spi1debug_default { 1822 function = "SPI1DEBUG"; 1823 groups = "SPI1DEBUG"; 1824 }; 1825 1826 pinctrl_spi1passthru_default: spi1passthru_default { 1827 function = "SPI1PASSTHRU"; 1828 groups = "SPI1PASSTHRU"; 1829 }; 1830 1831 pinctrl_spi2ck_default: spi2ck_default { 1832 function = "SPI2CK"; 1833 groups = "SPI2CK"; 1834 }; 1835 1836 pinctrl_spi2cs0_default: spi2cs0_default { 1837 function = "SPI2CS0"; 1838 groups = "SPI2CS0"; 1839 }; 1840 1841 pinctrl_spi2cs1_default: spi2cs1_default { 1842 function = "SPI2CS1"; 1843 groups = "SPI2CS1"; 1844 }; 1845 1846 pinctrl_spi2miso_default: spi2miso_default { 1847 function = "SPI2MISO"; 1848 groups = "SPI2MISO"; 1849 }; 1850 1851 pinctrl_spi2mosi_default: spi2mosi_default { 1852 function = "SPI2MOSI"; 1853 groups = "SPI2MOSI"; 1854 }; 1855 1856 pinctrl_timer3_default: timer3_default { 1857 function = "TIMER3"; 1858 groups = "TIMER3"; 1859 }; 1860 1861 pinctrl_timer4_default: timer4_default { 1862 function = "TIMER4"; 1863 groups = "TIMER4"; 1864 }; 1865 1866 pinctrl_timer5_default: timer5_default { 1867 function = "TIMER5"; 1868 groups = "TIMER5"; 1869 }; 1870 1871 pinctrl_timer6_default: timer6_default { 1872 function = "TIMER6"; 1873 groups = "TIMER6"; 1874 }; 1875 1876 pinctrl_timer7_default: timer7_default { 1877 function = "TIMER7"; 1878 groups = "TIMER7"; 1879 }; 1880 1881 pinctrl_timer8_default: timer8_default { 1882 function = "TIMER8"; 1883 groups = "TIMER8"; 1884 }; 1885 1886 pinctrl_txd1_default: txd1_default { 1887 function = "TXD1"; 1888 groups = "TXD1"; 1889 }; 1890 1891 pinctrl_txd2_default: txd2_default { 1892 function = "TXD2"; 1893 groups = "TXD2"; 1894 }; 1895 1896 pinctrl_txd3_default: txd3_default { 1897 function = "TXD3"; 1898 groups = "TXD3"; 1899 }; 1900 1901 pinctrl_txd4_default: txd4_default { 1902 function = "TXD4"; 1903 groups = "TXD4"; 1904 }; 1905 1906 pinctrl_uart6_default: uart6_default { 1907 function = "UART6"; 1908 groups = "UART6"; 1909 }; 1910 1911 pinctrl_usbcki_default: usbcki_default { 1912 function = "USBCKI"; 1913 groups = "USBCKI"; 1914 }; 1915 1916 pinctrl_usb2ah_default: usb2ah_default { 1917 function = "USB2AH"; 1918 groups = "USB2AH"; 1919 }; 1920 1921 pinctrl_usb11bhid_default: usb11bhid_default { 1922 function = "USB11BHID"; 1923 groups = "USB11BHID"; 1924 }; 1925 1926 pinctrl_usb2bh_default: usb2bh_default { 1927 function = "USB2BH"; 1928 groups = "USB2BH"; 1929 }; 1930 1931 pinctrl_vgabiosrom_default: vgabiosrom_default { 1932 function = "VGABIOSROM"; 1933 groups = "VGABIOSROM"; 1934 }; 1935 1936 pinctrl_vgahs_default: vgahs_default { 1937 function = "VGAHS"; 1938 groups = "VGAHS"; 1939 }; 1940 1941 pinctrl_vgavs_default: vgavs_default { 1942 function = "VGAVS"; 1943 groups = "VGAVS"; 1944 }; 1945 1946 pinctrl_vpi24_default: vpi24_default { 1947 function = "VPI24"; 1948 groups = "VPI24"; 1949 }; 1950 1951 pinctrl_vpo_default: vpo_default { 1952 function = "VPO"; 1953 groups = "VPO"; 1954 }; 1955 1956 pinctrl_wdtrst1_default: wdtrst1_default { 1957 function = "WDTRST1"; 1958 groups = "WDTRST1"; 1959 }; 1960 1961 pinctrl_wdtrst2_default: wdtrst2_default { 1962 function = "WDTRST2"; 1963 groups = "WDTRST2"; 1964 }; 1965 1966 pinctrl_pcie0rc_default: pcie0rc_default { 1967 function = "PCIE0RC"; 1968 groups = "PCIE0RC"; 1969 }; 1970 1971 pinctrl_pcie1rc_default: pcie1rc_default { 1972 function = "PCIE1RC"; 1973 groups = "PCIE1RC"; 1974 }; 1975}; 1976