1// SPDX-License-Identifier: GPL-2.0+ 2#include <dt-bindings/interrupt-controller/arm-gic.h> 3#include <dt-bindings/gpio/aspeed-gpio.h> 4#include "skeleton.dtsi" 5 6/ { 7 model = "Aspeed BMC"; 8 compatible = "aspeed,ast2600"; 9 #address-cells = <1>; 10 #size-cells = <1>; 11 interrupt-parent = <&gic>; 12 13 aliases { 14 i2c0 = &i2c0; 15 i2c1 = &i2c1; 16 i2c2 = &i2c2; 17 i2c3 = &i2c3; 18 i2c4 = &i2c4; 19 i2c5 = &i2c5; 20 i2c6 = &i2c6; 21 i2c7 = &i2c7; 22 i2c8 = &i2c8; 23 i2c9 = &i2c9; 24 i2c10 = &i2c10; 25 i2c11 = &i2c11; 26 i2c12 = &i2c12; 27 i2c13 = &i2c13; 28 i2c14 = &i2c14; 29 i2c15 = &i2c15; 30 serial0 = &uart1; 31 serial1 = &uart2; 32 serial2 = &uart3; 33 serial3 = &uart4; 34 serial4 = &uart5; 35 serial5 = &uart6; 36 serial6 = &uart7; 37 serial7 = &uart8; 38 serial8 = &uart9; 39 serial9 = &uart10; 40 serial10 = &uart11; 41 serial11 = &uart12; 42 serial12 = &uart13; 43 }; 44 45 cpus { 46 #address-cells = <1>; 47 #size-cells = <0>; 48 enable-method = "aspeed,ast2600-smp"; 49 50 cpu@0 { 51 compatible = "arm,cortex-a7"; 52 device_type = "cpu"; 53 reg = <0>; 54 clock-frequency = <48000000>; 55 }; 56 57 cpu@1 { 58 compatible = "arm,cortex-a7"; 59 device_type = "cpu"; 60 reg = <1>; 61 clock-frequency = <48000000>; 62 }; 63 64 }; 65 66 timer { 67 compatible = "arm,armv7-timer"; 68 interrupt-parent = <&gic>; 69 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 70 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 71 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 72 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 73 clock-frequency = <25000000>; 74 }; 75 76 memory@80000000 { 77 device_type = "memory"; 78 reg = <0x80000000 0>; 79 }; 80 81 reserved-memory { 82 #address-cells = <1>; 83 #size-cells = <1>; 84 ranges; 85 86 gfx_memory: framebuffer { 87 size = <0x01000000>; 88 alignment = <0x01000000>; 89 compatible = "shared-dma-pool"; 90 reusable; 91 }; 92 93 video_memory: video { 94 size = <0x04000000>; 95 alignment = <0x01000000>; 96 compatible = "shared-dma-pool"; 97 no-map; 98 }; 99 }; 100 101 ahb { 102 compatible = "simple-bus"; 103 #address-cells = <1>; 104 #size-cells = <1>; 105 device_type = "soc"; 106 ranges; 107 108 gic: interrupt-controller@40461000 { 109 compatible = "arm,cortex-a7-gic"; 110 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 111 #interrupt-cells = <3>; 112 interrupt-controller; 113 interrupt-parent = <&gic>; 114 reg = <0x40461000 0x1000>, 115 <0x40462000 0x1000>, 116 <0x40464000 0x2000>, 117 <0x40466000 0x2000>; 118 }; 119 120 fmc: flash-controller@1e620000 { 121 reg = < 0x1e620000 0xc4 122 0x20000000 0x10000000 >; 123 #address-cells = <1>; 124 #size-cells = <0>; 125 compatible = "aspeed,ast2600-fmc"; 126 status = "disabled"; 127 interrupts = <19>; 128 clocks = <&scu ASPEED_CLK_AHB>; 129 flash@0 { 130 reg = < 0 >; 131 compatible = "jedec,spi-nor"; 132 status = "disabled"; 133 }; 134 flash@1 { 135 reg = < 1 >; 136 compatible = "jedec,spi-nor"; 137 status = "disabled"; 138 }; 139 flash@2 { 140 reg = < 2 >; 141 compatible = "jedec,spi-nor"; 142 status = "disabled"; 143 }; 144 }; 145 146 spi1: flash-controller@1e630000 { 147 reg = < 0x1e630000 0xc4 148 0x30000000 0x08000000 >; 149 #address-cells = <1>; 150 #size-cells = <0>; 151 compatible = "aspeed,ast2600-spi"; 152 clocks = <&scu ASPEED_CLK_AHB>; 153 status = "disabled"; 154 flash@0 { 155 reg = < 0 >; 156 compatible = "jedec,spi-nor"; 157 status = "disabled"; 158 }; 159 flash@1 { 160 reg = < 1 >; 161 compatible = "jedec,spi-nor"; 162 status = "disabled"; 163 }; 164 }; 165 166 spi2: flash-controller@1e631000 { 167 reg = < 0x1e631000 0xc4 168 0x38000000 0x08000000 >; 169 #address-cells = <1>; 170 #size-cells = <0>; 171 compatible = "aspeed,ast2600-spi"; 172 clocks = <&scu ASPEED_CLK_AHB>; 173 status = "disabled"; 174 flash@0 { 175 reg = < 0 >; 176 compatible = "jedec,spi-nor"; 177 status = "disabled"; 178 }; 179 flash@1 { 180 reg = < 1 >; 181 compatible = "jedec,spi-nor"; 182 status = "disabled"; 183 }; 184 }; 185 186 edac: sdram@1e6e0000 { 187 compatible = "aspeed,ast2600-sdram-edac"; 188 reg = <0x1e6e0000 0x174>; 189 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 190 }; 191 192 mdio: ethernet@1e650000 { 193 compatible = "aspeed,aspeed-mdio"; 194 reg = <0x1e650000 0x40>; 195 resets = <&rst ASPEED_RESET_MII>; 196 status = "disabled"; 197 }; 198 199 mac0: ethernet@1e660000 { 200 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 201 reg = <0x1e660000 0x180>, <0x1e650000 0x4>; 202 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 203 clocks = <&scu ASPEED_CLK_GATE_MAC1CLK>; 204 status = "disabled"; 205 }; 206 207 mac2: ftgmac@1e670000 { 208 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 209 reg = <0x1e670000 0x180>, <0x1e650010 0x4>; 210 #address-cells = <1>; 211 #size-cells = <0>; 212 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 213 clocks = <&scu ASPEED_CLK_GATE_MAC3CLK>; 214#if 0 215 phy-handle = <&phy0>; 216#endif 217 status = "disabled"; 218 }; 219 220 mac1: ftgmac@1e680000 { 221 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 222 reg = <0x1e680000 0x180>, <0x1e650008 0x4>; 223 #address-cells = <1>; 224 #size-cells = <0>; 225 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 226 clocks = <&scu ASPEED_CLK_GATE_MAC2CLK>; 227#if 0 228 phy-handle = <&phy0>; 229#endif 230 status = "disabled"; 231 }; 232 233 mac3: ftgmac@1e690000 { 234 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 235 reg = <0x1e690000 0x180>, <0x1e650018 0x4>; 236 #address-cells = <1>; 237 #size-cells = <0>; 238 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 239 clocks = <&scu ASPEED_CLK_GATE_MAC4CLK>; 240#if 0 241 phy-handle = <&phy0>; 242#endif 243 status = "disabled"; 244 }; 245 246 247 apb { 248 compatible = "simple-bus"; 249 #address-cells = <1>; 250 #size-cells = <1>; 251 ranges; 252 253 syscon: syscon@1e6e2000 { 254 compatible = "aspeed,g6-scu", "syscon", "simple-mfd"; 255 reg = <0x1e6e2000 0x1000>; 256 #address-cells = <1>; 257 #size-cells = <1>; 258 #clock-cells = <1>; 259 #reset-cells = <1>; 260 ranges = <0 0x1e6e2000 0x1000>; 261 262 pinctrl: pinctrl { 263 compatible = "aspeed,g6-pinctrl"; 264 aspeed,external-nodes = <&gfx &lhc>; 265 266 }; 267 268 vga_scratch: scratch { 269 compatible = "aspeed,bmc-misc"; 270 }; 271 272 scu_ic0: interrupt-controller@0 { 273 #interrupt-cells = <1>; 274 compatible = "aspeed,ast2600-scu-ic"; 275 reg = <0x560 0x10>; 276 interrupt-parent = <&gic>; 277 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 278 interrupt-controller; 279 }; 280 281 scu_ic1: interrupt-controller@1 { 282 #interrupt-cells = <1>; 283 compatible = "aspeed,ast2600-scu-ic"; 284 reg = <0x570 0x10>; 285 interrupt-parent = <&gic>; 286 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 287 interrupt-controller; 288 }; 289 290 }; 291 292 smp-memram@0 { 293 compatible = "aspeed,ast2600-smpmem", "syscon"; 294 reg = <0x1e6e2180 0x40>; 295 }; 296 297 gfx: display@1e6e6000 { 298 compatible = "aspeed,ast2500-gfx", "syscon"; 299 reg = <0x1e6e6000 0x1000>; 300 reg-io-width = <4>; 301 }; 302 303 sdhci: sdhci@1e740000 { 304 #interrupt-cells = <1>; 305 compatible = "aspeed,aspeed-sdhci-irq", "simple-mfd"; 306 reg = <0x1e740000 0x1000>; 307 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 308 interrupt-controller; 309 clocks = <&scu ASPEED_CLK_GATE_SDCLK>, <&scu ASPEED_CLK_GATE_SDEXTCLK>; 310 clock-names = "ctrlclk", "extclk"; 311 #address-cells = <1>; 312 #size-cells = <1>; 313 ranges = <0x0 0x1e740000 0x1000>; 314 315 sdhci_slot0: sdhci_slot0@100 { 316 compatible = "aspeed,sdhci-ast2600"; 317 reg = <0x100 0x100>; 318 interrupts = <0>; 319 interrupt-parent = <&sdhci>; 320 sdhci,auto-cmd12; 321 clocks = <&scu ASPEED_CLK_SDIO>; 322 pwr-gpios = <&gpio0 ASPEED_GPIO(V, 0) GPIO_ACTIVE_LOW>; 323 pwr-sw-gpios = <&gpio0 ASPEED_GPIO(V, 1) GPIO_ACTIVE_LOW>; 324 status = "disabled"; 325 }; 326 327 sdhci_slot1: sdhci_slot1@200 { 328 compatible = "aspeed,sdhci-ast2600"; 329 reg = <0x200 0x100>; 330 interrupts = <1>; 331 interrupt-parent = <&sdhci>; 332 sdhci,auto-cmd12; 333 clocks = <&scu ASPEED_CLK_SDIO>; 334 pwr-gpios = <&gpio0 ASPEED_GPIO(V, 2) GPIO_ACTIVE_LOW>; 335 pwr-sw-gpios = <&gpio0 ASPEED_GPIO(V, 3) GPIO_ACTIVE_LOW>; 336 status = "disabled"; 337 }; 338 339 }; 340 341 emmc: emmc@1e750000 { 342 #interrupt-cells = <1>; 343 compatible = "aspeed,aspeed-emmc-irq", "simple-mfd"; 344 reg = <0x1e750000 0x1000>; 345 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 346 interrupt-controller; 347 clocks = <&scu ASPEED_CLK_GATE_EMMCCLK>, <&scu ASPEED_CLK_GATE_EMMCEXTCLK>; 348 clock-names = "ctrlclk", "extclk"; 349 #address-cells = <1>; 350 #size-cells = <1>; 351 ranges = <0x0 0x1e750000 0x1000>; 352 353 emmc_slot0: emmc_slot0@100 { 354 compatible = "aspeed,emmc-ast2600"; 355 reg = <0x100 0x100>; 356 interrupts = <0>; 357 interrupt-parent = <&emmc>; 358 clocks = <&scu ASPEED_CLK_EMMC>; 359 status = "disabled"; 360 }; 361 362 }; 363 364 gpio0: gpio@1e780000 { 365 compatible = "aspeed,ast2600-gpio"; 366 reg = <0x1e780000 0x1000>; 367 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 368 #gpio-cells = <2>; 369 gpio-controller; 370 interrupt-controller; 371 gpio-ranges = <&pinctrl 0 0 220>; 372 }; 373 374 gpio1: gpio@1e780800 { 375 compatible = "aspeed,ast2600-gpio"; 376 reg = <0x1e780800 0x800>; 377 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 378 #gpio-cells = <2>; 379 gpio-controller; 380 interrupt-controller; 381 gpio-ranges = <&pinctrl 0 0 208>; 382 }; 383 384 uart1: serial@1e783000 { 385 compatible = "ns16550a"; 386 reg = <0x1e783000 0x20>; 387 reg-shift = <2>; 388 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 389 clocks = <&scu ASPEED_CLK_GATE_UART1CLK>; 390 no-loopback-test; 391 status = "disabled"; 392 }; 393 394 uart5: serial@1e784000 { 395 compatible = "ns16550a"; 396 reg = <0x1e784000 0x1000>; 397 reg-shift = <2>; 398 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 399 clocks = <&scu ASPEED_CLK_GATE_UART5CLK>; 400 no-loopback-test; 401 status = "disabled"; 402 }; 403 404 wdt1: watchdog@1e785000 { 405 compatible = "aspeed,ast2600-wdt"; 406 reg = <0x1e785000 0x40>; 407 }; 408 409 wdt2: watchdog@1e785040 { 410 compatible = "aspeed,ast2600-wdt"; 411 reg = <0x1e785040 0x40>; 412 }; 413 414 wdt3: watchdog@1e785080 { 415 compatible = "aspeed,ast2600-wdt"; 416 reg = <0x1e785080 0x40>; 417 }; 418 419 wdt4: watchdog@1e7850C0 { 420 compatible = "aspeed,ast2600-wdt"; 421 reg = <0x1e7850C0 0x40>; 422 }; 423 424 lpc: lpc@1e789000 { 425 compatible = "aspeed,ast-lpc", "simple-mfd", "syscon"; 426 reg = <0x1e789000 0x200>; 427 428 #address-cells = <1>; 429 #size-cells = <1>; 430 ranges = <0x0 0x1e789000 0x1000>; 431 432 lpc_bmc: lpc-bmc@0 { 433 compatible = "aspeed,ast2600-lpc-bmc", "simple-mfd", "syscon"; 434 reg = <0x0 0x80>; 435 reg-io-width = <4>; 436 #address-cells = <1>; 437 #size-cells = <1>; 438 ranges = <0x0 0x0 0x80>; 439 440 kcs1: kcs1@0 { 441 compatible = "aspeed,ast2600-kcs-bmc"; 442 reg = <0x0 0x80>; 443 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 444 kcs_chan = <1>; 445 kcs_addr = <0xCA0>; 446 status = "disabled"; 447 }; 448 449 kcs2: kcs2@0 { 450 compatible = "aspeed,ast2600-kcs-bmc"; 451 reg = <0x0 0x80>; 452 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 453 kcs_chan = <2>; 454 kcs_addr = <0xCA8>; 455 status = "disabled"; 456 }; 457 458 kcs3: kcs3@0 { 459 compatible = "aspeed,ast2600-kcs-bmc"; 460 reg = <0x0 0x80>; 461 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 462 kcs_chan = <3>; 463 kcs_addr = <0xCA2>; 464 }; 465 466 kcs4: kcs4@0 { 467 compatible = "aspeed,ast2600-kcs-bmc"; 468 reg = <0x0 0x120>; 469 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 470 kcs_chan = <4>; 471 kcs_addr = <0xCA4>; 472 status = "disabled"; 473 }; 474 475 }; 476 477 lpc_host: lpc-host@80 { 478 compatible = "aspeed,ast2600-lpc-host", "simple-mfd", "syscon"; 479 reg = <0x80 0x1e0>; 480 reg-io-width = <4>; 481 482 #address-cells = <1>; 483 #size-cells = <1>; 484 ranges = <0x0 0x80 0x1e0>; 485 486 lpc_ctrl: lpc-ctrl@0 { 487 compatible = "aspeed,ast2600-lpc-ctrl"; 488 reg = <0x0 0x80>; 489 status = "disabled"; 490 }; 491 492 lpc_snoop: lpc-snoop@0 { 493 compatible = "aspeed,ast2600-lpc-snoop"; 494 reg = <0x0 0x80>; 495 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 496 snoop-ports = <0x80>; 497 status = "disabled"; 498 }; 499 500 lhc: lhc@20 { 501 compatible = "aspeed,ast2600-lhc"; 502 reg = <0x20 0x24 0x48 0x8>; 503 }; 504 505 lpc_reset: reset-controller@18 { 506 compatible = "aspeed,ast2600-lpc-reset"; 507 reg = <0x18 0x4>; 508 #reset-cells = <1>; 509 status = "disabled"; 510 }; 511 512 ibt: ibt@c0 { 513 compatible = "aspeed,ast2600-ibt-bmc"; 514 reg = <0xc0 0x18>; 515 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 516 status = "disabled"; 517 }; 518 519 sio_regs: regs { 520 compatible = "aspeed,bmc-misc"; 521 }; 522 523 mbox: mbox@180 { 524 compatible = "aspeed,ast2600-mbox"; 525 reg = <0x180 0x5c>; 526 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 527 #mbox-cells = <1>; 528 status = "disabled"; 529 }; 530 }; 531 }; 532 533 uart2: serial@1e78d000 { 534 compatible = "ns16550a"; 535 reg = <0x1e78d000 0x20>; 536 reg-shift = <2>; 537 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 538 clocks = <&scu ASPEED_CLK_GATE_UART2CLK>; 539 no-loopback-test; 540 status = "disabled"; 541 }; 542 543 uart3: serial@1e78e000 { 544 compatible = "ns16550a"; 545 reg = <0x1e78e000 0x20>; 546 reg-shift = <2>; 547 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 548 clocks = <&scu ASPEED_CLK_GATE_UART3CLK>; 549 no-loopback-test; 550 status = "disabled"; 551 }; 552 553 uart4: serial@1e78f000 { 554 compatible = "ns16550a"; 555 reg = <0x1e78f000 0x20>; 556 reg-shift = <2>; 557 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 558 clocks = <&scu ASPEED_CLK_GATE_UART4CLK>; 559 no-loopback-test; 560 status = "disabled"; 561 }; 562 563 i2c: bus@1e78a000 { 564 compatible = "simple-bus"; 565 #address-cells = <1>; 566 #size-cells = <1>; 567 ranges = <0 0x1e78a000 0x1000>; 568 }; 569 570 uart6: serial@1e790000 { 571 compatible = "ns16550a"; 572 reg = <0x1e790000 0x20>; 573 reg-shift = <2>; 574 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 575 clocks = <&scu ASPEED_CLK_GATE_UART6CLK>; 576 no-loopback-test; 577 status = "disabled"; 578 }; 579 580 uart7: serial@1e790100 { 581 compatible = "ns16550a"; 582 reg = <0x1e790100 0x20>; 583 reg-shift = <2>; 584 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 585 clocks = <&scu ASPEED_CLK_GATE_UART7CLK>; 586 no-loopback-test; 587 status = "disabled"; 588 }; 589 590 uart8: serial@1e790200 { 591 compatible = "ns16550a"; 592 reg = <0x1e790200 0x20>; 593 reg-shift = <2>; 594 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 595 clocks = <&scu ASPEED_CLK_GATE_UART8CLK>; 596 no-loopback-test; 597 status = "disabled"; 598 }; 599 600 uart9: serial@1e790300 { 601 compatible = "ns16550a"; 602 reg = <0x1e790300 0x20>; 603 reg-shift = <2>; 604 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 605 clocks = <&scu ASPEED_CLK_GATE_UART9CLK>; 606 no-loopback-test; 607 status = "disabled"; 608 }; 609 610 uart10: serial@1e790400 { 611 compatible = "ns16550a"; 612 reg = <0x1e790400 0x20>; 613 reg-shift = <2>; 614 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 615 clocks = <&scu ASPEED_CLK_GATE_UART10CLK>; 616 no-loopback-test; 617 status = "disabled"; 618 }; 619 620 uart11: serial@1e790500 { 621 compatible = "ns16550a"; 622 reg = <0x1e790400 0x20>; 623 reg-shift = <2>; 624 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 625 clocks = <&scu ASPEED_CLK_GATE_UART11CLK>; 626 no-loopback-test; 627 status = "disabled"; 628 }; 629 630 uart12: serial@1e790600 { 631 compatible = "ns16550a"; 632 reg = <0x1e790600 0x20>; 633 reg-shift = <2>; 634 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 635 clocks = <&scu ASPEED_CLK_GATE_UART12CLK>; 636 no-loopback-test; 637 status = "disabled"; 638 }; 639 640 uart13: serial@1e790700 { 641 compatible = "ns16550a"; 642 reg = <0x1e790700 0x20>; 643 reg-shift = <2>; 644 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 645 clocks = <&scu ASPEED_CLK_GATE_UART13CLK>; 646 no-loopback-test; 647 status = "disabled"; 648 }; 649 650 651 652 }; 653 654 }; 655 656}; 657 658&i2c { 659 i2cglobal: i2cg@00 { 660 compatible = "aspeed,ast2600-i2c-global"; 661 reg = <0x0 0x40>; 662 resets = <&rst ASPEED_RESET_I2C>; 663#if 0 664 new-mode; 665#endif 666 }; 667 668 i2c0: i2c@80 { 669 #address-cells = <1>; 670 #size-cells = <0>; 671 #interrupt-cells = <1>; 672 673 reg = <0x80 0x80 0xC00 0x20>; 674 compatible = "aspeed,ast2600-i2c-bus"; 675 bus-frequency = <100000>; 676 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 677 clocks = <&scu ASPEED_CLK_APB>; 678 status = "disabled"; 679 }; 680 681 i2c1: i2c@100 { 682 #address-cells = <1>; 683 #size-cells = <0>; 684 #interrupt-cells = <1>; 685 686 reg = <0x100 0x80 0xC20 0x20>; 687 compatible = "aspeed,ast2600-i2c-bus"; 688 bus-frequency = <100000>; 689 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 690 clocks = <&scu ASPEED_CLK_APB>; 691 status = "disabled"; 692 }; 693 694 i2c2: i2c@180 { 695 #address-cells = <1>; 696 #size-cells = <0>; 697 #interrupt-cells = <1>; 698 699 reg = <0x180 0x80 0xC40 0x20>; 700 compatible = "aspeed,ast2600-i2c-bus"; 701 bus-frequency = <100000>; 702 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 703 clocks = <&scu ASPEED_CLK_APB>; 704 }; 705 706 i2c3: i2c@200 { 707 #address-cells = <1>; 708 #size-cells = <0>; 709 #interrupt-cells = <1>; 710 711 reg = <0x200 0x40 0xC60 0x20>; 712 compatible = "aspeed,ast2600-i2c-bus"; 713 bus-frequency = <100000>; 714 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 715 clocks = <&scu ASPEED_CLK_APB>; 716 }; 717 718 i2c4: i2c@280 { 719 #address-cells = <1>; 720 #size-cells = <0>; 721 #interrupt-cells = <1>; 722 723 reg = <0x280 0x80 0xC80 0x20>; 724 compatible = "aspeed,ast2600-i2c-bus"; 725 bus-frequency = <100000>; 726 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 727 clocks = <&scu ASPEED_CLK_APB>; 728 }; 729 730 i2c5: i2c@300 { 731 #address-cells = <1>; 732 #size-cells = <0>; 733 #interrupt-cells = <1>; 734 735 reg = <0x300 0x40 0xCA0 0x20>; 736 compatible = "aspeed,ast2600-i2c-bus"; 737 bus-frequency = <100000>; 738 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 739 clocks = <&scu ASPEED_CLK_APB>; 740 }; 741 742 i2c6: i2c@380 { 743 #address-cells = <1>; 744 #size-cells = <0>; 745 #interrupt-cells = <1>; 746 747 reg = <0x380 0x80 0xCC0 0x20>; 748 compatible = "aspeed,ast2600-i2c-bus"; 749 bus-frequency = <100000>; 750 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 751 clocks = <&scu ASPEED_CLK_APB>; 752 }; 753 754 i2c7: i2c@400 { 755 #address-cells = <1>; 756 #size-cells = <0>; 757 #interrupt-cells = <1>; 758 759 reg = <0x400 0x80 0xCE0 0x20>; 760 compatible = "aspeed,ast2600-i2c-bus"; 761 bus-frequency = <100000>; 762 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 763 clocks = <&scu ASPEED_CLK_APB>; 764 }; 765 766 i2c8: i2c@480 { 767 #address-cells = <1>; 768 #size-cells = <0>; 769 #interrupt-cells = <1>; 770 771 reg = <0x480 0x80 0xD00 0x20>; 772 compatible = "aspeed,ast2600-i2c-bus"; 773 bus-frequency = <100000>; 774 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 775 clocks = <&scu ASPEED_CLK_APB>; 776 }; 777 778 i2c9: i2c@500 { 779 #address-cells = <1>; 780 #size-cells = <0>; 781 #interrupt-cells = <1>; 782 783 reg = <0x500 0x80 0xD20 0x20>; 784 compatible = "aspeed,ast2600-i2c-bus"; 785 bus-frequency = <100000>; 786 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 787 clocks = <&scu ASPEED_CLK_APB>; 788 status = "disabled"; 789 }; 790 791 i2c10: i2c@580 { 792 #address-cells = <1>; 793 #size-cells = <0>; 794 #interrupt-cells = <1>; 795 796 reg = <0x580 0x80 0xD40 0x20>; 797 compatible = "aspeed,ast2600-i2c-bus"; 798 bus-frequency = <100000>; 799 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 800 clocks = <&scu ASPEED_CLK_APB>; 801 status = "disabled"; 802 }; 803 804 i2c11: i2c@600 { 805 #address-cells = <1>; 806 #size-cells = <0>; 807 #interrupt-cells = <1>; 808 809 reg = <0x600 0x80 0xD60 0x20>; 810 compatible = "aspeed,ast2600-i2c-bus"; 811 bus-frequency = <100000>; 812 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 813 clocks = <&scu ASPEED_CLK_APB>; 814 status = "disabled"; 815 }; 816 817 i2c12: i2c@680 { 818 #address-cells = <1>; 819 #size-cells = <0>; 820 #interrupt-cells = <1>; 821 822 reg = <0x680 0x80 0xD80 0x20>; 823 compatible = "aspeed,ast2600-i2c-bus"; 824 bus-frequency = <100000>; 825 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 826 clocks = <&scu ASPEED_CLK_APB>; 827 status = "disabled"; 828 }; 829 830 i2c13: i2c@700 { 831 #address-cells = <1>; 832 #size-cells = <0>; 833 #interrupt-cells = <1>; 834 835 reg = <0x700 0x80 0xDA0 0x20>; 836 compatible = "aspeed,ast2600-i2c-bus"; 837 bus-frequency = <100000>; 838 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 839 clocks = <&scu ASPEED_CLK_APB>; 840 status = "disabled"; 841 }; 842 843 i2c14: i2c@780 { 844 #address-cells = <1>; 845 #size-cells = <0>; 846 #interrupt-cells = <1>; 847 848 reg = <0x780 0x80 0xDC0 0x20>; 849 compatible = "aspeed,ast2600-i2c-bus"; 850 bus-frequency = <100000>; 851 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 852 clocks = <&scu ASPEED_CLK_APB>; 853 status = "disabled"; 854 }; 855 856 i2c15: i2c@800 { 857 #address-cells = <1>; 858 #size-cells = <0>; 859 #interrupt-cells = <1>; 860 861 reg = <0x800 0x80 0xDE0 0x20>; 862 compatible = "aspeed,ast2600-i2c-bus"; 863 bus-frequency = <100000>; 864 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 865 clocks = <&scu ASPEED_CLK_APB>; 866 status = "disabled"; 867 }; 868 869}; 870 871&pinctrl { 872 pinctrl_acpi_default: acpi_default { 873 function = "ACPI"; 874 groups = "ACPI"; 875 }; 876 877 pinctrl_adc0_default: adc0_default { 878 function = "ADC0"; 879 groups = "ADC0"; 880 }; 881 882 pinctrl_adc1_default: adc1_default { 883 function = "ADC1"; 884 groups = "ADC1"; 885 }; 886 887 pinctrl_adc10_default: adc10_default { 888 function = "ADC10"; 889 groups = "ADC10"; 890 }; 891 892 pinctrl_adc11_default: adc11_default { 893 function = "ADC11"; 894 groups = "ADC11"; 895 }; 896 897 pinctrl_adc12_default: adc12_default { 898 function = "ADC12"; 899 groups = "ADC12"; 900 }; 901 902 pinctrl_adc13_default: adc13_default { 903 function = "ADC13"; 904 groups = "ADC13"; 905 }; 906 907 pinctrl_adc14_default: adc14_default { 908 function = "ADC14"; 909 groups = "ADC14"; 910 }; 911 912 pinctrl_adc15_default: adc15_default { 913 function = "ADC15"; 914 groups = "ADC15"; 915 }; 916 917 pinctrl_adc2_default: adc2_default { 918 function = "ADC2"; 919 groups = "ADC2"; 920 }; 921 922 pinctrl_adc3_default: adc3_default { 923 function = "ADC3"; 924 groups = "ADC3"; 925 }; 926 927 pinctrl_adc4_default: adc4_default { 928 function = "ADC4"; 929 groups = "ADC4"; 930 }; 931 932 pinctrl_adc5_default: adc5_default { 933 function = "ADC5"; 934 groups = "ADC5"; 935 }; 936 937 pinctrl_adc6_default: adc6_default { 938 function = "ADC6"; 939 groups = "ADC6"; 940 }; 941 942 pinctrl_adc7_default: adc7_default { 943 function = "ADC7"; 944 groups = "ADC7"; 945 }; 946 947 pinctrl_adc8_default: adc8_default { 948 function = "ADC8"; 949 groups = "ADC8"; 950 }; 951 952 pinctrl_adc9_default: adc9_default { 953 function = "ADC9"; 954 groups = "ADC9"; 955 }; 956 957 pinctrl_bmcint_default: bmcint_default { 958 function = "BMCINT"; 959 groups = "BMCINT"; 960 }; 961 962 pinctrl_ddcclk_default: ddcclk_default { 963 function = "DDCCLK"; 964 groups = "DDCCLK"; 965 }; 966 967 pinctrl_ddcdat_default: ddcdat_default { 968 function = "DDCDAT"; 969 groups = "DDCDAT"; 970 }; 971 972 pinctrl_espi_default: espi_default { 973 function = "ESPI"; 974 groups = "ESPI"; 975 }; 976 977 pinctrl_fwspics1_default: fwspics1_default { 978 function = "FWSPICS1"; 979 groups = "FWSPICS1"; 980 }; 981 982 pinctrl_fwspics2_default: fwspics2_default { 983 function = "FWSPICS2"; 984 groups = "FWSPICS2"; 985 }; 986 987 pinctrl_gpid0_default: gpid0_default { 988 function = "GPID0"; 989 groups = "GPID0"; 990 }; 991 992 pinctrl_gpid2_default: gpid2_default { 993 function = "GPID2"; 994 groups = "GPID2"; 995 }; 996 997 pinctrl_gpid4_default: gpid4_default { 998 function = "GPID4"; 999 groups = "GPID4"; 1000 }; 1001 1002 pinctrl_gpid6_default: gpid6_default { 1003 function = "GPID6"; 1004 groups = "GPID6"; 1005 }; 1006 1007 pinctrl_gpie0_default: gpie0_default { 1008 function = "GPIE0"; 1009 groups = "GPIE0"; 1010 }; 1011 1012 pinctrl_gpie2_default: gpie2_default { 1013 function = "GPIE2"; 1014 groups = "GPIE2"; 1015 }; 1016 1017 pinctrl_gpie4_default: gpie4_default { 1018 function = "GPIE4"; 1019 groups = "GPIE4"; 1020 }; 1021 1022 pinctrl_gpie6_default: gpie6_default { 1023 function = "GPIE6"; 1024 groups = "GPIE6"; 1025 }; 1026 1027 pinctrl_i2c10_default: i2c10_default { 1028 function = "I2C10"; 1029 groups = "I2C10"; 1030 }; 1031 1032 pinctrl_i2c11_default: i2c11_default { 1033 function = "I2C11"; 1034 groups = "I2C11"; 1035 }; 1036 1037 pinctrl_i2c12_default: i2c12_default { 1038 function = "I2C12"; 1039 groups = "I2C12"; 1040 }; 1041 1042 pinctrl_i2c13_default: i2c13_default { 1043 function = "I2C13"; 1044 groups = "I2C13"; 1045 }; 1046 1047 pinctrl_i2c14_default: i2c14_default { 1048 function = "I2C14"; 1049 groups = "I2C14"; 1050 }; 1051 1052 pinctrl_i2c3_default: i2c3_default { 1053 function = "I2C3"; 1054 groups = "I2C3"; 1055 }; 1056 1057 pinctrl_i2c4_default: i2c4_default { 1058 function = "I2C4"; 1059 groups = "I2C4"; 1060 }; 1061 1062 pinctrl_i2c5_default: i2c5_default { 1063 function = "I2C5"; 1064 groups = "I2C5"; 1065 }; 1066 1067 pinctrl_i2c6_default: i2c6_default { 1068 function = "I2C6"; 1069 groups = "I2C6"; 1070 }; 1071 1072 pinctrl_i2c7_default: i2c7_default { 1073 function = "I2C7"; 1074 groups = "I2C7"; 1075 }; 1076 1077 pinctrl_i2c8_default: i2c8_default { 1078 function = "I2C8"; 1079 groups = "I2C8"; 1080 }; 1081 1082 pinctrl_i2c9_default: i2c9_default { 1083 function = "I2C9"; 1084 groups = "I2C9"; 1085 }; 1086 1087 pinctrl_lad0_default: lad0_default { 1088 function = "LAD0"; 1089 groups = "LAD0"; 1090 }; 1091 1092 pinctrl_lad1_default: lad1_default { 1093 function = "LAD1"; 1094 groups = "LAD1"; 1095 }; 1096 1097 pinctrl_lad2_default: lad2_default { 1098 function = "LAD2"; 1099 groups = "LAD2"; 1100 }; 1101 1102 pinctrl_lad3_default: lad3_default { 1103 function = "LAD3"; 1104 groups = "LAD3"; 1105 }; 1106 1107 pinctrl_lclk_default: lclk_default { 1108 function = "LCLK"; 1109 groups = "LCLK"; 1110 }; 1111 1112 pinctrl_lframe_default: lframe_default { 1113 function = "LFRAME"; 1114 groups = "LFRAME"; 1115 }; 1116 1117 pinctrl_lpchc_default: lpchc_default { 1118 function = "LPCHC"; 1119 groups = "LPCHC"; 1120 }; 1121 1122 pinctrl_lpcpd_default: lpcpd_default { 1123 function = "LPCPD"; 1124 groups = "LPCPD"; 1125 }; 1126 1127 pinctrl_lpcplus_default: lpcplus_default { 1128 function = "LPCPLUS"; 1129 groups = "LPCPLUS"; 1130 }; 1131 1132 pinctrl_lpcpme_default: lpcpme_default { 1133 function = "LPCPME"; 1134 groups = "LPCPME"; 1135 }; 1136 1137 pinctrl_lpcrst_default: lpcrst_default { 1138 function = "LPCRST"; 1139 groups = "LPCRST"; 1140 }; 1141 1142 pinctrl_lpcsmi_default: lpcsmi_default { 1143 function = "LPCSMI"; 1144 groups = "LPCSMI"; 1145 }; 1146 1147 pinctrl_lsirq_default: lsirq_default { 1148 function = "LSIRQ"; 1149 groups = "LSIRQ"; 1150 }; 1151 1152 pinctrl_mac1link_default: mac1link_default { 1153 function = "MAC1LINK"; 1154 groups = "MAC1LINK"; 1155 }; 1156 1157 pinctrl_mac2link_default: mac2link_default { 1158 function = "MAC2LINK"; 1159 groups = "MAC2LINK"; 1160 }; 1161 1162 pinctrl_mac3link_default: mac3link_default { 1163 function = "MAC3LINK"; 1164 groups = "MAC3LINK"; 1165 }; 1166 1167 pinctrl_mac4link_default: mac4link_default { 1168 function = "MAC4LINK"; 1169 groups = "MAC4LINK"; 1170 }; 1171 1172 pinctrl_mdio1_default: mdio1_default { 1173 function = "MDIO1"; 1174 groups = "MDIO1"; 1175 }; 1176 1177 pinctrl_mdio2_default: mdio2_default { 1178 function = "MDIO2"; 1179 groups = "MDIO2"; 1180 }; 1181 1182 pinctrl_mdio3_default: mdio3_default { 1183 function = "MDIO3"; 1184 groups = "MDIO3"; 1185 }; 1186 1187 pinctrl_mdio4_default: mdio4_default { 1188 function = "MDIO4"; 1189 groups = "MDIO4"; 1190 }; 1191 1192 pinctrl_ncts1_default: ncts1_default { 1193 function = "NCTS1"; 1194 groups = "NCTS1"; 1195 }; 1196 1197 pinctrl_ncts2_default: ncts2_default { 1198 function = "NCTS2"; 1199 groups = "NCTS2"; 1200 }; 1201 1202 pinctrl_ncts3_default: ncts3_default { 1203 function = "NCTS3"; 1204 groups = "NCTS3"; 1205 }; 1206 1207 pinctrl_ncts4_default: ncts4_default { 1208 function = "NCTS4"; 1209 groups = "NCTS4"; 1210 }; 1211 1212 pinctrl_ndcd1_default: ndcd1_default { 1213 function = "NDCD1"; 1214 groups = "NDCD1"; 1215 }; 1216 1217 pinctrl_ndcd2_default: ndcd2_default { 1218 function = "NDCD2"; 1219 groups = "NDCD2"; 1220 }; 1221 1222 pinctrl_ndcd3_default: ndcd3_default { 1223 function = "NDCD3"; 1224 groups = "NDCD3"; 1225 }; 1226 1227 pinctrl_ndcd4_default: ndcd4_default { 1228 function = "NDCD4"; 1229 groups = "NDCD4"; 1230 }; 1231 1232 pinctrl_ndsr1_default: ndsr1_default { 1233 function = "NDSR1"; 1234 groups = "NDSR1"; 1235 }; 1236 1237 pinctrl_ndsr2_default: ndsr2_default { 1238 function = "NDSR2"; 1239 groups = "NDSR2"; 1240 }; 1241 1242 pinctrl_ndsr3_default: ndsr3_default { 1243 function = "NDSR3"; 1244 groups = "NDSR3"; 1245 }; 1246 1247 pinctrl_ndsr4_default: ndsr4_default { 1248 function = "NDSR4"; 1249 groups = "NDSR4"; 1250 }; 1251 1252 pinctrl_ndtr1_default: ndtr1_default { 1253 function = "NDTR1"; 1254 groups = "NDTR1"; 1255 }; 1256 1257 pinctrl_ndtr2_default: ndtr2_default { 1258 function = "NDTR2"; 1259 groups = "NDTR2"; 1260 }; 1261 1262 pinctrl_ndtr3_default: ndtr3_default { 1263 function = "NDTR3"; 1264 groups = "NDTR3"; 1265 }; 1266 1267 pinctrl_ndtr4_default: ndtr4_default { 1268 function = "NDTR4"; 1269 groups = "NDTR4"; 1270 }; 1271 1272 pinctrl_nri1_default: nri1_default { 1273 function = "NRI1"; 1274 groups = "NRI1"; 1275 }; 1276 1277 pinctrl_nri2_default: nri2_default { 1278 function = "NRI2"; 1279 groups = "NRI2"; 1280 }; 1281 1282 pinctrl_nri3_default: nri3_default { 1283 function = "NRI3"; 1284 groups = "NRI3"; 1285 }; 1286 1287 pinctrl_nri4_default: nri4_default { 1288 function = "NRI4"; 1289 groups = "NRI4"; 1290 }; 1291 1292 pinctrl_nrts1_default: nrts1_default { 1293 function = "NRTS1"; 1294 groups = "NRTS1"; 1295 }; 1296 1297 pinctrl_nrts2_default: nrts2_default { 1298 function = "NRTS2"; 1299 groups = "NRTS2"; 1300 }; 1301 1302 pinctrl_nrts3_default: nrts3_default { 1303 function = "NRTS3"; 1304 groups = "NRTS3"; 1305 }; 1306 1307 pinctrl_nrts4_default: nrts4_default { 1308 function = "NRTS4"; 1309 groups = "NRTS4"; 1310 }; 1311 1312 pinctrl_oscclk_default: oscclk_default { 1313 function = "OSCCLK"; 1314 groups = "OSCCLK"; 1315 }; 1316 1317 pinctrl_pewake_default: pewake_default { 1318 function = "PEWAKE"; 1319 groups = "PEWAKE"; 1320 }; 1321 1322 pinctrl_pnor_default: pnor_default { 1323 function = "PNOR"; 1324 groups = "PNOR"; 1325 }; 1326 1327 pinctrl_pwm0_default: pwm0_default { 1328 function = "PWM0"; 1329 groups = "PWM0"; 1330 }; 1331 1332 pinctrl_pwm1_default: pwm1_default { 1333 function = "PWM1"; 1334 groups = "PWM1"; 1335 }; 1336 1337 pinctrl_pwm2_default: pwm2_default { 1338 function = "PWM2"; 1339 groups = "PWM2"; 1340 }; 1341 1342 pinctrl_pwm3_default: pwm3_default { 1343 function = "PWM3"; 1344 groups = "PWM3"; 1345 }; 1346 1347 pinctrl_pwm4_default: pwm4_default { 1348 function = "PWM4"; 1349 groups = "PWM4"; 1350 }; 1351 1352 pinctrl_pwm5_default: pwm5_default { 1353 function = "PWM5"; 1354 groups = "PWM5"; 1355 }; 1356 1357 pinctrl_pwm6_default: pwm6_default { 1358 function = "PWM6"; 1359 groups = "PWM6"; 1360 }; 1361 1362 pinctrl_pwm7_default: pwm7_default { 1363 function = "PWM7"; 1364 groups = "PWM7"; 1365 }; 1366 1367 pinctrl_rgmii1_default: rgmii1_default { 1368 function = "RGMII1"; 1369 groups = "RGMII1"; 1370 }; 1371 1372 pinctrl_rgmii2_default: rgmii2_default { 1373 function = "RGMII2"; 1374 groups = "RGMII2"; 1375 }; 1376 1377 pinctrl_rmii1_default: rmii1_default { 1378 function = "RMII1"; 1379 groups = "RMII1"; 1380 }; 1381 1382 pinctrl_rmii2_default: rmii2_default { 1383 function = "RMII2"; 1384 groups = "RMII2"; 1385 }; 1386 1387 pinctrl_rxd1_default: rxd1_default { 1388 function = "RXD1"; 1389 groups = "RXD1"; 1390 }; 1391 1392 pinctrl_rxd2_default: rxd2_default { 1393 function = "RXD2"; 1394 groups = "RXD2"; 1395 }; 1396 1397 pinctrl_rxd3_default: rxd3_default { 1398 function = "RXD3"; 1399 groups = "RXD3"; 1400 }; 1401 1402 pinctrl_rxd4_default: rxd4_default { 1403 function = "RXD4"; 1404 groups = "RXD4"; 1405 }; 1406 1407 pinctrl_salt1_default: salt1_default { 1408 function = "SALT1"; 1409 groups = "SALT1"; 1410 }; 1411 1412 pinctrl_salt10_default: salt10_default { 1413 function = "SALT10"; 1414 groups = "SALT10"; 1415 }; 1416 1417 pinctrl_salt11_default: salt11_default { 1418 function = "SALT11"; 1419 groups = "SALT11"; 1420 }; 1421 1422 pinctrl_salt12_default: salt12_default { 1423 function = "SALT12"; 1424 groups = "SALT12"; 1425 }; 1426 1427 pinctrl_salt13_default: salt13_default { 1428 function = "SALT13"; 1429 groups = "SALT13"; 1430 }; 1431 1432 pinctrl_salt14_default: salt14_default { 1433 function = "SALT14"; 1434 groups = "SALT14"; 1435 }; 1436 1437 pinctrl_salt2_default: salt2_default { 1438 function = "SALT2"; 1439 groups = "SALT2"; 1440 }; 1441 1442 pinctrl_salt3_default: salt3_default { 1443 function = "SALT3"; 1444 groups = "SALT3"; 1445 }; 1446 1447 pinctrl_salt4_default: salt4_default { 1448 function = "SALT4"; 1449 groups = "SALT4"; 1450 }; 1451 1452 pinctrl_salt5_default: salt5_default { 1453 function = "SALT5"; 1454 groups = "SALT5"; 1455 }; 1456 1457 pinctrl_salt6_default: salt6_default { 1458 function = "SALT6"; 1459 groups = "SALT6"; 1460 }; 1461 1462 pinctrl_salt7_default: salt7_default { 1463 function = "SALT7"; 1464 groups = "SALT7"; 1465 }; 1466 1467 pinctrl_salt8_default: salt8_default { 1468 function = "SALT8"; 1469 groups = "SALT8"; 1470 }; 1471 1472 pinctrl_salt9_default: salt9_default { 1473 function = "SALT9"; 1474 groups = "SALT9"; 1475 }; 1476 1477 pinctrl_scl1_default: scl1_default { 1478 function = "SCL1"; 1479 groups = "SCL1"; 1480 }; 1481 1482 pinctrl_scl2_default: scl2_default { 1483 function = "SCL2"; 1484 groups = "SCL2"; 1485 }; 1486 1487 pinctrl_sd1_default: sd1_default { 1488 function = "SD1"; 1489 groups = "SD1"; 1490 }; 1491 1492 pinctrl_sd2_default: sd2_default { 1493 function = "SD2"; 1494 groups = "SD2"; 1495 }; 1496 1497 pinctrl_emmc_default: emmc_default { 1498 function = "EMMC"; 1499 groups = "EMMC"; 1500 }; 1501 1502 pinctrl_sda1_default: sda1_default { 1503 function = "SDA1"; 1504 groups = "SDA1"; 1505 }; 1506 1507 pinctrl_sda2_default: sda2_default { 1508 function = "SDA2"; 1509 groups = "SDA2"; 1510 }; 1511 1512 pinctrl_sgps1_default: sgps1_default { 1513 function = "SGPS1"; 1514 groups = "SGPS1"; 1515 }; 1516 1517 pinctrl_sgps2_default: sgps2_default { 1518 function = "SGPS2"; 1519 groups = "SGPS2"; 1520 }; 1521 1522 pinctrl_sioonctrl_default: sioonctrl_default { 1523 function = "SIOONCTRL"; 1524 groups = "SIOONCTRL"; 1525 }; 1526 1527 pinctrl_siopbi_default: siopbi_default { 1528 function = "SIOPBI"; 1529 groups = "SIOPBI"; 1530 }; 1531 1532 pinctrl_siopbo_default: siopbo_default { 1533 function = "SIOPBO"; 1534 groups = "SIOPBO"; 1535 }; 1536 1537 pinctrl_siopwreq_default: siopwreq_default { 1538 function = "SIOPWREQ"; 1539 groups = "SIOPWREQ"; 1540 }; 1541 1542 pinctrl_siopwrgd_default: siopwrgd_default { 1543 function = "SIOPWRGD"; 1544 groups = "SIOPWRGD"; 1545 }; 1546 1547 pinctrl_sios3_default: sios3_default { 1548 function = "SIOS3"; 1549 groups = "SIOS3"; 1550 }; 1551 1552 pinctrl_sios5_default: sios5_default { 1553 function = "SIOS5"; 1554 groups = "SIOS5"; 1555 }; 1556 1557 pinctrl_siosci_default: siosci_default { 1558 function = "SIOSCI"; 1559 groups = "SIOSCI"; 1560 }; 1561 1562 pinctrl_spi1_default: spi1_default { 1563 function = "SPI1"; 1564 groups = "SPI1"; 1565 }; 1566 1567 pinctrl_spi1cs1_default: spi1cs1_default { 1568 function = "SPI1CS1"; 1569 groups = "SPI1CS1"; 1570 }; 1571 1572 pinctrl_spi1debug_default: spi1debug_default { 1573 function = "SPI1DEBUG"; 1574 groups = "SPI1DEBUG"; 1575 }; 1576 1577 pinctrl_spi1passthru_default: spi1passthru_default { 1578 function = "SPI1PASSTHRU"; 1579 groups = "SPI1PASSTHRU"; 1580 }; 1581 1582 pinctrl_spi2ck_default: spi2ck_default { 1583 function = "SPI2CK"; 1584 groups = "SPI2CK"; 1585 }; 1586 1587 pinctrl_spi2cs0_default: spi2cs0_default { 1588 function = "SPI2CS0"; 1589 groups = "SPI2CS0"; 1590 }; 1591 1592 pinctrl_spi2cs1_default: spi2cs1_default { 1593 function = "SPI2CS1"; 1594 groups = "SPI2CS1"; 1595 }; 1596 1597 pinctrl_spi2miso_default: spi2miso_default { 1598 function = "SPI2MISO"; 1599 groups = "SPI2MISO"; 1600 }; 1601 1602 pinctrl_spi2mosi_default: spi2mosi_default { 1603 function = "SPI2MOSI"; 1604 groups = "SPI2MOSI"; 1605 }; 1606 1607 pinctrl_timer3_default: timer3_default { 1608 function = "TIMER3"; 1609 groups = "TIMER3"; 1610 }; 1611 1612 pinctrl_timer4_default: timer4_default { 1613 function = "TIMER4"; 1614 groups = "TIMER4"; 1615 }; 1616 1617 pinctrl_timer5_default: timer5_default { 1618 function = "TIMER5"; 1619 groups = "TIMER5"; 1620 }; 1621 1622 pinctrl_timer6_default: timer6_default { 1623 function = "TIMER6"; 1624 groups = "TIMER6"; 1625 }; 1626 1627 pinctrl_timer7_default: timer7_default { 1628 function = "TIMER7"; 1629 groups = "TIMER7"; 1630 }; 1631 1632 pinctrl_timer8_default: timer8_default { 1633 function = "TIMER8"; 1634 groups = "TIMER8"; 1635 }; 1636 1637 pinctrl_txd1_default: txd1_default { 1638 function = "TXD1"; 1639 groups = "TXD1"; 1640 }; 1641 1642 pinctrl_txd2_default: txd2_default { 1643 function = "TXD2"; 1644 groups = "TXD2"; 1645 }; 1646 1647 pinctrl_txd3_default: txd3_default { 1648 function = "TXD3"; 1649 groups = "TXD3"; 1650 }; 1651 1652 pinctrl_txd4_default: txd4_default { 1653 function = "TXD4"; 1654 groups = "TXD4"; 1655 }; 1656 1657 pinctrl_uart6_default: uart6_default { 1658 function = "UART6"; 1659 groups = "UART6"; 1660 }; 1661 1662 pinctrl_usbcki_default: usbcki_default { 1663 function = "USBCKI"; 1664 groups = "USBCKI"; 1665 }; 1666 1667 pinctrl_usb2ah_default: usb2ah_default { 1668 function = "USB2AH"; 1669 groups = "USB2AH"; 1670 }; 1671 1672 pinctrl_usb11bhid_default: usb11bhid_default { 1673 function = "USB11BHID"; 1674 groups = "USB11BHID"; 1675 }; 1676 1677 pinctrl_usb2bh_default: usb2bh_default { 1678 function = "USB2BH"; 1679 groups = "USB2BH"; 1680 }; 1681 1682 pinctrl_vgabiosrom_default: vgabiosrom_default { 1683 function = "VGABIOSROM"; 1684 groups = "VGABIOSROM"; 1685 }; 1686 1687 pinctrl_vgahs_default: vgahs_default { 1688 function = "VGAHS"; 1689 groups = "VGAHS"; 1690 }; 1691 1692 pinctrl_vgavs_default: vgavs_default { 1693 function = "VGAVS"; 1694 groups = "VGAVS"; 1695 }; 1696 1697 pinctrl_vpi24_default: vpi24_default { 1698 function = "VPI24"; 1699 groups = "VPI24"; 1700 }; 1701 1702 pinctrl_vpo_default: vpo_default { 1703 function = "VPO"; 1704 groups = "VPO"; 1705 }; 1706 1707 pinctrl_wdtrst1_default: wdtrst1_default { 1708 function = "WDTRST1"; 1709 groups = "WDTRST1"; 1710 }; 1711 1712 pinctrl_wdtrst2_default: wdtrst2_default { 1713 function = "WDTRST2"; 1714 groups = "WDTRST2"; 1715 }; 1716}; 1717