1// SPDX-License-Identifier: GPL-2.0+ 2#include <dt-bindings/interrupt-controller/arm-gic.h> 3#include <dt-bindings/gpio/aspeed-gpio.h> 4#include "skeleton.dtsi" 5 6/ { 7 model = "Aspeed BMC"; 8 compatible = "aspeed,ast2600"; 9 #address-cells = <1>; 10 #size-cells = <1>; 11 interrupt-parent = <&gic>; 12 13 aliases { 14 i2c0 = &i2c0; 15 i2c1 = &i2c1; 16 i2c2 = &i2c2; 17 i2c3 = &i2c3; 18 i2c4 = &i2c4; 19 i2c5 = &i2c5; 20 i2c6 = &i2c6; 21 i2c7 = &i2c7; 22 i2c8 = &i2c8; 23 i2c9 = &i2c9; 24 i2c10 = &i2c10; 25 i2c11 = &i2c11; 26 i2c12 = &i2c12; 27 i2c13 = &i2c13; 28 i2c14 = &i2c14; 29 i2c15 = &i2c15; 30 serial0 = &uart1; 31 serial1 = &uart2; 32 serial2 = &uart3; 33 serial3 = &uart4; 34 serial4 = &uart5; 35 serial5 = &uart6; 36 serial6 = &uart7; 37 serial7 = &uart8; 38 serial8 = &uart9; 39 serial9 = &uart10; 40 serial10 = &uart11; 41 serial11 = &uart12; 42 serial12 = &uart13; 43 }; 44 45 cpus { 46 #address-cells = <1>; 47 #size-cells = <0>; 48 enable-method = "aspeed,ast2600-smp"; 49 50 cpu@0 { 51 compatible = "arm,cortex-a7"; 52 device_type = "cpu"; 53 reg = <0>; 54 }; 55 56 cpu@1 { 57 compatible = "arm,cortex-a7"; 58 device_type = "cpu"; 59 reg = <1>; 60 }; 61 62 }; 63 64 timer { 65 compatible = "arm,armv7-timer"; 66 interrupt-parent = <&gic>; 67 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 68 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 69 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 70 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 71 }; 72 73 reserved-memory { 74 #address-cells = <1>; 75 #size-cells = <1>; 76 ranges; 77 78 gfx_memory: framebuffer { 79 size = <0x01000000>; 80 alignment = <0x01000000>; 81 compatible = "shared-dma-pool"; 82 reusable; 83 }; 84 85 video_memory: video { 86 size = <0x04000000>; 87 alignment = <0x01000000>; 88 compatible = "shared-dma-pool"; 89 no-map; 90 }; 91 }; 92 93 ahb { 94 compatible = "simple-bus"; 95 #address-cells = <1>; 96 #size-cells = <1>; 97 device_type = "soc"; 98 ranges; 99 100 gic: interrupt-controller@40461000 { 101 compatible = "arm,cortex-a7-gic"; 102 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 103 #interrupt-cells = <3>; 104 interrupt-controller; 105 interrupt-parent = <&gic>; 106 reg = <0x40461000 0x1000>, 107 <0x40462000 0x1000>, 108 <0x40464000 0x2000>, 109 <0x40466000 0x2000>; 110 }; 111 112 ahbc: ahbc@1e600000 { 113 compatible = "aspeed,aspeed-ahbc"; 114 reg = < 0x1e600000 0x100>; 115 }; 116 117 fmc: flash-controller@1e620000 { 118 reg = <0x1e620000 0xc4 119 0x20000000 0x10000000>; 120 #address-cells = <1>; 121 #size-cells = <0>; 122 compatible = "aspeed,ast2600-fmc"; 123 status = "disabled"; 124 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 125 clocks = <&scu ASPEED_CLK_AHB>; 126 num-cs = <3>; 127 flash@0 { 128 reg = < 0 >; 129 compatible = "jedec,spi-nor"; 130 status = "disabled"; 131 }; 132 flash@1 { 133 reg = < 1 >; 134 compatible = "jedec,spi-nor"; 135 status = "disabled"; 136 }; 137 flash@2 { 138 reg = < 2 >; 139 compatible = "jedec,spi-nor"; 140 status = "disabled"; 141 }; 142 }; 143 144 spi1: flash-controller@1e630000 { 145 reg = <0x1e630000 0xc4 146 0x30000000 0x10000000>; 147 #address-cells = <1>; 148 #size-cells = <0>; 149 compatible = "aspeed,ast2600-spi"; 150 clocks = <&scu ASPEED_CLK_AHB>; 151 num-cs = <2>; 152 status = "disabled"; 153 flash@0 { 154 reg = < 0 >; 155 compatible = "jedec,spi-nor"; 156 status = "disabled"; 157 }; 158 flash@1 { 159 reg = < 1 >; 160 compatible = "jedec,spi-nor"; 161 status = "disabled"; 162 }; 163 }; 164 165 spi2: flash-controller@1e631000 { 166 reg = <0x1e631000 0xc4 167 0x50000000 0x10000000>; 168 #address-cells = <1>; 169 #size-cells = <0>; 170 compatible = "aspeed,ast2600-spi"; 171 clocks = <&scu ASPEED_CLK_AHB>; 172 num-cs = <3>; 173 status = "disabled"; 174 flash@0 { 175 reg = < 0 >; 176 compatible = "jedec,spi-nor"; 177 status = "disabled"; 178 }; 179 flash@1 { 180 reg = < 1 >; 181 compatible = "jedec,spi-nor"; 182 status = "disabled"; 183 }; 184 flash@2 { 185 reg = < 2 >; 186 compatible = "jedec,spi-nor"; 187 status = "disabled"; 188 }; 189 }; 190 191 edac: sdram@1e6e0000 { 192 compatible = "aspeed,ast2600-sdram-edac"; 193 reg = <0x1e6e0000 0x174>; 194 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 195 }; 196 197 mdio: ethernet@1e650000 { 198 compatible = "aspeed,aspeed-mdio"; 199 reg = <0x1e650000 0x40>; 200 resets = <&rst ASPEED_RESET_MII>; 201 status = "disabled"; 202 }; 203 204 mac0: ftgmac@1e660000 { 205 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 206 reg = <0x1e660000 0x180>, <0x1e650000 0x4>; 207 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 208 clocks = <&scu ASPEED_CLK_GATE_MAC1CLK>; 209 status = "disabled"; 210 }; 211 212 mac1: ftgmac@1e680000 { 213 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 214 reg = <0x1e680000 0x180>, <0x1e650008 0x4>; 215 #address-cells = <1>; 216 #size-cells = <0>; 217 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 218 clocks = <&scu ASPEED_CLK_GATE_MAC2CLK>; 219 status = "disabled"; 220 }; 221 222 mac2: ftgmac@1e670000 { 223 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 224 reg = <0x1e670000 0x180>, <0x1e650010 0x4>; 225 #address-cells = <1>; 226 #size-cells = <0>; 227 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 228 clocks = <&scu ASPEED_CLK_GATE_MAC3CLK>; 229 status = "disabled"; 230 }; 231 232 mac3: ftgmac@1e690000 { 233 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 234 reg = <0x1e690000 0x180>, <0x1e650018 0x4>; 235 #address-cells = <1>; 236 #size-cells = <0>; 237 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 238 clocks = <&scu ASPEED_CLK_GATE_MAC4CLK>; 239 status = "disabled"; 240 }; 241 242 vhub: usb-vhub@1e6a0000 { 243 compatible = "aspeed,ast2600-usb-vhub"; 244 reg = <0x1e6a0000 0x350>; 245 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 246 clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>; 247 resets = <&rst ASPEED_RESET_EHCI_P1>; 248 pinctrl-names = "default"; 249 pinctrl-0 = <&pinctrl_usb2ad_default>; 250 status = "disabled"; 251 }; 252 253 ehci0: usb@1e6a1000 { 254 compatible = "aspeed,aspeed-ehci", "usb-ehci"; 255 reg = <0x1e6a1000 0x100>; 256 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 257 clocks = <&scu ASPEED_CLK_GATE_USBPORT1CLK>; 258 pinctrl-names = "default"; 259 pinctrl-0 = <&pinctrl_usb2ah_default>; 260 status = "disabled"; 261 }; 262 263 ehci1: usb@1e6a3000 { 264 compatible = "aspeed,aspeed-ehci", "usb-ehci"; 265 reg = <0x1e6a3000 0x100>; 266 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 267 clocks = <&scu ASPEED_CLK_GATE_USBPORT2CLK>; 268 pinctrl-names = "default"; 269 pinctrl-0 = <&pinctrl_usb2bh_default>; 270 status = "disabled"; 271 }; 272 273 apb { 274 compatible = "simple-bus"; 275 #address-cells = <1>; 276 #size-cells = <1>; 277 ranges; 278 u-boot,dm-pre-reloc; 279 280 syscon: syscon@1e6e2000 { 281 compatible = "aspeed,g6-scu", "syscon", "simple-mfd"; 282 reg = <0x1e6e2000 0x1000>; 283 #address-cells = <1>; 284 #size-cells = <1>; 285 #clock-cells = <1>; 286 #reset-cells = <1>; 287 ranges = <0 0x1e6e2000 0x1000>; 288 u-boot,dm-pre-reloc; 289 290 pinctrl: pinctrl { 291 compatible = "aspeed,g6-pinctrl"; 292 aspeed,external-nodes = <&gfx &lhc>; 293 u-boot,dm-pre-reloc; 294 }; 295 296 vga_scratch: scratch { 297 compatible = "aspeed,bmc-misc"; 298 }; 299 300 scu_ic0: interrupt-controller@0 { 301 #interrupt-cells = <1>; 302 compatible = "aspeed,ast2600-scu-ic"; 303 reg = <0x560 0x10>; 304 interrupt-parent = <&gic>; 305 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 306 interrupt-controller; 307 }; 308 309 scu_ic1: interrupt-controller@1 { 310 #interrupt-cells = <1>; 311 compatible = "aspeed,ast2600-scu-ic"; 312 reg = <0x570 0x10>; 313 interrupt-parent = <&gic>; 314 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 315 interrupt-controller; 316 }; 317 318 }; 319 320 hace: hace@1e6d0000 { 321 compatible = "aspeed,ast2600-hace"; 322 reg = <0x1e6d0000 0x200>; 323 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 324 clocks = <&scu ASPEED_CLK_GATE_YCLK>; 325 clock-names = "yclk"; 326 status = "disabled"; 327 }; 328 329 acry: acry@1e6fa000 { 330 compatible = "aspeed,ast2600-acry"; 331 reg = <0x1e6fa000 0x1000>, 332 <0x1e710000 0x20000>; 333 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 334 clocks = <&scu ASPEED_CLK_GATE_RSAECCCLK>; 335 clock-names = "rsaeccclk"; 336 status = "disabled"; 337 }; 338 339 smp-memram@0 { 340 compatible = "aspeed,ast2600-smpmem", "syscon"; 341 reg = <0x1e6e2180 0x40>; 342 }; 343 344 gfx: display@1e6e6000 { 345 compatible = "aspeed,ast2500-gfx", "syscon"; 346 reg = <0x1e6e6000 0x1000>; 347 reg-io-width = <4>; 348 }; 349 350 sdhci: sdhci@1e740000 { 351 #interrupt-cells = <1>; 352 compatible = "aspeed,aspeed-sdhci-irq", "simple-mfd"; 353 reg = <0x1e740000 0x1000>; 354 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 355 interrupt-controller; 356 clocks = <&scu ASPEED_CLK_GATE_SDCLK>, <&scu ASPEED_CLK_GATE_SDEXTCLK>; 357 clock-names = "ctrlclk", "extclk"; 358 #address-cells = <1>; 359 #size-cells = <1>; 360 ranges = <0x0 0x1e740000 0x1000>; 361 362 sdhci_slot0: sdhci_slot0@100 { 363 compatible = "aspeed,sdhci-ast2600"; 364 reg = <0x100 0x100>; 365 interrupts = <0>; 366 interrupt-parent = <&sdhci>; 367 sdhci,auto-cmd12; 368 clocks = <&scu ASPEED_CLK_SDIO>; 369 status = "disabled"; 370 }; 371 372 sdhci_slot1: sdhci_slot1@200 { 373 compatible = "aspeed,sdhci-ast2600"; 374 reg = <0x200 0x100>; 375 interrupts = <1>; 376 interrupt-parent = <&sdhci>; 377 sdhci,auto-cmd12; 378 clocks = <&scu ASPEED_CLK_SDIO>; 379 status = "disabled"; 380 }; 381 }; 382 383 emmc: emmc@1e750000 { 384 #interrupt-cells = <1>; 385 compatible = "aspeed,aspeed-emmc-irq", "simple-mfd"; 386 reg = <0x1e750000 0x1000>; 387 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 388 interrupt-controller; 389 clocks = <&scu ASPEED_CLK_GATE_EMMCCLK>, <&scu ASPEED_CLK_GATE_EMMCEXTCLK>; 390 clock-names = "ctrlclk", "extclk"; 391 #address-cells = <1>; 392 #size-cells = <1>; 393 ranges = <0x0 0x1e750000 0x1000>; 394 395 emmc_slot0: emmc_slot0@100 { 396 compatible = "aspeed,emmc-ast2600"; 397 reg = <0x100 0x100>; 398 interrupts = <0>; 399 interrupt-parent = <&emmc>; 400 clocks = <&scu ASPEED_CLK_EMMC>; 401 status = "disabled"; 402 }; 403 }; 404 405 pcie_phy0: phy@1e6ed000 { 406 compatible = "aspeed,ast2600-pcie_phy"; 407 reg = <0x1e6ed000 0x100>; 408 resets = <&rst ASPEED_RESET_PCIE_DEV_O>; 409 pinctrl-names = "default"; 410 pinctrl-0 = <&pinctrl_pcie0rc_default>; 411 status = "disabled"; 412 }; 413 414 pcie_phy1: phy@1e6ed200 { 415 compatible = "aspeed,ast2600-pcie_phy"; 416 reg = <0x1e6ed200 0x100>; 417 resets = <&rst ASPEED_RESET_PCIE_RC_O>; 418 pinctrl-names = "default"; 419 pinctrl-0 = <&pinctrl_pcie1rc_default>; 420 status = "disabled"; 421 }; 422 423 pcie_bridge: pcie@1e770000 { 424 compatible = "aspeed,ast2600-pcie"; 425 #address-cells = <3>; 426 #size-cells = <2>; 427 reg = <0x1e770000 0x100>; 428 ranges = <0x81000000 0x0 0x0 0x0 0x0 0x10000 /* downstream I/O */ 429 0x82000000 0x0 0x60000000 0x60000000 0x0 0x20000000>; /* non-prefetchable memory */ 430 device_type = "pci"; 431 bus-range = <0x00 0xff>; 432 resets = <&rst ASPEED_RESET_H2X>, <&rst ASPEED_RESET_PCIE_DEV_O>, <&rst ASPEED_RESET_PCIE_RC_O>; 433 slot0-handle = <&pcie_phy0>; 434 slot1-handle = <&pcie_phy1>; 435 status = "disabled"; 436 }; 437 438 gpio0: gpio@1e780000 { 439 compatible = "aspeed,ast2600-gpio"; 440 reg = <0x1e780000 0x400>; 441 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 442 #gpio-cells = <2>; 443 gpio-controller; 444 interrupt-controller; 445 gpio-ranges = <&pinctrl 0 0 208>; 446 ngpios = <208>; 447 }; 448 449 gpio1: gpio@1e780800 { 450 compatible = "aspeed,ast2600-gpio"; 451 reg = <0x1e780800 0x800>; 452 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 453 #gpio-cells = <2>; 454 gpio-controller; 455 interrupt-controller; 456 gpio-ranges = <&pinctrl 0 208 36>; 457 ngpios = <36>; 458 }; 459 460 uart1: serial@1e783000 { 461 compatible = "ns16550a"; 462 reg = <0x1e783000 0x20>; 463 reg-shift = <2>; 464 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 465 clocks = <&scu ASPEED_CLK_GATE_UART1CLK>; 466 clock-frequency = <1846154>; 467 no-loopback-test; 468 u-boot,dm-pre-reloc; 469 pinctrl-names = "default"; 470 pinctrl-0 = <&pinctrl_txd1_default &pinctrl_rxd1_default>; 471 status = "disabled"; 472 }; 473 474 uart5: serial@1e784000 { 475 compatible = "ns16550a"; 476 reg = <0x1e784000 0x1000>; 477 reg-shift = <2>; 478 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 479 clocks = <&scu ASPEED_CLK_GATE_UART5CLK>; 480 clock-frequency = <1846154>; 481 no-loopback-test; 482 u-boot,dm-pre-reloc; 483 status = "disabled"; 484 }; 485 486 wdt1: watchdog@1e785000 { 487 compatible = "aspeed,ast2600-wdt"; 488 reg = <0x1e785000 0x40>; 489 }; 490 491 wdt2: watchdog@1e785040 { 492 compatible = "aspeed,ast2600-wdt"; 493 reg = <0x1e785040 0x40>; 494 }; 495 496 wdt3: watchdog@1e785080 { 497 compatible = "aspeed,ast2600-wdt"; 498 reg = <0x1e785080 0x40>; 499 }; 500 501 wdt4: watchdog@1e7850C0 { 502 compatible = "aspeed,ast2600-wdt"; 503 reg = <0x1e7850C0 0x40>; 504 }; 505 506 lpc: lpc@1e789000 { 507 compatible = "aspeed,ast-lpc", "simple-mfd", "syscon"; 508 reg = <0x1e789000 0x200>; 509 510 #address-cells = <1>; 511 #size-cells = <1>; 512 ranges = <0x0 0x1e789000 0x1000>; 513 514 lpc_bmc: lpc-bmc@0 { 515 compatible = "aspeed,ast2600-lpc-bmc", "simple-mfd", "syscon"; 516 reg = <0x0 0x80>; 517 reg-io-width = <4>; 518 #address-cells = <1>; 519 #size-cells = <1>; 520 ranges = <0x0 0x0 0x80>; 521 522 kcs1: kcs1@0 { 523 compatible = "aspeed,ast2600-kcs-bmc"; 524 reg = <0x0 0x80>; 525 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 526 kcs_chan = <1>; 527 kcs_addr = <0xCA0>; 528 status = "disabled"; 529 }; 530 531 kcs2: kcs2@0 { 532 compatible = "aspeed,ast2600-kcs-bmc"; 533 reg = <0x0 0x80>; 534 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 535 kcs_chan = <2>; 536 kcs_addr = <0xCA8>; 537 status = "disabled"; 538 }; 539 540 kcs3: kcs3@0 { 541 compatible = "aspeed,ast2600-kcs-bmc"; 542 reg = <0x0 0x80>; 543 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 544 kcs_chan = <3>; 545 kcs_addr = <0xCA2>; 546 }; 547 548 kcs4: kcs4@0 { 549 compatible = "aspeed,ast2600-kcs-bmc"; 550 reg = <0x0 0x120>; 551 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 552 kcs_chan = <4>; 553 kcs_addr = <0xCA4>; 554 status = "disabled"; 555 }; 556 557 }; 558 559 lpc_host: lpc-host@80 { 560 compatible = "aspeed,ast2600-lpc-host", "simple-mfd", "syscon"; 561 reg = <0x80 0x1e0>; 562 reg-io-width = <4>; 563 564 #address-cells = <1>; 565 #size-cells = <1>; 566 ranges = <0x0 0x80 0x1e0>; 567 568 lpc_ctrl: lpc-ctrl@0 { 569 compatible = "aspeed,ast2600-lpc-ctrl"; 570 reg = <0x0 0x80>; 571 status = "disabled"; 572 }; 573 574 lpc_snoop: lpc-snoop@0 { 575 compatible = "aspeed,ast2600-lpc-snoop"; 576 reg = <0x0 0x80>; 577 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 578 snoop-ports = <0x80>; 579 status = "disabled"; 580 }; 581 582 lhc: lhc@20 { 583 compatible = "aspeed,ast2600-lhc"; 584 reg = <0x20 0x24 0x48 0x8>; 585 }; 586 587 lpc_reset: reset-controller@18 { 588 compatible = "aspeed,ast2600-lpc-reset"; 589 reg = <0x18 0x4>; 590 #reset-cells = <1>; 591 status = "disabled"; 592 }; 593 594 ibt: ibt@c0 { 595 compatible = "aspeed,ast2600-ibt-bmc"; 596 reg = <0xc0 0x18>; 597 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 598 status = "disabled"; 599 }; 600 601 sio_regs: regs { 602 compatible = "aspeed,bmc-misc"; 603 }; 604 605 mbox: mbox@180 { 606 compatible = "aspeed,ast2600-mbox"; 607 reg = <0x180 0x5c>; 608 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 609 #mbox-cells = <1>; 610 status = "disabled"; 611 }; 612 }; 613 }; 614 615 uart2: serial@1e78d000 { 616 compatible = "ns16550a"; 617 reg = <0x1e78d000 0x20>; 618 reg-shift = <2>; 619 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 620 clocks = <&scu ASPEED_CLK_GATE_UART2CLK>; 621 clock-frequency = <1846154>; 622 no-loopback-test; 623 pinctrl-names = "default"; 624 pinctrl-0 = <&pinctrl_txd2_default &pinctrl_rxd2_default>; 625 u-boot,dm-pre-reloc; 626 status = "disabled"; 627 }; 628 629 uart3: serial@1e78e000 { 630 compatible = "ns16550a"; 631 reg = <0x1e78e000 0x20>; 632 reg-shift = <2>; 633 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 634 clocks = <&scu ASPEED_CLK_GATE_UART3CLK>; 635 clock-frequency = <1846154>; 636 no-loopback-test; 637 pinctrl-names = "default"; 638 pinctrl-0 = <&pinctrl_txd3_default &pinctrl_rxd3_default>; 639 u-boot,dm-pre-reloc; 640 status = "disabled"; 641 }; 642 643 uart4: serial@1e78f000 { 644 compatible = "ns16550a"; 645 reg = <0x1e78f000 0x20>; 646 reg-shift = <2>; 647 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 648 clocks = <&scu ASPEED_CLK_GATE_UART4CLK>; 649 clock-frequency = <1846154>; 650 no-loopback-test; 651 u-boot,dm-pre-reloc; 652 pinctrl-names = "default"; 653 pinctrl-0 = <&pinctrl_txd4_default &pinctrl_rxd4_default>; 654 status = "disabled"; 655 }; 656 657 i2c: bus@1e78a000 { 658 compatible = "simple-bus"; 659 #address-cells = <1>; 660 #size-cells = <1>; 661 ranges = <0 0x1e78a000 0x1000>; 662 }; 663 664 fsim0: fsi@1e79b000 { 665 compatible = "aspeed,ast2600-fsi-master", "fsi-master"; 666 reg = <0x1e79b000 0x94>; 667 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 668 pinctrl-names = "default"; 669 pinctrl-0 = <&pinctrl_fsi1_default>; 670 clocks = <&scu ASPEED_CLK_GATE_FSICLK>; 671 status = "disabled"; 672 }; 673 674 fsim1: fsi@1e79b100 { 675 compatible = "aspeed,ast2600-fsi-master", "fsi-master"; 676 reg = <0x1e79b100 0x94>; 677 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 678 pinctrl-names = "default"; 679 pinctrl-0 = <&pinctrl_fsi2_default>; 680 clocks = <&scu ASPEED_CLK_GATE_FSICLK>; 681 status = "disabled"; 682 }; 683 684 uart6: serial@1e790000 { 685 compatible = "ns16550a"; 686 reg = <0x1e790000 0x20>; 687 reg-shift = <2>; 688 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 689 clocks = <&scu ASPEED_CLK_GATE_UART6CLK>; 690 clock-frequency = <1846154>; 691 no-loopback-test; 692 status = "disabled"; 693 }; 694 695 uart7: serial@1e790100 { 696 compatible = "ns16550a"; 697 reg = <0x1e790100 0x20>; 698 reg-shift = <2>; 699 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 700 clocks = <&scu ASPEED_CLK_GATE_UART7CLK>; 701 clock-frequency = <1846154>; 702 no-loopback-test; 703 status = "disabled"; 704 }; 705 706 uart8: serial@1e790200 { 707 compatible = "ns16550a"; 708 reg = <0x1e790200 0x20>; 709 reg-shift = <2>; 710 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 711 clocks = <&scu ASPEED_CLK_GATE_UART8CLK>; 712 clock-frequency = <1846154>; 713 no-loopback-test; 714 status = "disabled"; 715 }; 716 717 uart9: serial@1e790300 { 718 compatible = "ns16550a"; 719 reg = <0x1e790300 0x20>; 720 reg-shift = <2>; 721 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 722 clocks = <&scu ASPEED_CLK_GATE_UART9CLK>; 723 clock-frequency = <1846154>; 724 no-loopback-test; 725 status = "disabled"; 726 }; 727 728 uart10: serial@1e790400 { 729 compatible = "ns16550a"; 730 reg = <0x1e790400 0x20>; 731 reg-shift = <2>; 732 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 733 clocks = <&scu ASPEED_CLK_GATE_UART10CLK>; 734 clock-frequency = <1846154>; 735 no-loopback-test; 736 status = "disabled"; 737 }; 738 739 uart11: serial@1e790500 { 740 compatible = "ns16550a"; 741 reg = <0x1e790400 0x20>; 742 reg-shift = <2>; 743 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 744 clocks = <&scu ASPEED_CLK_GATE_UART11CLK>; 745 clock-frequency = <1846154>; 746 no-loopback-test; 747 status = "disabled"; 748 }; 749 750 uart12: serial@1e790600 { 751 compatible = "ns16550a"; 752 reg = <0x1e790600 0x20>; 753 reg-shift = <2>; 754 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 755 clocks = <&scu ASPEED_CLK_GATE_UART12CLK>; 756 clock-frequency = <1846154>; 757 no-loopback-test; 758 status = "disabled"; 759 }; 760 761 uart13: serial@1e790700 { 762 compatible = "ns16550a"; 763 reg = <0x1e790700 0x20>; 764 reg-shift = <2>; 765 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 766 clocks = <&scu ASPEED_CLK_GATE_UART13CLK>; 767 clock-frequency = <1846154>; 768 no-loopback-test; 769 status = "disabled"; 770 }; 771 772 display_port: dp@1e6eb000 { 773 compatible = "aspeed,ast2600-displayport"; 774 reg = <0x1e6eb000 0x200>; 775 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 776 resets = <&rst ASPEED_RESET_DP>, <&rst ASPEED_RESET_DP_MCU>; 777 status = "disabled"; 778 }; 779 780 }; 781 782 }; 783 784}; 785 786&i2c { 787 i2cglobal: i2cg@00 { 788 compatible = "aspeed,ast2600-i2c-global"; 789 reg = <0x0 0x40>; 790 resets = <&rst ASPEED_RESET_I2C>; 791 }; 792 793 i2c0: i2c@80 { 794 #address-cells = <1>; 795 #size-cells = <0>; 796 #interrupt-cells = <1>; 797 798 reg = <0x80 0x80 0xC00 0x20>; 799 compatible = "aspeed,ast2600-i2c-bus"; 800 bus-frequency = <100000>; 801 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 802 clocks = <&scu ASPEED_CLK_APB2>; 803 pinctrl-names = "default"; 804 pinctrl-0 = <&pinctrl_i2c1_default>; 805 status = "disabled"; 806 }; 807 808 i2c1: i2c@100 { 809 #address-cells = <1>; 810 #size-cells = <0>; 811 #interrupt-cells = <1>; 812 813 reg = <0x100 0x80 0xC20 0x20>; 814 compatible = "aspeed,ast2600-i2c-bus"; 815 bus-frequency = <100000>; 816 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 817 clocks = <&scu ASPEED_CLK_APB2>; 818 pinctrl-names = "default"; 819 pinctrl-0 = <&pinctrl_i2c2_default>; 820 status = "disabled"; 821 }; 822 823 i2c2: i2c@180 { 824 #address-cells = <1>; 825 #size-cells = <0>; 826 #interrupt-cells = <1>; 827 828 reg = <0x180 0x80 0xC40 0x20>; 829 compatible = "aspeed,ast2600-i2c-bus"; 830 bus-frequency = <100000>; 831 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 832 clocks = <&scu ASPEED_CLK_APB2>; 833 pinctrl-names = "default"; 834 pinctrl-0 = <&pinctrl_i2c3_default>; 835 }; 836 837 i2c3: i2c@200 { 838 #address-cells = <1>; 839 #size-cells = <0>; 840 #interrupt-cells = <1>; 841 842 reg = <0x200 0x40 0xC60 0x20>; 843 compatible = "aspeed,ast2600-i2c-bus"; 844 bus-frequency = <100000>; 845 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 846 clocks = <&scu ASPEED_CLK_APB2>; 847 pinctrl-names = "default"; 848 pinctrl-0 = <&pinctrl_i2c4_default>; 849 }; 850 851 i2c4: i2c@280 { 852 #address-cells = <1>; 853 #size-cells = <0>; 854 #interrupt-cells = <1>; 855 856 reg = <0x280 0x80 0xC80 0x20>; 857 compatible = "aspeed,ast2600-i2c-bus"; 858 bus-frequency = <100000>; 859 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 860 clocks = <&scu ASPEED_CLK_APB2>; 861 pinctrl-names = "default"; 862 pinctrl-0 = <&pinctrl_i2c5_default>; 863 }; 864 865 i2c5: i2c@300 { 866 #address-cells = <1>; 867 #size-cells = <0>; 868 #interrupt-cells = <1>; 869 870 reg = <0x300 0x40 0xCA0 0x20>; 871 compatible = "aspeed,ast2600-i2c-bus"; 872 bus-frequency = <100000>; 873 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 874 clocks = <&scu ASPEED_CLK_APB2>; 875 pinctrl-names = "default"; 876 pinctrl-0 = <&pinctrl_i2c6_default>; 877 }; 878 879 i2c6: i2c@380 { 880 #address-cells = <1>; 881 #size-cells = <0>; 882 #interrupt-cells = <1>; 883 884 reg = <0x380 0x80 0xCC0 0x20>; 885 compatible = "aspeed,ast2600-i2c-bus"; 886 bus-frequency = <100000>; 887 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 888 clocks = <&scu ASPEED_CLK_APB2>; 889 pinctrl-names = "default"; 890 pinctrl-0 = <&pinctrl_i2c7_default>; 891 }; 892 893 i2c7: i2c@400 { 894 #address-cells = <1>; 895 #size-cells = <0>; 896 #interrupt-cells = <1>; 897 898 reg = <0x400 0x80 0xCE0 0x20>; 899 compatible = "aspeed,ast2600-i2c-bus"; 900 bus-frequency = <100000>; 901 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 902 clocks = <&scu ASPEED_CLK_APB2>; 903 pinctrl-names = "default"; 904 pinctrl-0 = <&pinctrl_i2c8_default>; 905 }; 906 907 i2c8: i2c@480 { 908 #address-cells = <1>; 909 #size-cells = <0>; 910 #interrupt-cells = <1>; 911 912 reg = <0x480 0x80 0xD00 0x20>; 913 compatible = "aspeed,ast2600-i2c-bus"; 914 bus-frequency = <100000>; 915 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 916 clocks = <&scu ASPEED_CLK_APB2>; 917 pinctrl-names = "default"; 918 pinctrl-0 = <&pinctrl_i2c9_default>; 919 }; 920 921 i2c9: i2c@500 { 922 #address-cells = <1>; 923 #size-cells = <0>; 924 #interrupt-cells = <1>; 925 926 reg = <0x500 0x80 0xD20 0x20>; 927 compatible = "aspeed,ast2600-i2c-bus"; 928 bus-frequency = <100000>; 929 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 930 clocks = <&scu ASPEED_CLK_APB2>; 931 pinctrl-names = "default"; 932 pinctrl-0 = <&pinctrl_i2c10_default>; 933 status = "disabled"; 934 }; 935 936 i2c10: i2c@580 { 937 #address-cells = <1>; 938 #size-cells = <0>; 939 #interrupt-cells = <1>; 940 941 reg = <0x580 0x80 0xD40 0x20>; 942 compatible = "aspeed,ast2600-i2c-bus"; 943 bus-frequency = <100000>; 944 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 945 clocks = <&scu ASPEED_CLK_APB2>; 946 pinctrl-names = "default"; 947 pinctrl-0 = <&pinctrl_i2c11_default>; 948 status = "disabled"; 949 }; 950 951 i2c11: i2c@600 { 952 #address-cells = <1>; 953 #size-cells = <0>; 954 #interrupt-cells = <1>; 955 956 reg = <0x600 0x80 0xD60 0x20>; 957 compatible = "aspeed,ast2600-i2c-bus"; 958 bus-frequency = <100000>; 959 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 960 clocks = <&scu ASPEED_CLK_APB2>; 961 pinctrl-names = "default"; 962 pinctrl-0 = <&pinctrl_i2c12_default>; 963 status = "disabled"; 964 }; 965 966 i2c12: i2c@680 { 967 #address-cells = <1>; 968 #size-cells = <0>; 969 #interrupt-cells = <1>; 970 971 reg = <0x680 0x80 0xD80 0x20>; 972 compatible = "aspeed,ast2600-i2c-bus"; 973 bus-frequency = <100000>; 974 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 975 clocks = <&scu ASPEED_CLK_APB2>; 976 pinctrl-names = "default"; 977 pinctrl-0 = <&pinctrl_i2c13_default>; 978 status = "disabled"; 979 }; 980 981 i2c13: i2c@700 { 982 #address-cells = <1>; 983 #size-cells = <0>; 984 #interrupt-cells = <1>; 985 986 reg = <0x700 0x80 0xDA0 0x20>; 987 compatible = "aspeed,ast2600-i2c-bus"; 988 bus-frequency = <100000>; 989 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 990 clocks = <&scu ASPEED_CLK_APB2>; 991 pinctrl-names = "default"; 992 pinctrl-0 = <&pinctrl_i2c14_default>; 993 status = "disabled"; 994 }; 995 996 i2c14: i2c@780 { 997 #address-cells = <1>; 998 #size-cells = <0>; 999 #interrupt-cells = <1>; 1000 1001 reg = <0x780 0x80 0xDC0 0x20>; 1002 compatible = "aspeed,ast2600-i2c-bus"; 1003 bus-frequency = <100000>; 1004 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 1005 clocks = <&scu ASPEED_CLK_APB2>; 1006 pinctrl-names = "default"; 1007 pinctrl-0 = <&pinctrl_i2c15_default>; 1008 status = "disabled"; 1009 }; 1010 1011 i2c15: i2c@800 { 1012 #address-cells = <1>; 1013 #size-cells = <0>; 1014 #interrupt-cells = <1>; 1015 1016 reg = <0x800 0x80 0xDE0 0x20>; 1017 compatible = "aspeed,ast2600-i2c-bus"; 1018 bus-frequency = <100000>; 1019 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 1020 clocks = <&scu ASPEED_CLK_APB2>; 1021 pinctrl-names = "default"; 1022 pinctrl-0 = <&pinctrl_i2c16_default>; 1023 status = "disabled"; 1024 }; 1025 1026}; 1027 1028&pinctrl { 1029 u-boot,dm-pre-reloc; 1030 1031 pinctrl_fmcquad_default: fmcquad_default { 1032 function = "FMCQUAD"; 1033 groups = "FMCQUAD"; 1034 }; 1035 1036 pinctrl_spi1_default: spi1_default { 1037 function = "SPI1"; 1038 groups = "SPI1"; 1039 }; 1040 1041 pinctrl_spi1abr_default: spi1abr_default { 1042 function = "SPI1ABR"; 1043 groups = "SPI1ABR"; 1044 }; 1045 1046 pinctrl_spi1cs1_default: spi1cs1_default { 1047 function = "SPI1CS1"; 1048 groups = "SPI1CS1"; 1049 }; 1050 1051 pinctrl_spi1wp_default: spi1wp_default { 1052 function = "SPI1WP"; 1053 groups = "SPI1WP"; 1054 }; 1055 1056 pinctrl_spi1quad_default: spi1quad_default { 1057 function = "SPI1QUAD"; 1058 groups = "SPI1QUAD"; 1059 }; 1060 1061 pinctrl_spi2_default: spi2_default { 1062 function = "SPI2"; 1063 groups = "SPI2"; 1064 }; 1065 1066 pinctrl_spi2cs1_default: spi2cs1_default { 1067 function = "SPI2CS1"; 1068 groups = "SPI2CS1"; 1069 }; 1070 1071 pinctrl_spi2cs2_default: spi2cs2_default { 1072 function = "SPI2CS2"; 1073 groups = "SPI2CS2"; 1074 }; 1075 1076 pinctrl_spi2quad_default: spi2quad_default { 1077 function = "SPI2QUAD"; 1078 groups = "SPI2QUAD"; 1079 }; 1080 1081 pinctrl_acpi_default: acpi_default { 1082 function = "ACPI"; 1083 groups = "ACPI"; 1084 }; 1085 1086 pinctrl_adc0_default: adc0_default { 1087 function = "ADC0"; 1088 groups = "ADC0"; 1089 }; 1090 1091 pinctrl_adc1_default: adc1_default { 1092 function = "ADC1"; 1093 groups = "ADC1"; 1094 }; 1095 1096 pinctrl_adc10_default: adc10_default { 1097 function = "ADC10"; 1098 groups = "ADC10"; 1099 }; 1100 1101 pinctrl_adc11_default: adc11_default { 1102 function = "ADC11"; 1103 groups = "ADC11"; 1104 }; 1105 1106 pinctrl_adc12_default: adc12_default { 1107 function = "ADC12"; 1108 groups = "ADC12"; 1109 }; 1110 1111 pinctrl_adc13_default: adc13_default { 1112 function = "ADC13"; 1113 groups = "ADC13"; 1114 }; 1115 1116 pinctrl_adc14_default: adc14_default { 1117 function = "ADC14"; 1118 groups = "ADC14"; 1119 }; 1120 1121 pinctrl_adc15_default: adc15_default { 1122 function = "ADC15"; 1123 groups = "ADC15"; 1124 }; 1125 1126 pinctrl_adc2_default: adc2_default { 1127 function = "ADC2"; 1128 groups = "ADC2"; 1129 }; 1130 1131 pinctrl_adc3_default: adc3_default { 1132 function = "ADC3"; 1133 groups = "ADC3"; 1134 }; 1135 1136 pinctrl_adc4_default: adc4_default { 1137 function = "ADC4"; 1138 groups = "ADC4"; 1139 }; 1140 1141 pinctrl_adc5_default: adc5_default { 1142 function = "ADC5"; 1143 groups = "ADC5"; 1144 }; 1145 1146 pinctrl_adc6_default: adc6_default { 1147 function = "ADC6"; 1148 groups = "ADC6"; 1149 }; 1150 1151 pinctrl_adc7_default: adc7_default { 1152 function = "ADC7"; 1153 groups = "ADC7"; 1154 }; 1155 1156 pinctrl_adc8_default: adc8_default { 1157 function = "ADC8"; 1158 groups = "ADC8"; 1159 }; 1160 1161 pinctrl_adc9_default: adc9_default { 1162 function = "ADC9"; 1163 groups = "ADC9"; 1164 }; 1165 1166 pinctrl_bmcint_default: bmcint_default { 1167 function = "BMCINT"; 1168 groups = "BMCINT"; 1169 }; 1170 1171 pinctrl_ddcclk_default: ddcclk_default { 1172 function = "DDCCLK"; 1173 groups = "DDCCLK"; 1174 }; 1175 1176 pinctrl_ddcdat_default: ddcdat_default { 1177 function = "DDCDAT"; 1178 groups = "DDCDAT"; 1179 }; 1180 1181 pinctrl_espi_default: espi_default { 1182 function = "ESPI"; 1183 groups = "ESPI"; 1184 }; 1185 1186 pinctrl_fsi1_default: fsi1_default { 1187 function = "FSI1"; 1188 groups = "FSI1"; 1189 }; 1190 1191 pinctrl_fsi2_default: fsi2_default { 1192 function = "FSI2"; 1193 groups = "FSI2"; 1194 }; 1195 1196 pinctrl_fwspics1_default: fwspics1_default { 1197 function = "FWSPICS1"; 1198 groups = "FWSPICS1"; 1199 }; 1200 1201 pinctrl_fwspics2_default: fwspics2_default { 1202 function = "FWSPICS2"; 1203 groups = "FWSPICS2"; 1204 }; 1205 1206 pinctrl_gpid0_default: gpid0_default { 1207 function = "GPID0"; 1208 groups = "GPID0"; 1209 }; 1210 1211 pinctrl_gpid2_default: gpid2_default { 1212 function = "GPID2"; 1213 groups = "GPID2"; 1214 }; 1215 1216 pinctrl_gpid4_default: gpid4_default { 1217 function = "GPID4"; 1218 groups = "GPID4"; 1219 }; 1220 1221 pinctrl_gpid6_default: gpid6_default { 1222 function = "GPID6"; 1223 groups = "GPID6"; 1224 }; 1225 1226 pinctrl_gpie0_default: gpie0_default { 1227 function = "GPIE0"; 1228 groups = "GPIE0"; 1229 }; 1230 1231 pinctrl_gpie2_default: gpie2_default { 1232 function = "GPIE2"; 1233 groups = "GPIE2"; 1234 }; 1235 1236 pinctrl_gpie4_default: gpie4_default { 1237 function = "GPIE4"; 1238 groups = "GPIE4"; 1239 }; 1240 1241 pinctrl_gpie6_default: gpie6_default { 1242 function = "GPIE6"; 1243 groups = "GPIE6"; 1244 }; 1245 1246 pinctrl_i2c1_default: i2c1_default { 1247 function = "I2C1"; 1248 groups = "I2C1"; 1249 }; 1250 1251 pinctrl_i2c2_default: i2c2_default { 1252 function = "I2C2"; 1253 groups = "I2C2"; 1254 }; 1255 1256 pinctrl_i2c3_default: i2c3_default { 1257 function = "I2C3"; 1258 groups = "I2C3"; 1259 }; 1260 1261 pinctrl_i2c4_default: i2c4_default { 1262 function = "I2C4"; 1263 groups = "I2C4"; 1264 }; 1265 1266 pinctrl_i2c5_default: i2c5_default { 1267 function = "I2C5"; 1268 groups = "I2C5"; 1269 }; 1270 1271 pinctrl_i2c6_default: i2c6_default { 1272 function = "I2C6"; 1273 groups = "I2C6"; 1274 }; 1275 1276 pinctrl_i2c7_default: i2c7_default { 1277 function = "I2C7"; 1278 groups = "I2C7"; 1279 }; 1280 1281 pinctrl_i2c8_default: i2c8_default { 1282 function = "I2C8"; 1283 groups = "I2C8"; 1284 }; 1285 1286 pinctrl_i2c9_default: i2c9_default { 1287 function = "I2C9"; 1288 groups = "I2C9"; 1289 }; 1290 1291 pinctrl_i2c10_default: i2c10_default { 1292 function = "I2C10"; 1293 groups = "I2C10"; 1294 }; 1295 1296 pinctrl_i2c11_default: i2c11_default { 1297 function = "I2C11"; 1298 groups = "I2C11"; 1299 }; 1300 1301 pinctrl_i2c12_default: i2c12_default { 1302 function = "I2C12"; 1303 groups = "I2C12"; 1304 }; 1305 1306 pinctrl_i2c13_default: i2c13_default { 1307 function = "I2C13"; 1308 groups = "I2C13"; 1309 }; 1310 1311 pinctrl_i2c14_default: i2c14_default { 1312 function = "I2C14"; 1313 groups = "I2C14"; 1314 }; 1315 1316 pinctrl_i2c15_default: i2c15_default { 1317 function = "I2C15"; 1318 groups = "I2C15"; 1319 }; 1320 1321 pinctrl_i2c16_default: i2c16_default { 1322 function = "I2C16"; 1323 groups = "I2C16"; 1324 }; 1325 1326 pinctrl_si2c1_default: si2c1_default { 1327 function = "SI2C1"; 1328 groups = "SI2C1"; 1329 }; 1330 1331 pinctrl_si2c2_default: si2c2_default { 1332 function = "SI2C2"; 1333 groups = "SI2C2"; 1334 }; 1335 1336 pinctrl_si2c3_default: si2c3_default { 1337 function = "SI2C3"; 1338 groups = "SI2C3"; 1339 }; 1340 1341 pinctrl_si2c4_default: si2c4_default { 1342 function = "SI2C4"; 1343 groups = "SI2C4"; 1344 }; 1345 1346 pinctrl_si2c5_default: si2c5_default { 1347 function = "SI2C5"; 1348 groups = "SI2C5"; 1349 }; 1350 1351 pinctrl_si2c6_default: si2c6_default { 1352 function = "SI2C6"; 1353 groups = "SI2C6"; 1354 }; 1355 1356 pinctrl_si2c7_default: si2c7_default { 1357 function = "SI2C7"; 1358 groups = "SI2C7"; 1359 }; 1360 1361 pinctrl_si2c8_default: si2c8_default { 1362 function = "SI2C8"; 1363 groups = "SI2C8"; 1364 }; 1365 1366 pinctrl_si2c9_default: si2c9_default { 1367 function = "SI2C9"; 1368 groups = "SI2C9"; 1369 }; 1370 1371 pinctrl_si2c10_default: si2c10_default { 1372 function = "SI2C10"; 1373 groups = "SI2C10"; 1374 }; 1375 1376 pinctrl_lad0_default: lad0_default { 1377 function = "LAD0"; 1378 groups = "LAD0"; 1379 }; 1380 1381 pinctrl_lad1_default: lad1_default { 1382 function = "LAD1"; 1383 groups = "LAD1"; 1384 }; 1385 1386 pinctrl_lad2_default: lad2_default { 1387 function = "LAD2"; 1388 groups = "LAD2"; 1389 }; 1390 1391 pinctrl_lad3_default: lad3_default { 1392 function = "LAD3"; 1393 groups = "LAD3"; 1394 }; 1395 1396 pinctrl_lclk_default: lclk_default { 1397 function = "LCLK"; 1398 groups = "LCLK"; 1399 }; 1400 1401 pinctrl_lframe_default: lframe_default { 1402 function = "LFRAME"; 1403 groups = "LFRAME"; 1404 }; 1405 1406 pinctrl_lpchc_default: lpchc_default { 1407 function = "LPCHC"; 1408 groups = "LPCHC"; 1409 }; 1410 1411 pinctrl_lpcpd_default: lpcpd_default { 1412 function = "LPCPD"; 1413 groups = "LPCPD"; 1414 }; 1415 1416 pinctrl_lpcplus_default: lpcplus_default { 1417 function = "LPCPLUS"; 1418 groups = "LPCPLUS"; 1419 }; 1420 1421 pinctrl_lpcpme_default: lpcpme_default { 1422 function = "LPCPME"; 1423 groups = "LPCPME"; 1424 }; 1425 1426 pinctrl_lpcrst_default: lpcrst_default { 1427 function = "LPCRST"; 1428 groups = "LPCRST"; 1429 }; 1430 1431 pinctrl_lpcsmi_default: lpcsmi_default { 1432 function = "LPCSMI"; 1433 groups = "LPCSMI"; 1434 }; 1435 1436 pinctrl_lsirq_default: lsirq_default { 1437 function = "LSIRQ"; 1438 groups = "LSIRQ"; 1439 }; 1440 1441 pinctrl_mac1link_default: mac1link_default { 1442 function = "MAC1LINK"; 1443 groups = "MAC1LINK"; 1444 }; 1445 1446 pinctrl_mac2link_default: mac2link_default { 1447 function = "MAC2LINK"; 1448 groups = "MAC2LINK"; 1449 }; 1450 1451 pinctrl_mac3link_default: mac3link_default { 1452 function = "MAC3LINK"; 1453 groups = "MAC3LINK"; 1454 }; 1455 1456 pinctrl_mac4link_default: mac4link_default { 1457 function = "MAC4LINK"; 1458 groups = "MAC4LINK"; 1459 }; 1460 1461 pinctrl_mdio1_default: mdio1_default { 1462 function = "MDIO1"; 1463 groups = "MDIO1"; 1464 }; 1465 1466 pinctrl_mdio2_default: mdio2_default { 1467 function = "MDIO2"; 1468 groups = "MDIO2"; 1469 }; 1470 1471 pinctrl_mdio3_default: mdio3_default { 1472 function = "MDIO3"; 1473 groups = "MDIO3"; 1474 }; 1475 1476 pinctrl_mdio4_default: mdio4_default { 1477 function = "MDIO4"; 1478 groups = "MDIO4"; 1479 }; 1480 1481 pinctrl_rmii1_default: rmii1_default { 1482 function = "RMII1"; 1483 groups = "RMII1"; 1484 }; 1485 1486 pinctrl_rmii2_default: rmii2_default { 1487 function = "RMII2"; 1488 groups = "RMII2"; 1489 }; 1490 1491 pinctrl_rmii3_default: rmii3_default { 1492 function = "RMII3"; 1493 groups = "RMII3"; 1494 }; 1495 1496 pinctrl_rmii4_default: rmii4_default { 1497 function = "RMII4"; 1498 groups = "RMII4"; 1499 }; 1500 1501 pinctrl_rmii1rclk_default: rmii1rclk_default { 1502 function = "RMII1RCLK"; 1503 groups = "RMII1RCLK"; 1504 }; 1505 1506 pinctrl_rmii2rclk_default: rmii2rclk_default { 1507 function = "RMII2RCLK"; 1508 groups = "RMII2RCLK"; 1509 }; 1510 1511 pinctrl_rmii3rclk_default: rmii3rclk_default { 1512 function = "RMII3RCLK"; 1513 groups = "RMII3RCLK"; 1514 }; 1515 1516 pinctrl_rmii4rclk_default: rmii4rclk_default { 1517 function = "RMII4RCLK"; 1518 groups = "RMII4RCLK"; 1519 }; 1520 1521 pinctrl_ncts1_default: ncts1_default { 1522 function = "NCTS1"; 1523 groups = "NCTS1"; 1524 }; 1525 1526 pinctrl_ncts2_default: ncts2_default { 1527 function = "NCTS2"; 1528 groups = "NCTS2"; 1529 }; 1530 1531 pinctrl_ncts3_default: ncts3_default { 1532 function = "NCTS3"; 1533 groups = "NCTS3"; 1534 }; 1535 1536 pinctrl_ncts4_default: ncts4_default { 1537 function = "NCTS4"; 1538 groups = "NCTS4"; 1539 }; 1540 1541 pinctrl_ndcd1_default: ndcd1_default { 1542 function = "NDCD1"; 1543 groups = "NDCD1"; 1544 }; 1545 1546 pinctrl_ndcd2_default: ndcd2_default { 1547 function = "NDCD2"; 1548 groups = "NDCD2"; 1549 }; 1550 1551 pinctrl_ndcd3_default: ndcd3_default { 1552 function = "NDCD3"; 1553 groups = "NDCD3"; 1554 }; 1555 1556 pinctrl_ndcd4_default: ndcd4_default { 1557 function = "NDCD4"; 1558 groups = "NDCD4"; 1559 }; 1560 1561 pinctrl_ndsr1_default: ndsr1_default { 1562 function = "NDSR1"; 1563 groups = "NDSR1"; 1564 }; 1565 1566 pinctrl_ndsr2_default: ndsr2_default { 1567 function = "NDSR2"; 1568 groups = "NDSR2"; 1569 }; 1570 1571 pinctrl_ndsr3_default: ndsr3_default { 1572 function = "NDSR3"; 1573 groups = "NDSR3"; 1574 }; 1575 1576 pinctrl_ndsr4_default: ndsr4_default { 1577 function = "NDSR4"; 1578 groups = "NDSR4"; 1579 }; 1580 1581 pinctrl_ndtr1_default: ndtr1_default { 1582 function = "NDTR1"; 1583 groups = "NDTR1"; 1584 }; 1585 1586 pinctrl_ndtr2_default: ndtr2_default { 1587 function = "NDTR2"; 1588 groups = "NDTR2"; 1589 }; 1590 1591 pinctrl_ndtr3_default: ndtr3_default { 1592 function = "NDTR3"; 1593 groups = "NDTR3"; 1594 }; 1595 1596 pinctrl_ndtr4_default: ndtr4_default { 1597 function = "NDTR4"; 1598 groups = "NDTR4"; 1599 }; 1600 1601 pinctrl_nri1_default: nri1_default { 1602 function = "NRI1"; 1603 groups = "NRI1"; 1604 }; 1605 1606 pinctrl_nri2_default: nri2_default { 1607 function = "NRI2"; 1608 groups = "NRI2"; 1609 }; 1610 1611 pinctrl_nri3_default: nri3_default { 1612 function = "NRI3"; 1613 groups = "NRI3"; 1614 }; 1615 1616 pinctrl_nri4_default: nri4_default { 1617 function = "NRI4"; 1618 groups = "NRI4"; 1619 }; 1620 1621 pinctrl_nrts1_default: nrts1_default { 1622 function = "NRTS1"; 1623 groups = "NRTS1"; 1624 }; 1625 1626 pinctrl_nrts2_default: nrts2_default { 1627 function = "NRTS2"; 1628 groups = "NRTS2"; 1629 }; 1630 1631 pinctrl_nrts3_default: nrts3_default { 1632 function = "NRTS3"; 1633 groups = "NRTS3"; 1634 }; 1635 1636 pinctrl_nrts4_default: nrts4_default { 1637 function = "NRTS4"; 1638 groups = "NRTS4"; 1639 }; 1640 1641 pinctrl_oscclk_default: oscclk_default { 1642 function = "OSCCLK"; 1643 groups = "OSCCLK"; 1644 }; 1645 1646 pinctrl_pewake_default: pewake_default { 1647 function = "PEWAKE"; 1648 groups = "PEWAKE"; 1649 }; 1650 1651 pinctrl_pnor_default: pnor_default { 1652 function = "PNOR"; 1653 groups = "PNOR"; 1654 }; 1655 1656 pinctrl_pwm0_default: pwm0_default { 1657 function = "PWM0"; 1658 groups = "PWM0"; 1659 }; 1660 1661 pinctrl_pwm1_default: pwm1_default { 1662 function = "PWM1"; 1663 groups = "PWM1"; 1664 }; 1665 1666 pinctrl_pwm2_default: pwm2_default { 1667 function = "PWM2"; 1668 groups = "PWM2"; 1669 }; 1670 1671 pinctrl_pwm3_default: pwm3_default { 1672 function = "PWM3"; 1673 groups = "PWM3"; 1674 }; 1675 1676 pinctrl_pwm4_default: pwm4_default { 1677 function = "PWM4"; 1678 groups = "PWM4"; 1679 }; 1680 1681 pinctrl_pwm5_default: pwm5_default { 1682 function = "PWM5"; 1683 groups = "PWM5"; 1684 }; 1685 1686 pinctrl_pwm6_default: pwm6_default { 1687 function = "PWM6"; 1688 groups = "PWM6"; 1689 }; 1690 1691 pinctrl_pwm7_default: pwm7_default { 1692 function = "PWM7"; 1693 groups = "PWM7"; 1694 }; 1695 1696 pinctrl_rgmii1_default: rgmii1_default { 1697 function = "RGMII1"; 1698 groups = "RGMII1"; 1699 }; 1700 1701 pinctrl_rgmii2_default: rgmii2_default { 1702 function = "RGMII2"; 1703 groups = "RGMII2"; 1704 }; 1705 1706 pinctrl_rgmii3_default: rgmii3_default { 1707 function = "RGMII3"; 1708 groups = "RGMII3"; 1709 }; 1710 1711 pinctrl_rgmii4_default: rgmii4_default { 1712 function = "RGMII4"; 1713 groups = "RGMII4"; 1714 }; 1715 1716 pinctrl_rmii1_default: rmii1_default { 1717 function = "RMII1"; 1718 groups = "RMII1"; 1719 }; 1720 1721 pinctrl_rmii2_default: rmii2_default { 1722 function = "RMII2"; 1723 groups = "RMII2"; 1724 }; 1725 1726 pinctrl_rxd1_default: rxd1_default { 1727 function = "RXD1"; 1728 groups = "RXD1"; 1729 u-boot,dm-pre-reloc; 1730 }; 1731 1732 pinctrl_rxd2_default: rxd2_default { 1733 function = "RXD2"; 1734 groups = "RXD2"; 1735 u-boot,dm-pre-reloc; 1736 }; 1737 1738 pinctrl_rxd3_default: rxd3_default { 1739 function = "RXD3"; 1740 groups = "RXD3"; 1741 u-boot,dm-pre-reloc; 1742 }; 1743 1744 pinctrl_rxd4_default: rxd4_default { 1745 function = "RXD4"; 1746 groups = "RXD4"; 1747 u-boot,dm-pre-reloc; 1748 }; 1749 1750 pinctrl_salt1_default: salt1_default { 1751 function = "SALT1"; 1752 groups = "SALT1"; 1753 }; 1754 1755 pinctrl_salt10_default: salt10_default { 1756 function = "SALT10"; 1757 groups = "SALT10"; 1758 }; 1759 1760 pinctrl_salt11_default: salt11_default { 1761 function = "SALT11"; 1762 groups = "SALT11"; 1763 }; 1764 1765 pinctrl_salt12_default: salt12_default { 1766 function = "SALT12"; 1767 groups = "SALT12"; 1768 }; 1769 1770 pinctrl_salt13_default: salt13_default { 1771 function = "SALT13"; 1772 groups = "SALT13"; 1773 }; 1774 1775 pinctrl_salt14_default: salt14_default { 1776 function = "SALT14"; 1777 groups = "SALT14"; 1778 }; 1779 1780 pinctrl_salt2_default: salt2_default { 1781 function = "SALT2"; 1782 groups = "SALT2"; 1783 }; 1784 1785 pinctrl_salt3_default: salt3_default { 1786 function = "SALT3"; 1787 groups = "SALT3"; 1788 }; 1789 1790 pinctrl_salt4_default: salt4_default { 1791 function = "SALT4"; 1792 groups = "SALT4"; 1793 }; 1794 1795 pinctrl_salt5_default: salt5_default { 1796 function = "SALT5"; 1797 groups = "SALT5"; 1798 }; 1799 1800 pinctrl_salt6_default: salt6_default { 1801 function = "SALT6"; 1802 groups = "SALT6"; 1803 }; 1804 1805 pinctrl_salt7_default: salt7_default { 1806 function = "SALT7"; 1807 groups = "SALT7"; 1808 }; 1809 1810 pinctrl_salt8_default: salt8_default { 1811 function = "SALT8"; 1812 groups = "SALT8"; 1813 }; 1814 1815 pinctrl_salt9_default: salt9_default { 1816 function = "SALT9"; 1817 groups = "SALT9"; 1818 }; 1819 1820 pinctrl_scl1_default: scl1_default { 1821 function = "SCL1"; 1822 groups = "SCL1"; 1823 }; 1824 1825 pinctrl_scl2_default: scl2_default { 1826 function = "SCL2"; 1827 groups = "SCL2"; 1828 }; 1829 1830 pinctrl_sd1_default: sd1_default { 1831 function = "SD1"; 1832 groups = "SD1"; 1833 }; 1834 1835 pinctrl_sd2_default: sd2_default { 1836 function = "SD2"; 1837 groups = "SD2"; 1838 }; 1839 1840 pinctrl_emmc_default: emmc_default { 1841 function = "EMMC"; 1842 groups = "EMMC"; 1843 }; 1844 1845 pinctrl_emmcg8_default: emmcg8_default { 1846 function = "EMMCG8"; 1847 groups = "EMMCG8"; 1848 }; 1849 1850 pinctrl_sda1_default: sda1_default { 1851 function = "SDA1"; 1852 groups = "SDA1"; 1853 }; 1854 1855 pinctrl_sda2_default: sda2_default { 1856 function = "SDA2"; 1857 groups = "SDA2"; 1858 }; 1859 1860 pinctrl_sgps1_default: sgps1_default { 1861 function = "SGPS1"; 1862 groups = "SGPS1"; 1863 }; 1864 1865 pinctrl_sgps2_default: sgps2_default { 1866 function = "SGPS2"; 1867 groups = "SGPS2"; 1868 }; 1869 1870 pinctrl_sioonctrl_default: sioonctrl_default { 1871 function = "SIOONCTRL"; 1872 groups = "SIOONCTRL"; 1873 }; 1874 1875 pinctrl_siopbi_default: siopbi_default { 1876 function = "SIOPBI"; 1877 groups = "SIOPBI"; 1878 }; 1879 1880 pinctrl_siopbo_default: siopbo_default { 1881 function = "SIOPBO"; 1882 groups = "SIOPBO"; 1883 }; 1884 1885 pinctrl_siopwreq_default: siopwreq_default { 1886 function = "SIOPWREQ"; 1887 groups = "SIOPWREQ"; 1888 }; 1889 1890 pinctrl_siopwrgd_default: siopwrgd_default { 1891 function = "SIOPWRGD"; 1892 groups = "SIOPWRGD"; 1893 }; 1894 1895 pinctrl_sios3_default: sios3_default { 1896 function = "SIOS3"; 1897 groups = "SIOS3"; 1898 }; 1899 1900 pinctrl_sios5_default: sios5_default { 1901 function = "SIOS5"; 1902 groups = "SIOS5"; 1903 }; 1904 1905 pinctrl_siosci_default: siosci_default { 1906 function = "SIOSCI"; 1907 groups = "SIOSCI"; 1908 }; 1909 1910 pinctrl_spi1_default: spi1_default { 1911 function = "SPI1"; 1912 groups = "SPI1"; 1913 }; 1914 1915 pinctrl_spi1cs1_default: spi1cs1_default { 1916 function = "SPI1CS1"; 1917 groups = "SPI1CS1"; 1918 }; 1919 1920 pinctrl_spi1debug_default: spi1debug_default { 1921 function = "SPI1DEBUG"; 1922 groups = "SPI1DEBUG"; 1923 }; 1924 1925 pinctrl_spi1passthru_default: spi1passthru_default { 1926 function = "SPI1PASSTHRU"; 1927 groups = "SPI1PASSTHRU"; 1928 }; 1929 1930 pinctrl_spi2ck_default: spi2ck_default { 1931 function = "SPI2CK"; 1932 groups = "SPI2CK"; 1933 }; 1934 1935 pinctrl_spi2cs0_default: spi2cs0_default { 1936 function = "SPI2CS0"; 1937 groups = "SPI2CS0"; 1938 }; 1939 1940 pinctrl_spi2cs1_default: spi2cs1_default { 1941 function = "SPI2CS1"; 1942 groups = "SPI2CS1"; 1943 }; 1944 1945 pinctrl_spi2miso_default: spi2miso_default { 1946 function = "SPI2MISO"; 1947 groups = "SPI2MISO"; 1948 }; 1949 1950 pinctrl_spi2mosi_default: spi2mosi_default { 1951 function = "SPI2MOSI"; 1952 groups = "SPI2MOSI"; 1953 }; 1954 1955 pinctrl_timer3_default: timer3_default { 1956 function = "TIMER3"; 1957 groups = "TIMER3"; 1958 }; 1959 1960 pinctrl_timer4_default: timer4_default { 1961 function = "TIMER4"; 1962 groups = "TIMER4"; 1963 }; 1964 1965 pinctrl_timer5_default: timer5_default { 1966 function = "TIMER5"; 1967 groups = "TIMER5"; 1968 }; 1969 1970 pinctrl_timer6_default: timer6_default { 1971 function = "TIMER6"; 1972 groups = "TIMER6"; 1973 }; 1974 1975 pinctrl_timer7_default: timer7_default { 1976 function = "TIMER7"; 1977 groups = "TIMER7"; 1978 }; 1979 1980 pinctrl_timer8_default: timer8_default { 1981 function = "TIMER8"; 1982 groups = "TIMER8"; 1983 }; 1984 1985 pinctrl_txd1_default: txd1_default { 1986 function = "TXD1"; 1987 groups = "TXD1"; 1988 u-boot,dm-pre-reloc; 1989 }; 1990 1991 pinctrl_txd2_default: txd2_default { 1992 function = "TXD2"; 1993 groups = "TXD2"; 1994 u-boot,dm-pre-reloc; 1995 }; 1996 1997 pinctrl_txd3_default: txd3_default { 1998 function = "TXD3"; 1999 groups = "TXD3"; 2000 u-boot,dm-pre-reloc; 2001 }; 2002 2003 pinctrl_txd4_default: txd4_default { 2004 function = "TXD4"; 2005 groups = "TXD4"; 2006 u-boot,dm-pre-reloc; 2007 }; 2008 2009 pinctrl_uart6_default: uart6_default { 2010 function = "UART6"; 2011 groups = "UART6"; 2012 }; 2013 2014 pinctrl_usbcki_default: usbcki_default { 2015 function = "USBCKI"; 2016 groups = "USBCKI"; 2017 }; 2018 2019 pinctrl_usb2ad_default: usb2ad_default { 2020 function = "USB2AD"; 2021 groups = "USB2AD"; 2022 }; 2023 2024 pinctrl_usb2ah_default: usb2ah_default { 2025 function = "USB2AH"; 2026 groups = "USB2AH"; 2027 }; 2028 2029 pinctrl_usb11bhid_default: usb11bhid_default { 2030 function = "USB11BHID"; 2031 groups = "USB11BHID"; 2032 }; 2033 2034 pinctrl_usb2bh_default: usb2bh_default { 2035 function = "USB2BH"; 2036 groups = "USB2BH"; 2037 }; 2038 2039 pinctrl_vgabiosrom_default: vgabiosrom_default { 2040 function = "VGABIOSROM"; 2041 groups = "VGABIOSROM"; 2042 }; 2043 2044 pinctrl_vgahs_default: vgahs_default { 2045 function = "VGAHS"; 2046 groups = "VGAHS"; 2047 }; 2048 2049 pinctrl_vgavs_default: vgavs_default { 2050 function = "VGAVS"; 2051 groups = "VGAVS"; 2052 }; 2053 2054 pinctrl_vpi24_default: vpi24_default { 2055 function = "VPI24"; 2056 groups = "VPI24"; 2057 }; 2058 2059 pinctrl_vpo_default: vpo_default { 2060 function = "VPO"; 2061 groups = "VPO"; 2062 }; 2063 2064 pinctrl_wdtrst1_default: wdtrst1_default { 2065 function = "WDTRST1"; 2066 groups = "WDTRST1"; 2067 }; 2068 2069 pinctrl_wdtrst2_default: wdtrst2_default { 2070 function = "WDTRST2"; 2071 groups = "WDTRST2"; 2072 }; 2073 2074 pinctrl_pcie0rc_default: pcie0rc_default { 2075 function = "PCIE0RC"; 2076 groups = "PCIE0RC"; 2077 }; 2078 2079 pinctrl_pcie1rc_default: pcie1rc_default { 2080 function = "PCIE1RC"; 2081 groups = "PCIE1RC"; 2082 }; 2083}; 2084