1// SPDX-License-Identifier: GPL-2.0+ 2#include <dt-bindings/interrupt-controller/arm-gic.h> 3#include <dt-bindings/gpio/aspeed-gpio.h> 4#include "skeleton.dtsi" 5 6/ { 7 model = "Aspeed BMC"; 8 compatible = "aspeed,ast2600"; 9 #address-cells = <1>; 10 #size-cells = <1>; 11 interrupt-parent = <&gic>; 12 13 aliases { 14 i2c0 = &i2c0; 15 i2c1 = &i2c1; 16 i2c2 = &i2c2; 17 i2c3 = &i2c3; 18 i2c4 = &i2c4; 19 i2c5 = &i2c5; 20 i2c6 = &i2c6; 21 i2c7 = &i2c7; 22 i2c8 = &i2c8; 23 i2c9 = &i2c9; 24 i2c10 = &i2c10; 25 i2c11 = &i2c11; 26 i2c12 = &i2c12; 27 i2c13 = &i2c13; 28 i2c14 = &i2c14; 29 i2c15 = &i2c15; 30 serial0 = &uart1; 31 serial1 = &uart2; 32 serial2 = &uart3; 33 serial3 = &uart4; 34 serial4 = &uart5; 35 serial5 = &uart6; 36 serial6 = &uart7; 37 serial7 = &uart8; 38 serial8 = &uart9; 39 serial9 = &uart10; 40 serial10 = &uart11; 41 serial11 = &uart12; 42 serial12 = &uart13; 43 }; 44 45 cpus { 46 #address-cells = <1>; 47 #size-cells = <0>; 48 enable-method = "aspeed,ast2600-smp"; 49 50 cpu@0 { 51 compatible = "arm,cortex-a7"; 52 device_type = "cpu"; 53 reg = <0>; 54 }; 55 56 cpu@1 { 57 compatible = "arm,cortex-a7"; 58 device_type = "cpu"; 59 reg = <1>; 60 }; 61 62 }; 63 64 timer { 65 compatible = "arm,armv7-timer"; 66 interrupt-parent = <&gic>; 67 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 68 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 69 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 70 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 71 }; 72 73 reserved-memory { 74 #address-cells = <1>; 75 #size-cells = <1>; 76 ranges; 77 78 gfx_memory: framebuffer { 79 size = <0x01000000>; 80 alignment = <0x01000000>; 81 compatible = "shared-dma-pool"; 82 reusable; 83 }; 84 85 video_memory: video { 86 size = <0x04000000>; 87 alignment = <0x01000000>; 88 compatible = "shared-dma-pool"; 89 no-map; 90 }; 91 }; 92 93 ahb { 94 compatible = "simple-bus"; 95 #address-cells = <1>; 96 #size-cells = <1>; 97 device_type = "soc"; 98 ranges; 99 100 gic: interrupt-controller@40461000 { 101 compatible = "arm,cortex-a7-gic"; 102 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 103 #interrupt-cells = <3>; 104 interrupt-controller; 105 interrupt-parent = <&gic>; 106 reg = <0x40461000 0x1000>, 107 <0x40462000 0x1000>, 108 <0x40464000 0x2000>, 109 <0x40466000 0x2000>; 110 }; 111 112 ahbc: ahbc@1e600000 { 113 compatible = "aspeed,aspeed-ahbc"; 114 reg = < 0x1e600000 0x100>; 115 }; 116 117 fmc: flash-controller@1e620000 { 118 reg = < 0x1e620000 0xc4 119 0x20000000 0x10000000 >; 120 #address-cells = <1>; 121 #size-cells = <0>; 122 compatible = "aspeed,ast2600-fmc"; 123 status = "disabled"; 124 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 125 clocks = <&scu ASPEED_CLK_AHB>; 126 num-cs = <3>; 127 flash@0 { 128 reg = < 0 >; 129 compatible = "jedec,spi-nor"; 130 status = "disabled"; 131 }; 132 flash@1 { 133 reg = < 1 >; 134 compatible = "jedec,spi-nor"; 135 status = "disabled"; 136 }; 137 flash@2 { 138 reg = < 2 >; 139 compatible = "jedec,spi-nor"; 140 status = "disabled"; 141 }; 142 }; 143 144 spi1: flash-controller@1e630000 { 145 reg = < 0x1e630000 0xc4 146 0x30000000 0x08000000 >; 147 #address-cells = <1>; 148 #size-cells = <0>; 149 compatible = "aspeed,ast2600-spi"; 150 clocks = <&scu ASPEED_CLK_AHB>; 151 num-cs = <2>; 152 status = "disabled"; 153 flash@0 { 154 reg = < 0 >; 155 compatible = "jedec,spi-nor"; 156 status = "disabled"; 157 }; 158 flash@1 { 159 reg = < 1 >; 160 compatible = "jedec,spi-nor"; 161 status = "disabled"; 162 }; 163 }; 164 165 spi2: flash-controller@1e631000 { 166 reg = < 0x1e631000 0xc4 167 0x50000000 0x08000000 >; 168 #address-cells = <1>; 169 #size-cells = <0>; 170 compatible = "aspeed,ast2600-spi"; 171 clocks = <&scu ASPEED_CLK_AHB>; 172 num-cs = <3>; 173 status = "disabled"; 174 flash@0 { 175 reg = < 0 >; 176 compatible = "jedec,spi-nor"; 177 status = "disabled"; 178 }; 179 flash@1 { 180 reg = < 1 >; 181 compatible = "jedec,spi-nor"; 182 status = "disabled"; 183 }; 184 flash@2 { 185 reg = < 1 >; 186 compatible = "jedec,spi-nor"; 187 status = "disabled"; 188 }; 189 }; 190 191 edac: sdram@1e6e0000 { 192 compatible = "aspeed,ast2600-sdram-edac"; 193 reg = <0x1e6e0000 0x174>; 194 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 195 }; 196 197 mdio: ethernet@1e650000 { 198 compatible = "aspeed,aspeed-mdio"; 199 reg = <0x1e650000 0x40>; 200 resets = <&rst ASPEED_RESET_MII>; 201 status = "disabled"; 202 }; 203 204 mac0: ftgmac@1e660000 { 205 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 206 reg = <0x1e660000 0x180>, <0x1e650000 0x4>; 207 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 208 clocks = <&scu ASPEED_CLK_GATE_MAC1CLK>; 209 status = "disabled"; 210 }; 211 212 mac1: ftgmac@1e680000 { 213 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 214 reg = <0x1e680000 0x180>, <0x1e650008 0x4>; 215 #address-cells = <1>; 216 #size-cells = <0>; 217 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 218 clocks = <&scu ASPEED_CLK_GATE_MAC2CLK>; 219#if 0 220 phy-handle = <&phy0>; 221#endif 222 status = "disabled"; 223 }; 224 225 mac2: ftgmac@1e670000 { 226 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 227 reg = <0x1e670000 0x180>, <0x1e650010 0x4>; 228 #address-cells = <1>; 229 #size-cells = <0>; 230 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 231 clocks = <&scu ASPEED_CLK_GATE_MAC3CLK>; 232#if 0 233 phy-handle = <&phy0>; 234#endif 235 status = "disabled"; 236 }; 237 238 mac3: ftgmac@1e690000 { 239 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 240 reg = <0x1e690000 0x180>, <0x1e650018 0x4>; 241 #address-cells = <1>; 242 #size-cells = <0>; 243 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 244 clocks = <&scu ASPEED_CLK_GATE_MAC4CLK>; 245#if 0 246 phy-handle = <&phy0>; 247#endif 248 status = "disabled"; 249 }; 250 251 apb { 252 compatible = "simple-bus"; 253 #address-cells = <1>; 254 #size-cells = <1>; 255 ranges; 256 257 syscon: syscon@1e6e2000 { 258 compatible = "aspeed,g6-scu", "syscon", "simple-mfd"; 259 reg = <0x1e6e2000 0x1000>; 260 #address-cells = <1>; 261 #size-cells = <1>; 262 #clock-cells = <1>; 263 #reset-cells = <1>; 264 ranges = <0 0x1e6e2000 0x1000>; 265 266 pinctrl: pinctrl { 267 compatible = "aspeed,g6-pinctrl"; 268 aspeed,external-nodes = <&gfx &lhc>; 269 270 }; 271 272 vga_scratch: scratch { 273 compatible = "aspeed,bmc-misc"; 274 }; 275 276 scu_ic0: interrupt-controller@0 { 277 #interrupt-cells = <1>; 278 compatible = "aspeed,ast2600-scu-ic"; 279 reg = <0x560 0x10>; 280 interrupt-parent = <&gic>; 281 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 282 interrupt-controller; 283 }; 284 285 scu_ic1: interrupt-controller@1 { 286 #interrupt-cells = <1>; 287 compatible = "aspeed,ast2600-scu-ic"; 288 reg = <0x570 0x10>; 289 interrupt-parent = <&gic>; 290 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 291 interrupt-controller; 292 }; 293 294 }; 295 296 smp-memram@0 { 297 compatible = "aspeed,ast2600-smpmem", "syscon"; 298 reg = <0x1e6e2180 0x40>; 299 }; 300 301 gfx: display@1e6e6000 { 302 compatible = "aspeed,ast2500-gfx", "syscon"; 303 reg = <0x1e6e6000 0x1000>; 304 reg-io-width = <4>; 305 }; 306 307 pcie_bridge0: pcie_bridge@0x1e6ed000 { 308 compatible = "aspeed,ast2600-pcie"; 309 reg = <0x1e6ed000 0x100>; 310 ranges = <0x60000000 0 0 0x60000000 0x1 0 1 0>; 311 bus-range = <0x00 0xff>; 312 resets = <&rst ASPEED_RESET_PCIE_DEV_OEN>, <&rst ASPEED_RESET_PCIE_DEV_O>; 313 314 status = "disabled"; 315 }; 316 317 pcie_bridge1: pcie_bridge@0x1e6ed200 { 318 compatible = "aspeed,ast2600-pcie"; 319 reg = <0x1e6ed200 0x100>; 320 ranges = <0x70000000 0 0 0x70000000 0x1 0 1 0>; 321 bus-range = <0x00 0xff>; 322 resets = <&rst ASPEED_RESET_PCIE_RC_OEN>, <&rst ASPEED_RESET_PCIE_RC_O>; 323 pinctrl-names = "default"; 324 pinctrl-0 = <&pinctrl_pcierc_default>; 325 326 status = "disabled"; 327 }; 328 329 sdhci: sdhci@1e740000 { 330 #interrupt-cells = <1>; 331 compatible = "aspeed,aspeed-sdhci-irq", "simple-mfd"; 332 reg = <0x1e740000 0x1000>; 333 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 334 interrupt-controller; 335 clocks = <&scu ASPEED_CLK_GATE_SDCLK>, <&scu ASPEED_CLK_GATE_SDEXTCLK>; 336 clock-names = "ctrlclk", "extclk"; 337 #address-cells = <1>; 338 #size-cells = <1>; 339 ranges = <0x0 0x1e740000 0x1000>; 340 341 sdhci_slot0: sdhci_slot0@100 { 342 compatible = "aspeed,sdhci-ast2600"; 343 reg = <0x100 0x100>; 344 interrupts = <0>; 345 interrupt-parent = <&sdhci>; 346 sdhci,auto-cmd12; 347 clocks = <&scu ASPEED_CLK_SDIO>; 348 status = "disabled"; 349 }; 350 351 sdhci_slot1: sdhci_slot1@200 { 352 compatible = "aspeed,sdhci-ast2600"; 353 reg = <0x200 0x100>; 354 interrupts = <1>; 355 interrupt-parent = <&sdhci>; 356 sdhci,auto-cmd12; 357 clocks = <&scu ASPEED_CLK_SDIO>; 358 status = "disabled"; 359 }; 360 }; 361 362 emmc: emmc@1e750000 { 363 #interrupt-cells = <1>; 364 compatible = "aspeed,aspeed-emmc-irq", "simple-mfd"; 365 reg = <0x1e750000 0x1000>; 366 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 367 interrupt-controller; 368 clocks = <&scu ASPEED_CLK_GATE_EMMCCLK>, <&scu ASPEED_CLK_GATE_EMMCEXTCLK>; 369 clock-names = "ctrlclk", "extclk"; 370 #address-cells = <1>; 371 #size-cells = <1>; 372 ranges = <0x0 0x1e750000 0x1000>; 373 374 emmc_slot0: emmc_slot0@100 { 375 compatible = "aspeed,emmc-ast2600"; 376 reg = <0x100 0x100>; 377 interrupts = <0>; 378 interrupt-parent = <&emmc>; 379 clocks = <&scu ASPEED_CLK_EMMC>; 380 status = "disabled"; 381 }; 382 }; 383 384 h2x: h2x@1e770000 { 385 compatible = "aspeed,ast2600-h2x"; 386 reg = <0x1e770000 0x100>; 387 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 388 resets = <&rst ASPEED_RESET_H2X>; 389 status = "disabled"; 390 }; 391 392 gpio0: gpio@1e780000 { 393 compatible = "aspeed,ast2600-gpio"; 394 reg = <0x1e780000 0x1000>; 395 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 396 #gpio-cells = <2>; 397 gpio-controller; 398 interrupt-controller; 399 gpio-ranges = <&pinctrl 0 0 220>; 400 }; 401 402 gpio1: gpio@1e780800 { 403 compatible = "aspeed,ast2600-gpio"; 404 reg = <0x1e780800 0x800>; 405 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 406 #gpio-cells = <2>; 407 gpio-controller; 408 interrupt-controller; 409 gpio-ranges = <&pinctrl 0 0 208>; 410 }; 411 412 uart1: serial@1e783000 { 413 compatible = "ns16550a"; 414 reg = <0x1e783000 0x20>; 415 reg-shift = <2>; 416 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 417 clocks = <&scu ASPEED_CLK_GATE_UART1CLK>; 418 clock-frequency = <1846154>; 419 no-loopback-test; 420 status = "disabled"; 421 }; 422 423 uart5: serial@1e784000 { 424 compatible = "ns16550a"; 425 reg = <0x1e784000 0x1000>; 426 reg-shift = <2>; 427 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 428 clocks = <&scu ASPEED_CLK_GATE_UART5CLK>; 429 clock-frequency = <1846154>; 430 no-loopback-test; 431 status = "disabled"; 432 }; 433 434 wdt1: watchdog@1e785000 { 435 compatible = "aspeed,ast2600-wdt"; 436 reg = <0x1e785000 0x40>; 437 }; 438 439 wdt2: watchdog@1e785040 { 440 compatible = "aspeed,ast2600-wdt"; 441 reg = <0x1e785040 0x40>; 442 }; 443 444 wdt3: watchdog@1e785080 { 445 compatible = "aspeed,ast2600-wdt"; 446 reg = <0x1e785080 0x40>; 447 }; 448 449 wdt4: watchdog@1e7850C0 { 450 compatible = "aspeed,ast2600-wdt"; 451 reg = <0x1e7850C0 0x40>; 452 }; 453 454 lpc: lpc@1e789000 { 455 compatible = "aspeed,ast-lpc", "simple-mfd", "syscon"; 456 reg = <0x1e789000 0x200>; 457 458 #address-cells = <1>; 459 #size-cells = <1>; 460 ranges = <0x0 0x1e789000 0x1000>; 461 462 lpc_bmc: lpc-bmc@0 { 463 compatible = "aspeed,ast2600-lpc-bmc", "simple-mfd", "syscon"; 464 reg = <0x0 0x80>; 465 reg-io-width = <4>; 466 #address-cells = <1>; 467 #size-cells = <1>; 468 ranges = <0x0 0x0 0x80>; 469 470 kcs1: kcs1@0 { 471 compatible = "aspeed,ast2600-kcs-bmc"; 472 reg = <0x0 0x80>; 473 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 474 kcs_chan = <1>; 475 kcs_addr = <0xCA0>; 476 status = "disabled"; 477 }; 478 479 kcs2: kcs2@0 { 480 compatible = "aspeed,ast2600-kcs-bmc"; 481 reg = <0x0 0x80>; 482 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 483 kcs_chan = <2>; 484 kcs_addr = <0xCA8>; 485 status = "disabled"; 486 }; 487 488 kcs3: kcs3@0 { 489 compatible = "aspeed,ast2600-kcs-bmc"; 490 reg = <0x0 0x80>; 491 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 492 kcs_chan = <3>; 493 kcs_addr = <0xCA2>; 494 }; 495 496 kcs4: kcs4@0 { 497 compatible = "aspeed,ast2600-kcs-bmc"; 498 reg = <0x0 0x120>; 499 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 500 kcs_chan = <4>; 501 kcs_addr = <0xCA4>; 502 status = "disabled"; 503 }; 504 505 }; 506 507 lpc_host: lpc-host@80 { 508 compatible = "aspeed,ast2600-lpc-host", "simple-mfd", "syscon"; 509 reg = <0x80 0x1e0>; 510 reg-io-width = <4>; 511 512 #address-cells = <1>; 513 #size-cells = <1>; 514 ranges = <0x0 0x80 0x1e0>; 515 516 lpc_ctrl: lpc-ctrl@0 { 517 compatible = "aspeed,ast2600-lpc-ctrl"; 518 reg = <0x0 0x80>; 519 status = "disabled"; 520 }; 521 522 lpc_snoop: lpc-snoop@0 { 523 compatible = "aspeed,ast2600-lpc-snoop"; 524 reg = <0x0 0x80>; 525 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 526 snoop-ports = <0x80>; 527 status = "disabled"; 528 }; 529 530 lhc: lhc@20 { 531 compatible = "aspeed,ast2600-lhc"; 532 reg = <0x20 0x24 0x48 0x8>; 533 }; 534 535 lpc_reset: reset-controller@18 { 536 compatible = "aspeed,ast2600-lpc-reset"; 537 reg = <0x18 0x4>; 538 #reset-cells = <1>; 539 status = "disabled"; 540 }; 541 542 ibt: ibt@c0 { 543 compatible = "aspeed,ast2600-ibt-bmc"; 544 reg = <0xc0 0x18>; 545 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 546 status = "disabled"; 547 }; 548 549 sio_regs: regs { 550 compatible = "aspeed,bmc-misc"; 551 }; 552 553 mbox: mbox@180 { 554 compatible = "aspeed,ast2600-mbox"; 555 reg = <0x180 0x5c>; 556 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 557 #mbox-cells = <1>; 558 status = "disabled"; 559 }; 560 }; 561 }; 562 563 uart2: serial@1e78d000 { 564 compatible = "ns16550a"; 565 reg = <0x1e78d000 0x20>; 566 reg-shift = <2>; 567 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 568 clocks = <&scu ASPEED_CLK_GATE_UART2CLK>; 569 clock-frequency = <1846154>; 570 no-loopback-test; 571 status = "disabled"; 572 }; 573 574 uart3: serial@1e78e000 { 575 compatible = "ns16550a"; 576 reg = <0x1e78e000 0x20>; 577 reg-shift = <2>; 578 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 579 clocks = <&scu ASPEED_CLK_GATE_UART3CLK>; 580 clock-frequency = <1846154>; 581 no-loopback-test; 582 status = "disabled"; 583 }; 584 585 uart4: serial@1e78f000 { 586 compatible = "ns16550a"; 587 reg = <0x1e78f000 0x20>; 588 reg-shift = <2>; 589 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 590 clocks = <&scu ASPEED_CLK_GATE_UART4CLK>; 591 clock-frequency = <1846154>; 592 no-loopback-test; 593 status = "disabled"; 594 }; 595 596 i2c: bus@1e78a000 { 597 compatible = "simple-bus"; 598 #address-cells = <1>; 599 #size-cells = <1>; 600 ranges = <0 0x1e78a000 0x1000>; 601 }; 602 603 fsim0: fsi@1e79b000 { 604 compatible = "aspeed,ast2600-fsi-master", "fsi-master"; 605 reg = <0x1e79b000 0x94>; 606 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 607 pinctrl-names = "default"; 608 pinctrl-0 = <&pinctrl_fsi1_default>; 609 clocks = <&scu ASPEED_CLK_GATE_FSICLK>; 610 status = "disabled"; 611 }; 612 613 fsim1: fsi@1e79b100 { 614 compatible = "aspeed,ast2600-fsi-master", "fsi-master"; 615 reg = <0x1e79b100 0x94>; 616 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 617 pinctrl-names = "default"; 618 pinctrl-0 = <&pinctrl_fsi2_default>; 619 clocks = <&scu ASPEED_CLK_GATE_FSICLK>; 620 status = "disabled"; 621 }; 622 623 uart6: serial@1e790000 { 624 compatible = "ns16550a"; 625 reg = <0x1e790000 0x20>; 626 reg-shift = <2>; 627 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 628 clocks = <&scu ASPEED_CLK_GATE_UART6CLK>; 629 clock-frequency = <1846154>; 630 no-loopback-test; 631 status = "disabled"; 632 }; 633 634 uart7: serial@1e790100 { 635 compatible = "ns16550a"; 636 reg = <0x1e790100 0x20>; 637 reg-shift = <2>; 638 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 639 clocks = <&scu ASPEED_CLK_GATE_UART7CLK>; 640 clock-frequency = <1846154>; 641 no-loopback-test; 642 status = "disabled"; 643 }; 644 645 uart8: serial@1e790200 { 646 compatible = "ns16550a"; 647 reg = <0x1e790200 0x20>; 648 reg-shift = <2>; 649 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 650 clocks = <&scu ASPEED_CLK_GATE_UART8CLK>; 651 clock-frequency = <1846154>; 652 no-loopback-test; 653 status = "disabled"; 654 }; 655 656 uart9: serial@1e790300 { 657 compatible = "ns16550a"; 658 reg = <0x1e790300 0x20>; 659 reg-shift = <2>; 660 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 661 clocks = <&scu ASPEED_CLK_GATE_UART9CLK>; 662 clock-frequency = <1846154>; 663 no-loopback-test; 664 status = "disabled"; 665 }; 666 667 uart10: serial@1e790400 { 668 compatible = "ns16550a"; 669 reg = <0x1e790400 0x20>; 670 reg-shift = <2>; 671 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 672 clocks = <&scu ASPEED_CLK_GATE_UART10CLK>; 673 clock-frequency = <1846154>; 674 no-loopback-test; 675 status = "disabled"; 676 }; 677 678 uart11: serial@1e790500 { 679 compatible = "ns16550a"; 680 reg = <0x1e790400 0x20>; 681 reg-shift = <2>; 682 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 683 clocks = <&scu ASPEED_CLK_GATE_UART11CLK>; 684 clock-frequency = <1846154>; 685 no-loopback-test; 686 status = "disabled"; 687 }; 688 689 uart12: serial@1e790600 { 690 compatible = "ns16550a"; 691 reg = <0x1e790600 0x20>; 692 reg-shift = <2>; 693 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 694 clocks = <&scu ASPEED_CLK_GATE_UART12CLK>; 695 clock-frequency = <1846154>; 696 no-loopback-test; 697 status = "disabled"; 698 }; 699 700 uart13: serial@1e790700 { 701 compatible = "ns16550a"; 702 reg = <0x1e790700 0x20>; 703 reg-shift = <2>; 704 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 705 clocks = <&scu ASPEED_CLK_GATE_UART13CLK>; 706 clock-frequency = <1846154>; 707 no-loopback-test; 708 status = "disabled"; 709 }; 710 711 712 713 }; 714 715 }; 716 717}; 718 719&i2c { 720 i2cglobal: i2cg@00 { 721 compatible = "aspeed,ast2600-i2c-global"; 722 reg = <0x0 0x40>; 723 resets = <&rst ASPEED_RESET_I2C>; 724#if 0 725 new-mode; 726#endif 727 }; 728 729 i2c0: i2c@80 { 730 #address-cells = <1>; 731 #size-cells = <0>; 732 #interrupt-cells = <1>; 733 734 reg = <0x80 0x80 0xC00 0x20>; 735 compatible = "aspeed,ast2600-i2c-bus"; 736 bus-frequency = <100000>; 737 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 738 clocks = <&scu ASPEED_CLK_APB2>; 739 status = "disabled"; 740 }; 741 742 i2c1: i2c@100 { 743 #address-cells = <1>; 744 #size-cells = <0>; 745 #interrupt-cells = <1>; 746 747 reg = <0x100 0x80 0xC20 0x20>; 748 compatible = "aspeed,ast2600-i2c-bus"; 749 bus-frequency = <100000>; 750 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 751 clocks = <&scu ASPEED_CLK_APB2>; 752 status = "disabled"; 753 }; 754 755 i2c2: i2c@180 { 756 #address-cells = <1>; 757 #size-cells = <0>; 758 #interrupt-cells = <1>; 759 760 reg = <0x180 0x80 0xC40 0x20>; 761 compatible = "aspeed,ast2600-i2c-bus"; 762 bus-frequency = <100000>; 763 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 764 clocks = <&scu ASPEED_CLK_APB2>; 765 }; 766 767 i2c3: i2c@200 { 768 #address-cells = <1>; 769 #size-cells = <0>; 770 #interrupt-cells = <1>; 771 772 reg = <0x200 0x40 0xC60 0x20>; 773 compatible = "aspeed,ast2600-i2c-bus"; 774 bus-frequency = <100000>; 775 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 776 clocks = <&scu ASPEED_CLK_APB2>; 777 }; 778 779 i2c4: i2c@280 { 780 #address-cells = <1>; 781 #size-cells = <0>; 782 #interrupt-cells = <1>; 783 784 reg = <0x280 0x80 0xC80 0x20>; 785 compatible = "aspeed,ast2600-i2c-bus"; 786 bus-frequency = <100000>; 787 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 788 clocks = <&scu ASPEED_CLK_APB2>; 789 }; 790 791 i2c5: i2c@300 { 792 #address-cells = <1>; 793 #size-cells = <0>; 794 #interrupt-cells = <1>; 795 796 reg = <0x300 0x40 0xCA0 0x20>; 797 compatible = "aspeed,ast2600-i2c-bus"; 798 bus-frequency = <100000>; 799 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 800 clocks = <&scu ASPEED_CLK_APB2>; 801 }; 802 803 i2c6: i2c@380 { 804 #address-cells = <1>; 805 #size-cells = <0>; 806 #interrupt-cells = <1>; 807 808 reg = <0x380 0x80 0xCC0 0x20>; 809 compatible = "aspeed,ast2600-i2c-bus"; 810 bus-frequency = <100000>; 811 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 812 clocks = <&scu ASPEED_CLK_APB2>; 813 }; 814 815 i2c7: i2c@400 { 816 #address-cells = <1>; 817 #size-cells = <0>; 818 #interrupt-cells = <1>; 819 820 reg = <0x400 0x80 0xCE0 0x20>; 821 compatible = "aspeed,ast2600-i2c-bus"; 822 bus-frequency = <100000>; 823 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 824 clocks = <&scu ASPEED_CLK_APB2>; 825 }; 826 827 i2c8: i2c@480 { 828 #address-cells = <1>; 829 #size-cells = <0>; 830 #interrupt-cells = <1>; 831 832 reg = <0x480 0x80 0xD00 0x20>; 833 compatible = "aspeed,ast2600-i2c-bus"; 834 bus-frequency = <100000>; 835 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 836 clocks = <&scu ASPEED_CLK_APB2>; 837 }; 838 839 i2c9: i2c@500 { 840 #address-cells = <1>; 841 #size-cells = <0>; 842 #interrupt-cells = <1>; 843 844 reg = <0x500 0x80 0xD20 0x20>; 845 compatible = "aspeed,ast2600-i2c-bus"; 846 bus-frequency = <100000>; 847 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 848 clocks = <&scu ASPEED_CLK_APB2>; 849 status = "disabled"; 850 }; 851 852 i2c10: i2c@580 { 853 #address-cells = <1>; 854 #size-cells = <0>; 855 #interrupt-cells = <1>; 856 857 reg = <0x580 0x80 0xD40 0x20>; 858 compatible = "aspeed,ast2600-i2c-bus"; 859 bus-frequency = <100000>; 860 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 861 clocks = <&scu ASPEED_CLK_APB2>; 862 status = "disabled"; 863 }; 864 865 i2c11: i2c@600 { 866 #address-cells = <1>; 867 #size-cells = <0>; 868 #interrupt-cells = <1>; 869 870 reg = <0x600 0x80 0xD60 0x20>; 871 compatible = "aspeed,ast2600-i2c-bus"; 872 bus-frequency = <100000>; 873 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 874 clocks = <&scu ASPEED_CLK_APB2>; 875 status = "disabled"; 876 }; 877 878 i2c12: i2c@680 { 879 #address-cells = <1>; 880 #size-cells = <0>; 881 #interrupt-cells = <1>; 882 883 reg = <0x680 0x80 0xD80 0x20>; 884 compatible = "aspeed,ast2600-i2c-bus"; 885 bus-frequency = <100000>; 886 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 887 clocks = <&scu ASPEED_CLK_APB2>; 888 status = "disabled"; 889 }; 890 891 i2c13: i2c@700 { 892 #address-cells = <1>; 893 #size-cells = <0>; 894 #interrupt-cells = <1>; 895 896 reg = <0x700 0x80 0xDA0 0x20>; 897 compatible = "aspeed,ast2600-i2c-bus"; 898 bus-frequency = <100000>; 899 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 900 clocks = <&scu ASPEED_CLK_APB2>; 901 status = "disabled"; 902 }; 903 904 i2c14: i2c@780 { 905 #address-cells = <1>; 906 #size-cells = <0>; 907 #interrupt-cells = <1>; 908 909 reg = <0x780 0x80 0xDC0 0x20>; 910 compatible = "aspeed,ast2600-i2c-bus"; 911 bus-frequency = <100000>; 912 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 913 clocks = <&scu ASPEED_CLK_APB2>; 914 status = "disabled"; 915 }; 916 917 i2c15: i2c@800 { 918 #address-cells = <1>; 919 #size-cells = <0>; 920 #interrupt-cells = <1>; 921 922 reg = <0x800 0x80 0xDE0 0x20>; 923 compatible = "aspeed,ast2600-i2c-bus"; 924 bus-frequency = <100000>; 925 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 926 clocks = <&scu ASPEED_CLK_APB2>; 927 status = "disabled"; 928 }; 929 930}; 931 932&pinctrl { 933 pinctrl_fmcquad_default: fmcquad_default { 934 function = "FMCQUAD"; 935 groups = "FMCQUAD"; 936 }; 937 938 pinctrl_spi1_default: spi1_default { 939 function = "SPI1"; 940 groups = "SPI1"; 941 }; 942 943 pinctrl_spi1abr_default: spi1abr_default { 944 function = "SPI1ABR"; 945 groups = "SPI1ABR"; 946 }; 947 948 pinctrl_spi1cs1_default: spi1cs1_default { 949 function = "SPI1CS1"; 950 groups = "SPI1CS1"; 951 }; 952 953 pinctrl_spi1wp_default: spi1wp_default { 954 function = "SPI1WP"; 955 groups = "SPI1WP"; 956 }; 957 958 pinctrl_spi1quad_default: spi1quad_default { 959 function = "SPI1QUAD"; 960 groups = "SPI1QUAD"; 961 }; 962 963 pinctrl_spi2_default: spi2_default { 964 function = "SPI2"; 965 groups = "SPI2"; 966 }; 967 968 pinctrl_spi2cs1_default: spi2cs1_default { 969 function = "SPI2CS1"; 970 groups = "SPI2CS1"; 971 }; 972 973 pinctrl_spi2cs2_default: spi2cs2_default { 974 function = "SPI2CS2"; 975 groups = "SPI2CS2"; 976 }; 977 978 pinctrl_spi2quad_default: spi2quad_default { 979 function = "SPI2QUAD"; 980 groups = "SPI2QUAD"; 981 }; 982 983 pinctrl_acpi_default: acpi_default { 984 function = "ACPI"; 985 groups = "ACPI"; 986 }; 987 988 pinctrl_adc0_default: adc0_default { 989 function = "ADC0"; 990 groups = "ADC0"; 991 }; 992 993 pinctrl_adc1_default: adc1_default { 994 function = "ADC1"; 995 groups = "ADC1"; 996 }; 997 998 pinctrl_adc10_default: adc10_default { 999 function = "ADC10"; 1000 groups = "ADC10"; 1001 }; 1002 1003 pinctrl_adc11_default: adc11_default { 1004 function = "ADC11"; 1005 groups = "ADC11"; 1006 }; 1007 1008 pinctrl_adc12_default: adc12_default { 1009 function = "ADC12"; 1010 groups = "ADC12"; 1011 }; 1012 1013 pinctrl_adc13_default: adc13_default { 1014 function = "ADC13"; 1015 groups = "ADC13"; 1016 }; 1017 1018 pinctrl_adc14_default: adc14_default { 1019 function = "ADC14"; 1020 groups = "ADC14"; 1021 }; 1022 1023 pinctrl_adc15_default: adc15_default { 1024 function = "ADC15"; 1025 groups = "ADC15"; 1026 }; 1027 1028 pinctrl_adc2_default: adc2_default { 1029 function = "ADC2"; 1030 groups = "ADC2"; 1031 }; 1032 1033 pinctrl_adc3_default: adc3_default { 1034 function = "ADC3"; 1035 groups = "ADC3"; 1036 }; 1037 1038 pinctrl_adc4_default: adc4_default { 1039 function = "ADC4"; 1040 groups = "ADC4"; 1041 }; 1042 1043 pinctrl_adc5_default: adc5_default { 1044 function = "ADC5"; 1045 groups = "ADC5"; 1046 }; 1047 1048 pinctrl_adc6_default: adc6_default { 1049 function = "ADC6"; 1050 groups = "ADC6"; 1051 }; 1052 1053 pinctrl_adc7_default: adc7_default { 1054 function = "ADC7"; 1055 groups = "ADC7"; 1056 }; 1057 1058 pinctrl_adc8_default: adc8_default { 1059 function = "ADC8"; 1060 groups = "ADC8"; 1061 }; 1062 1063 pinctrl_adc9_default: adc9_default { 1064 function = "ADC9"; 1065 groups = "ADC9"; 1066 }; 1067 1068 pinctrl_bmcint_default: bmcint_default { 1069 function = "BMCINT"; 1070 groups = "BMCINT"; 1071 }; 1072 1073 pinctrl_ddcclk_default: ddcclk_default { 1074 function = "DDCCLK"; 1075 groups = "DDCCLK"; 1076 }; 1077 1078 pinctrl_ddcdat_default: ddcdat_default { 1079 function = "DDCDAT"; 1080 groups = "DDCDAT"; 1081 }; 1082 1083 pinctrl_espi_default: espi_default { 1084 function = "ESPI"; 1085 groups = "ESPI"; 1086 }; 1087 1088 pinctrl_fsi1_default: fsi1_default { 1089 function = "FSI1"; 1090 groups = "FSI1"; 1091 }; 1092 1093 pinctrl_fsi2_default: fsi2_default { 1094 function = "FSI2"; 1095 groups = "FSI2"; 1096 }; 1097 1098 pinctrl_fwspics1_default: fwspics1_default { 1099 function = "FWSPICS1"; 1100 groups = "FWSPICS1"; 1101 }; 1102 1103 pinctrl_fwspics2_default: fwspics2_default { 1104 function = "FWSPICS2"; 1105 groups = "FWSPICS2"; 1106 }; 1107 1108 pinctrl_gpid0_default: gpid0_default { 1109 function = "GPID0"; 1110 groups = "GPID0"; 1111 }; 1112 1113 pinctrl_gpid2_default: gpid2_default { 1114 function = "GPID2"; 1115 groups = "GPID2"; 1116 }; 1117 1118 pinctrl_gpid4_default: gpid4_default { 1119 function = "GPID4"; 1120 groups = "GPID4"; 1121 }; 1122 1123 pinctrl_gpid6_default: gpid6_default { 1124 function = "GPID6"; 1125 groups = "GPID6"; 1126 }; 1127 1128 pinctrl_gpie0_default: gpie0_default { 1129 function = "GPIE0"; 1130 groups = "GPIE0"; 1131 }; 1132 1133 pinctrl_gpie2_default: gpie2_default { 1134 function = "GPIE2"; 1135 groups = "GPIE2"; 1136 }; 1137 1138 pinctrl_gpie4_default: gpie4_default { 1139 function = "GPIE4"; 1140 groups = "GPIE4"; 1141 }; 1142 1143 pinctrl_gpie6_default: gpie6_default { 1144 function = "GPIE6"; 1145 groups = "GPIE6"; 1146 }; 1147 1148 pinctrl_i2c1_default: i2c1_default { 1149 function = "I2C1"; 1150 groups = "I2C1"; 1151 }; 1152 pinctrl_i2c2_default: i2c2_default { 1153 function = "I2C2"; 1154 groups = "I2C2"; 1155 }; 1156 1157 pinctrl_i2c3_default: i2c3_default { 1158 function = "I2C3"; 1159 groups = "I2C3"; 1160 }; 1161 1162 pinctrl_i2c4_default: i2c4_default { 1163 function = "I2C4"; 1164 groups = "I2C4"; 1165 }; 1166 1167 pinctrl_i2c5_default: i2c5_default { 1168 function = "I2C5"; 1169 groups = "I2C5"; 1170 }; 1171 1172 pinctrl_i2c6_default: i2c6_default { 1173 function = "I2C6"; 1174 groups = "I2C6"; 1175 }; 1176 1177 pinctrl_i2c7_default: i2c7_default { 1178 function = "I2C7"; 1179 groups = "I2C7"; 1180 }; 1181 1182 pinctrl_i2c8_default: i2c8_default { 1183 function = "I2C8"; 1184 groups = "I2C8"; 1185 }; 1186 1187 pinctrl_i2c9_default: i2c9_default { 1188 function = "I2C9"; 1189 groups = "I2C9"; 1190 }; 1191 1192 pinctrl_i2c10_default: i2c10_default { 1193 function = "I2C10"; 1194 groups = "I2C10"; 1195 }; 1196 1197 pinctrl_i2c11_default: i2c11_default { 1198 function = "I2C11"; 1199 groups = "I2C11"; 1200 }; 1201 1202 pinctrl_i2c12_default: i2c12_default { 1203 function = "I2C12"; 1204 groups = "I2C12"; 1205 }; 1206 1207 pinctrl_i2c13_default: i2c13_default { 1208 function = "I2C13"; 1209 groups = "I2C13"; 1210 }; 1211 1212 pinctrl_i2c14_default: i2c14_default { 1213 function = "I2C14"; 1214 groups = "I2C14"; 1215 }; 1216 1217 pinctrl_i2c15_default: i2c15_default { 1218 function = "I2C15"; 1219 groups = "I2C15"; 1220 }; 1221 1222 pinctrl_i2c16_default: i2c16_default { 1223 function = "I2C16"; 1224 groups = "I2C16"; 1225 }; 1226 1227 pinctrl_lad0_default: lad0_default { 1228 function = "LAD0"; 1229 groups = "LAD0"; 1230 }; 1231 1232 pinctrl_lad1_default: lad1_default { 1233 function = "LAD1"; 1234 groups = "LAD1"; 1235 }; 1236 1237 pinctrl_lad2_default: lad2_default { 1238 function = "LAD2"; 1239 groups = "LAD2"; 1240 }; 1241 1242 pinctrl_lad3_default: lad3_default { 1243 function = "LAD3"; 1244 groups = "LAD3"; 1245 }; 1246 1247 pinctrl_lclk_default: lclk_default { 1248 function = "LCLK"; 1249 groups = "LCLK"; 1250 }; 1251 1252 pinctrl_lframe_default: lframe_default { 1253 function = "LFRAME"; 1254 groups = "LFRAME"; 1255 }; 1256 1257 pinctrl_lpchc_default: lpchc_default { 1258 function = "LPCHC"; 1259 groups = "LPCHC"; 1260 }; 1261 1262 pinctrl_lpcpd_default: lpcpd_default { 1263 function = "LPCPD"; 1264 groups = "LPCPD"; 1265 }; 1266 1267 pinctrl_lpcplus_default: lpcplus_default { 1268 function = "LPCPLUS"; 1269 groups = "LPCPLUS"; 1270 }; 1271 1272 pinctrl_lpcpme_default: lpcpme_default { 1273 function = "LPCPME"; 1274 groups = "LPCPME"; 1275 }; 1276 1277 pinctrl_lpcrst_default: lpcrst_default { 1278 function = "LPCRST"; 1279 groups = "LPCRST"; 1280 }; 1281 1282 pinctrl_lpcsmi_default: lpcsmi_default { 1283 function = "LPCSMI"; 1284 groups = "LPCSMI"; 1285 }; 1286 1287 pinctrl_lsirq_default: lsirq_default { 1288 function = "LSIRQ"; 1289 groups = "LSIRQ"; 1290 }; 1291 1292 pinctrl_mac1link_default: mac1link_default { 1293 function = "MAC1LINK"; 1294 groups = "MAC1LINK"; 1295 }; 1296 1297 pinctrl_mac2link_default: mac2link_default { 1298 function = "MAC2LINK"; 1299 groups = "MAC2LINK"; 1300 }; 1301 1302 pinctrl_mac3link_default: mac3link_default { 1303 function = "MAC3LINK"; 1304 groups = "MAC3LINK"; 1305 }; 1306 1307 pinctrl_mac4link_default: mac4link_default { 1308 function = "MAC4LINK"; 1309 groups = "MAC4LINK"; 1310 }; 1311 1312 pinctrl_mdio1_default: mdio1_default { 1313 function = "MDIO1"; 1314 groups = "MDIO1"; 1315 }; 1316 1317 pinctrl_mdio2_default: mdio2_default { 1318 function = "MDIO2"; 1319 groups = "MDIO2"; 1320 }; 1321 1322 pinctrl_mdio3_default: mdio3_default { 1323 function = "MDIO3"; 1324 groups = "MDIO3"; 1325 }; 1326 1327 pinctrl_mdio4_default: mdio4_default { 1328 function = "MDIO4"; 1329 groups = "MDIO4"; 1330 }; 1331 1332 pinctrl_ncts1_default: ncts1_default { 1333 function = "NCTS1"; 1334 groups = "NCTS1"; 1335 }; 1336 1337 pinctrl_ncts2_default: ncts2_default { 1338 function = "NCTS2"; 1339 groups = "NCTS2"; 1340 }; 1341 1342 pinctrl_ncts3_default: ncts3_default { 1343 function = "NCTS3"; 1344 groups = "NCTS3"; 1345 }; 1346 1347 pinctrl_ncts4_default: ncts4_default { 1348 function = "NCTS4"; 1349 groups = "NCTS4"; 1350 }; 1351 1352 pinctrl_ndcd1_default: ndcd1_default { 1353 function = "NDCD1"; 1354 groups = "NDCD1"; 1355 }; 1356 1357 pinctrl_ndcd2_default: ndcd2_default { 1358 function = "NDCD2"; 1359 groups = "NDCD2"; 1360 }; 1361 1362 pinctrl_ndcd3_default: ndcd3_default { 1363 function = "NDCD3"; 1364 groups = "NDCD3"; 1365 }; 1366 1367 pinctrl_ndcd4_default: ndcd4_default { 1368 function = "NDCD4"; 1369 groups = "NDCD4"; 1370 }; 1371 1372 pinctrl_ndsr1_default: ndsr1_default { 1373 function = "NDSR1"; 1374 groups = "NDSR1"; 1375 }; 1376 1377 pinctrl_ndsr2_default: ndsr2_default { 1378 function = "NDSR2"; 1379 groups = "NDSR2"; 1380 }; 1381 1382 pinctrl_ndsr3_default: ndsr3_default { 1383 function = "NDSR3"; 1384 groups = "NDSR3"; 1385 }; 1386 1387 pinctrl_ndsr4_default: ndsr4_default { 1388 function = "NDSR4"; 1389 groups = "NDSR4"; 1390 }; 1391 1392 pinctrl_ndtr1_default: ndtr1_default { 1393 function = "NDTR1"; 1394 groups = "NDTR1"; 1395 }; 1396 1397 pinctrl_ndtr2_default: ndtr2_default { 1398 function = "NDTR2"; 1399 groups = "NDTR2"; 1400 }; 1401 1402 pinctrl_ndtr3_default: ndtr3_default { 1403 function = "NDTR3"; 1404 groups = "NDTR3"; 1405 }; 1406 1407 pinctrl_ndtr4_default: ndtr4_default { 1408 function = "NDTR4"; 1409 groups = "NDTR4"; 1410 }; 1411 1412 pinctrl_nri1_default: nri1_default { 1413 function = "NRI1"; 1414 groups = "NRI1"; 1415 }; 1416 1417 pinctrl_nri2_default: nri2_default { 1418 function = "NRI2"; 1419 groups = "NRI2"; 1420 }; 1421 1422 pinctrl_nri3_default: nri3_default { 1423 function = "NRI3"; 1424 groups = "NRI3"; 1425 }; 1426 1427 pinctrl_nri4_default: nri4_default { 1428 function = "NRI4"; 1429 groups = "NRI4"; 1430 }; 1431 1432 pinctrl_nrts1_default: nrts1_default { 1433 function = "NRTS1"; 1434 groups = "NRTS1"; 1435 }; 1436 1437 pinctrl_nrts2_default: nrts2_default { 1438 function = "NRTS2"; 1439 groups = "NRTS2"; 1440 }; 1441 1442 pinctrl_nrts3_default: nrts3_default { 1443 function = "NRTS3"; 1444 groups = "NRTS3"; 1445 }; 1446 1447 pinctrl_nrts4_default: nrts4_default { 1448 function = "NRTS4"; 1449 groups = "NRTS4"; 1450 }; 1451 1452 pinctrl_oscclk_default: oscclk_default { 1453 function = "OSCCLK"; 1454 groups = "OSCCLK"; 1455 }; 1456 1457 pinctrl_pewake_default: pewake_default { 1458 function = "PEWAKE"; 1459 groups = "PEWAKE"; 1460 }; 1461 1462 pinctrl_pnor_default: pnor_default { 1463 function = "PNOR"; 1464 groups = "PNOR"; 1465 }; 1466 1467 pinctrl_pwm0_default: pwm0_default { 1468 function = "PWM0"; 1469 groups = "PWM0"; 1470 }; 1471 1472 pinctrl_pwm1_default: pwm1_default { 1473 function = "PWM1"; 1474 groups = "PWM1"; 1475 }; 1476 1477 pinctrl_pwm2_default: pwm2_default { 1478 function = "PWM2"; 1479 groups = "PWM2"; 1480 }; 1481 1482 pinctrl_pwm3_default: pwm3_default { 1483 function = "PWM3"; 1484 groups = "PWM3"; 1485 }; 1486 1487 pinctrl_pwm4_default: pwm4_default { 1488 function = "PWM4"; 1489 groups = "PWM4"; 1490 }; 1491 1492 pinctrl_pwm5_default: pwm5_default { 1493 function = "PWM5"; 1494 groups = "PWM5"; 1495 }; 1496 1497 pinctrl_pwm6_default: pwm6_default { 1498 function = "PWM6"; 1499 groups = "PWM6"; 1500 }; 1501 1502 pinctrl_pwm7_default: pwm7_default { 1503 function = "PWM7"; 1504 groups = "PWM7"; 1505 }; 1506 1507 pinctrl_rgmii1_default: rgmii1_default { 1508 function = "RGMII1"; 1509 groups = "RGMII1"; 1510 }; 1511 1512 pinctrl_rgmii2_default: rgmii2_default { 1513 function = "RGMII2"; 1514 groups = "RGMII2"; 1515 }; 1516 1517 pinctrl_rmii1_default: rmii1_default { 1518 function = "RMII1"; 1519 groups = "RMII1"; 1520 }; 1521 1522 pinctrl_rmii2_default: rmii2_default { 1523 function = "RMII2"; 1524 groups = "RMII2"; 1525 }; 1526 1527 pinctrl_rxd1_default: rxd1_default { 1528 function = "RXD1"; 1529 groups = "RXD1"; 1530 }; 1531 1532 pinctrl_rxd2_default: rxd2_default { 1533 function = "RXD2"; 1534 groups = "RXD2"; 1535 }; 1536 1537 pinctrl_rxd3_default: rxd3_default { 1538 function = "RXD3"; 1539 groups = "RXD3"; 1540 }; 1541 1542 pinctrl_rxd4_default: rxd4_default { 1543 function = "RXD4"; 1544 groups = "RXD4"; 1545 }; 1546 1547 pinctrl_salt1_default: salt1_default { 1548 function = "SALT1"; 1549 groups = "SALT1"; 1550 }; 1551 1552 pinctrl_salt10_default: salt10_default { 1553 function = "SALT10"; 1554 groups = "SALT10"; 1555 }; 1556 1557 pinctrl_salt11_default: salt11_default { 1558 function = "SALT11"; 1559 groups = "SALT11"; 1560 }; 1561 1562 pinctrl_salt12_default: salt12_default { 1563 function = "SALT12"; 1564 groups = "SALT12"; 1565 }; 1566 1567 pinctrl_salt13_default: salt13_default { 1568 function = "SALT13"; 1569 groups = "SALT13"; 1570 }; 1571 1572 pinctrl_salt14_default: salt14_default { 1573 function = "SALT14"; 1574 groups = "SALT14"; 1575 }; 1576 1577 pinctrl_salt2_default: salt2_default { 1578 function = "SALT2"; 1579 groups = "SALT2"; 1580 }; 1581 1582 pinctrl_salt3_default: salt3_default { 1583 function = "SALT3"; 1584 groups = "SALT3"; 1585 }; 1586 1587 pinctrl_salt4_default: salt4_default { 1588 function = "SALT4"; 1589 groups = "SALT4"; 1590 }; 1591 1592 pinctrl_salt5_default: salt5_default { 1593 function = "SALT5"; 1594 groups = "SALT5"; 1595 }; 1596 1597 pinctrl_salt6_default: salt6_default { 1598 function = "SALT6"; 1599 groups = "SALT6"; 1600 }; 1601 1602 pinctrl_salt7_default: salt7_default { 1603 function = "SALT7"; 1604 groups = "SALT7"; 1605 }; 1606 1607 pinctrl_salt8_default: salt8_default { 1608 function = "SALT8"; 1609 groups = "SALT8"; 1610 }; 1611 1612 pinctrl_salt9_default: salt9_default { 1613 function = "SALT9"; 1614 groups = "SALT9"; 1615 }; 1616 1617 pinctrl_scl1_default: scl1_default { 1618 function = "SCL1"; 1619 groups = "SCL1"; 1620 }; 1621 1622 pinctrl_scl2_default: scl2_default { 1623 function = "SCL2"; 1624 groups = "SCL2"; 1625 }; 1626 1627 pinctrl_sd1_default: sd1_default { 1628 function = "SD1"; 1629 groups = "SD1"; 1630 }; 1631 1632 pinctrl_sd2_default: sd2_default { 1633 function = "SD2"; 1634 groups = "SD2"; 1635 }; 1636 1637 pinctrl_emmc_default: emmc_default { 1638 function = "EMMC"; 1639 groups = "EMMC"; 1640 }; 1641 1642 pinctrl_sda1_default: sda1_default { 1643 function = "SDA1"; 1644 groups = "SDA1"; 1645 }; 1646 1647 pinctrl_sda2_default: sda2_default { 1648 function = "SDA2"; 1649 groups = "SDA2"; 1650 }; 1651 1652 pinctrl_sgps1_default: sgps1_default { 1653 function = "SGPS1"; 1654 groups = "SGPS1"; 1655 }; 1656 1657 pinctrl_sgps2_default: sgps2_default { 1658 function = "SGPS2"; 1659 groups = "SGPS2"; 1660 }; 1661 1662 pinctrl_sioonctrl_default: sioonctrl_default { 1663 function = "SIOONCTRL"; 1664 groups = "SIOONCTRL"; 1665 }; 1666 1667 pinctrl_siopbi_default: siopbi_default { 1668 function = "SIOPBI"; 1669 groups = "SIOPBI"; 1670 }; 1671 1672 pinctrl_siopbo_default: siopbo_default { 1673 function = "SIOPBO"; 1674 groups = "SIOPBO"; 1675 }; 1676 1677 pinctrl_siopwreq_default: siopwreq_default { 1678 function = "SIOPWREQ"; 1679 groups = "SIOPWREQ"; 1680 }; 1681 1682 pinctrl_siopwrgd_default: siopwrgd_default { 1683 function = "SIOPWRGD"; 1684 groups = "SIOPWRGD"; 1685 }; 1686 1687 pinctrl_sios3_default: sios3_default { 1688 function = "SIOS3"; 1689 groups = "SIOS3"; 1690 }; 1691 1692 pinctrl_sios5_default: sios5_default { 1693 function = "SIOS5"; 1694 groups = "SIOS5"; 1695 }; 1696 1697 pinctrl_siosci_default: siosci_default { 1698 function = "SIOSCI"; 1699 groups = "SIOSCI"; 1700 }; 1701 1702 pinctrl_spi1_default: spi1_default { 1703 function = "SPI1"; 1704 groups = "SPI1"; 1705 }; 1706 1707 pinctrl_spi1cs1_default: spi1cs1_default { 1708 function = "SPI1CS1"; 1709 groups = "SPI1CS1"; 1710 }; 1711 1712 pinctrl_spi1debug_default: spi1debug_default { 1713 function = "SPI1DEBUG"; 1714 groups = "SPI1DEBUG"; 1715 }; 1716 1717 pinctrl_spi1passthru_default: spi1passthru_default { 1718 function = "SPI1PASSTHRU"; 1719 groups = "SPI1PASSTHRU"; 1720 }; 1721 1722 pinctrl_spi2ck_default: spi2ck_default { 1723 function = "SPI2CK"; 1724 groups = "SPI2CK"; 1725 }; 1726 1727 pinctrl_spi2cs0_default: spi2cs0_default { 1728 function = "SPI2CS0"; 1729 groups = "SPI2CS0"; 1730 }; 1731 1732 pinctrl_spi2cs1_default: spi2cs1_default { 1733 function = "SPI2CS1"; 1734 groups = "SPI2CS1"; 1735 }; 1736 1737 pinctrl_spi2miso_default: spi2miso_default { 1738 function = "SPI2MISO"; 1739 groups = "SPI2MISO"; 1740 }; 1741 1742 pinctrl_spi2mosi_default: spi2mosi_default { 1743 function = "SPI2MOSI"; 1744 groups = "SPI2MOSI"; 1745 }; 1746 1747 pinctrl_timer3_default: timer3_default { 1748 function = "TIMER3"; 1749 groups = "TIMER3"; 1750 }; 1751 1752 pinctrl_timer4_default: timer4_default { 1753 function = "TIMER4"; 1754 groups = "TIMER4"; 1755 }; 1756 1757 pinctrl_timer5_default: timer5_default { 1758 function = "TIMER5"; 1759 groups = "TIMER5"; 1760 }; 1761 1762 pinctrl_timer6_default: timer6_default { 1763 function = "TIMER6"; 1764 groups = "TIMER6"; 1765 }; 1766 1767 pinctrl_timer7_default: timer7_default { 1768 function = "TIMER7"; 1769 groups = "TIMER7"; 1770 }; 1771 1772 pinctrl_timer8_default: timer8_default { 1773 function = "TIMER8"; 1774 groups = "TIMER8"; 1775 }; 1776 1777 pinctrl_txd1_default: txd1_default { 1778 function = "TXD1"; 1779 groups = "TXD1"; 1780 }; 1781 1782 pinctrl_txd2_default: txd2_default { 1783 function = "TXD2"; 1784 groups = "TXD2"; 1785 }; 1786 1787 pinctrl_txd3_default: txd3_default { 1788 function = "TXD3"; 1789 groups = "TXD3"; 1790 }; 1791 1792 pinctrl_txd4_default: txd4_default { 1793 function = "TXD4"; 1794 groups = "TXD4"; 1795 }; 1796 1797 pinctrl_uart6_default: uart6_default { 1798 function = "UART6"; 1799 groups = "UART6"; 1800 }; 1801 1802 pinctrl_usbcki_default: usbcki_default { 1803 function = "USBCKI"; 1804 groups = "USBCKI"; 1805 }; 1806 1807 pinctrl_usb2ah_default: usb2ah_default { 1808 function = "USB2AH"; 1809 groups = "USB2AH"; 1810 }; 1811 1812 pinctrl_usb11bhid_default: usb11bhid_default { 1813 function = "USB11BHID"; 1814 groups = "USB11BHID"; 1815 }; 1816 1817 pinctrl_usb2bh_default: usb2bh_default { 1818 function = "USB2BH"; 1819 groups = "USB2BH"; 1820 }; 1821 1822 pinctrl_vgabiosrom_default: vgabiosrom_default { 1823 function = "VGABIOSROM"; 1824 groups = "VGABIOSROM"; 1825 }; 1826 1827 pinctrl_vgahs_default: vgahs_default { 1828 function = "VGAHS"; 1829 groups = "VGAHS"; 1830 }; 1831 1832 pinctrl_vgavs_default: vgavs_default { 1833 function = "VGAVS"; 1834 groups = "VGAVS"; 1835 }; 1836 1837 pinctrl_vpi24_default: vpi24_default { 1838 function = "VPI24"; 1839 groups = "VPI24"; 1840 }; 1841 1842 pinctrl_vpo_default: vpo_default { 1843 function = "VPO"; 1844 groups = "VPO"; 1845 }; 1846 1847 pinctrl_wdtrst1_default: wdtrst1_default { 1848 function = "WDTRST1"; 1849 groups = "WDTRST1"; 1850 }; 1851 1852 pinctrl_wdtrst2_default: wdtrst2_default { 1853 function = "WDTRST2"; 1854 groups = "WDTRST2"; 1855 }; 1856 1857 pinctrl_pcierc_default: pcierc_default { 1858 function = "PCIERC"; 1859 groups = "PCIERC"; 1860 }; 1861}; 1862