1// SPDX-License-Identifier: GPL-2.0+ 2#include <dt-bindings/interrupt-controller/arm-gic.h> 3#include "skeleton.dtsi" 4 5/ { 6 model = "Aspeed BMC"; 7 compatible = "aspeed,ast2600"; 8 #address-cells = <1>; 9 #size-cells = <1>; 10 interrupt-parent = <&gic>; 11 12 aliases { 13 i2c0 = &i2c0; 14 i2c1 = &i2c1; 15 i2c2 = &i2c2; 16 i2c3 = &i2c3; 17 i2c4 = &i2c4; 18 i2c5 = &i2c5; 19 i2c6 = &i2c6; 20 i2c7 = &i2c7; 21 i2c8 = &i2c8; 22 i2c9 = &i2c9; 23 i2c10 = &i2c10; 24 i2c11 = &i2c11; 25 i2c12 = &i2c12; 26 i2c13 = &i2c13; 27 i2c14 = &i2c14; 28 i2c15 = &i2c15; 29 serial0 = &uart1; 30 serial1 = &uart2; 31 serial2 = &uart3; 32 serial3 = &uart4; 33 serial4 = &uart5; 34 serial5 = &uart6; 35 serial6 = &uart7; 36 serial7 = &uart8; 37 serial8 = &uart9; 38 serial9 = &uart10; 39 serial10 = &uart11; 40 serial11 = &uart12; 41 serial12 = &uart13; 42 }; 43 44 cpus { 45 #address-cells = <1>; 46 #size-cells = <0>; 47 enable-method = "aspeed,ast2600-smp"; 48 49 cpu@0 { 50 compatible = "arm,cortex-a7"; 51 device_type = "cpu"; 52 reg = <0>; 53 clock-frequency = <48000000>; 54 }; 55 56 cpu@1 { 57 compatible = "arm,cortex-a7"; 58 device_type = "cpu"; 59 reg = <1>; 60 clock-frequency = <48000000>; 61 }; 62 63 }; 64 65 timer { 66 compatible = "arm,armv7-timer"; 67 interrupt-parent = <&gic>; 68 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 69 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 70 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 71 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 72 clock-frequency = <25000000>; 73 }; 74 75 memory@80000000 { 76 device_type = "memory"; 77 reg = <0x80000000 0>; 78 }; 79 80 reserved-memory { 81 #address-cells = <1>; 82 #size-cells = <1>; 83 ranges; 84 85 gfx_memory: framebuffer { 86 size = <0x01000000>; 87 alignment = <0x01000000>; 88 compatible = "shared-dma-pool"; 89 reusable; 90 }; 91 92 video_memory: video { 93 size = <0x04000000>; 94 alignment = <0x01000000>; 95 compatible = "shared-dma-pool"; 96 no-map; 97 }; 98 }; 99 100 ahb { 101 compatible = "simple-bus"; 102 #address-cells = <1>; 103 #size-cells = <1>; 104 device_type = "soc"; 105 ranges; 106 107 gic: interrupt-controller@40461000 { 108 compatible = "arm,cortex-a7-gic"; 109 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 110 #interrupt-cells = <3>; 111 interrupt-controller; 112 interrupt-parent = <&gic>; 113 reg = <0x40461000 0x1000>, 114 <0x40462000 0x1000>, 115 <0x40464000 0x2000>, 116 <0x40466000 0x2000>; 117 }; 118 119 fmc: flash-controller@1e620000 { 120 reg = < 0x1e620000 0xc4 121 0x20000000 0x10000000 >; 122 #address-cells = <1>; 123 #size-cells = <0>; 124 compatible = "aspeed,ast2600-fmc"; 125 status = "disabled"; 126 interrupts = <19>; 127 clocks = <&scu ASPEED_CLK_AHB>; 128 flash@0 { 129 reg = < 0 >; 130 compatible = "jedec,spi-nor"; 131 status = "disabled"; 132 }; 133 flash@1 { 134 reg = < 1 >; 135 compatible = "jedec,spi-nor"; 136 status = "disabled"; 137 }; 138 flash@2 { 139 reg = < 2 >; 140 compatible = "jedec,spi-nor"; 141 status = "disabled"; 142 }; 143 }; 144 145 spi1: flash-controller@1e630000 { 146 reg = < 0x1e630000 0xc4 147 0x30000000 0x08000000 >; 148 #address-cells = <1>; 149 #size-cells = <0>; 150 compatible = "aspeed,ast2600-spi"; 151 clocks = <&scu ASPEED_CLK_AHB>; 152 status = "disabled"; 153 flash@0 { 154 reg = < 0 >; 155 compatible = "jedec,spi-nor"; 156 status = "disabled"; 157 }; 158 flash@1 { 159 reg = < 1 >; 160 compatible = "jedec,spi-nor"; 161 status = "disabled"; 162 }; 163 }; 164 165 spi2: flash-controller@1e631000 { 166 reg = < 0x1e631000 0xc4 167 0x38000000 0x08000000 >; 168 #address-cells = <1>; 169 #size-cells = <0>; 170 compatible = "aspeed,ast2600-spi"; 171 clocks = <&scu ASPEED_CLK_AHB>; 172 status = "disabled"; 173 flash@0 { 174 reg = < 0 >; 175 compatible = "jedec,spi-nor"; 176 status = "disabled"; 177 }; 178 flash@1 { 179 reg = < 1 >; 180 compatible = "jedec,spi-nor"; 181 status = "disabled"; 182 }; 183 }; 184 185 edac: sdram@1e6e0000 { 186 compatible = "aspeed,ast2600-sdram-edac"; 187 reg = <0x1e6e0000 0x174>; 188 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 189 }; 190 191 mdio: ethernet@1e650000 { 192 compatible = "aspeed,aspeed-mdio"; 193 reg = <0x1e650000 0x40>; 194 resets = <&rst ASPEED_RESET_MII>; 195 status = "disabled"; 196 }; 197 198 mac0: ethernet@1e660000 { 199 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 200 reg = <0x1e660000 0x180>, <0x1e650000 0x4>; 201 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 202 clocks = <&scu ASPEED_CLK_GATE_MAC1CLK>; 203 status = "disabled"; 204 }; 205 206 mac2: ftgmac@1e670000 { 207 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 208 reg = <0x1e670000 0x180>, <0x1e650010 0x4>; 209 #address-cells = <1>; 210 #size-cells = <0>; 211 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 212 clocks = <&scu ASPEED_CLK_GATE_MAC3CLK>; 213#if 0 214 phy-handle = <&phy0>; 215#endif 216 status = "disabled"; 217 }; 218 219 mac1: ftgmac@1e680000 { 220 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 221 reg = <0x1e680000 0x180>, <0x1e650008 0x4>; 222 #address-cells = <1>; 223 #size-cells = <0>; 224 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 225 clocks = <&scu ASPEED_CLK_GATE_MAC2CLK>; 226#if 0 227 phy-handle = <&phy0>; 228#endif 229 status = "disabled"; 230 }; 231 232 mac3: ftgmac@1e690000 { 233 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 234 reg = <0x1e690000 0x180>, <0x1e650018 0x4>; 235 #address-cells = <1>; 236 #size-cells = <0>; 237 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 238 clocks = <&scu ASPEED_CLK_GATE_MAC4CLK>; 239#if 0 240 phy-handle = <&phy0>; 241#endif 242 status = "disabled"; 243 }; 244 245 246 apb { 247 compatible = "simple-bus"; 248 #address-cells = <1>; 249 #size-cells = <1>; 250 ranges; 251 252 syscon: syscon@1e6e2000 { 253 compatible = "aspeed,g6-scu", "syscon", "simple-mfd"; 254 reg = <0x1e6e2000 0x1000>; 255 #address-cells = <1>; 256 #size-cells = <1>; 257 #clock-cells = <1>; 258 #reset-cells = <1>; 259 ranges = <0 0x1e6e2000 0x1000>; 260 261 pinctrl: pinctrl { 262 compatible = "aspeed,g6-pinctrl"; 263 aspeed,external-nodes = <&gfx &lhc>; 264 265 }; 266 267 vga_scratch: scratch { 268 compatible = "aspeed,bmc-misc"; 269 }; 270 271 scu_ic0: interrupt-controller@0 { 272 #interrupt-cells = <1>; 273 compatible = "aspeed,ast2600-scu-ic"; 274 reg = <0x560 0x10>; 275 interrupt-parent = <&gic>; 276 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 277 interrupt-controller; 278 }; 279 280 scu_ic1: interrupt-controller@1 { 281 #interrupt-cells = <1>; 282 compatible = "aspeed,ast2600-scu-ic"; 283 reg = <0x570 0x10>; 284 interrupt-parent = <&gic>; 285 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 286 interrupt-controller; 287 }; 288 289 }; 290 291 smp-memram@0 { 292 compatible = "aspeed,ast2600-smpmem", "syscon"; 293 reg = <0x1e6e2180 0x40>; 294 }; 295 296 gfx: display@1e6e6000 { 297 compatible = "aspeed,ast2500-gfx", "syscon"; 298 reg = <0x1e6e6000 0x1000>; 299 reg-io-width = <4>; 300 }; 301 302 sdhci: sdhci@1e740000 { 303 #interrupt-cells = <1>; 304 compatible = "aspeed,aspeed-sdhci-irq", "simple-mfd"; 305 reg = <0x1e740000 0x1000>; 306 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 307 interrupt-controller; 308 clocks = <&scu ASPEED_CLK_GATE_SDCLK>, <&scu ASPEED_CLK_GATE_SDEXTCLK>; 309 clock-names = "ctrlclk", "extclk"; 310 #address-cells = <1>; 311 #size-cells = <1>; 312 ranges = <0x0 0x1e740000 0x1000>; 313 314 sdhci_slot0: sdhci_slot0@100 { 315 compatible = "aspeed,sdhci-ast2600"; 316 reg = <0x100 0x100>; 317 interrupts = <0>; 318 interrupt-parent = <&sdhci>; 319 sdhci,auto-cmd12; 320 clocks = <&scu ASPEED_CLK_SDIO>; 321#if 0 322 power-gpio = <&gpio0 ASPEED_GPIO(V, 0) GPIO_ACTIVE_LOW>; 323 power-switch-gpio = <&gpio0 ASPEED_GPIO(V, 1) GPIO_ACTIVE_LOW>; 324#endif 325 status = "disabled"; 326 }; 327 328 sdhci_slot1: sdhci_slot1@200 { 329 compatible = "aspeed,sdhci-ast2600"; 330 reg = <0x200 0x100>; 331 interrupts = <1>; 332 interrupt-parent = <&sdhci>; 333 sdhci,auto-cmd12; 334 clocks = <&scu ASPEED_CLK_SDIO>; 335#if 0 336 power-gpio = <&gpio0 ASPEED_GPIO(V, 2) GPIO_ACTIVE_LOW>; 337 power-switch-gpio = <&gpio0 ASPEED_GPIO(V, 3) GPIO_ACTIVE_LOW>; 338#endif 339 status = "disabled"; 340 }; 341 342 }; 343 344 emmc: emmc@1e750000 { 345 #interrupt-cells = <1>; 346 compatible = "aspeed,aspeed-emmc-irq", "simple-mfd"; 347 reg = <0x1e750000 0x1000>; 348 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 349 interrupt-controller; 350 clocks = <&scu ASPEED_CLK_GATE_EMMCCLK>, <&scu ASPEED_CLK_GATE_EMMCEXTCLK>; 351 clock-names = "ctrlclk", "extclk"; 352 #address-cells = <1>; 353 #size-cells = <1>; 354 ranges = <0x0 0x1e750000 0x1000>; 355 356 emmc_slot0: emmc_slot0@100 { 357 compatible = "aspeed,emmc-ast2600"; 358 reg = <0x100 0x100>; 359 interrupts = <0>; 360 interrupt-parent = <&emmc>; 361 clocks = <&scu ASPEED_CLK_EMMC>; 362 status = "disabled"; 363 }; 364 365 }; 366 367 uart1: serial@1e783000 { 368 compatible = "ns16550a"; 369 reg = <0x1e783000 0x20>; 370 reg-shift = <2>; 371 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 372 clocks = <&scu ASPEED_CLK_GATE_UART1CLK>; 373 no-loopback-test; 374 status = "disabled"; 375 }; 376 377 uart5: serial@1e784000 { 378 compatible = "ns16550a"; 379 reg = <0x1e784000 0x1000>; 380 reg-shift = <2>; 381 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 382 clocks = <&scu ASPEED_CLK_GATE_UART5CLK>; 383 no-loopback-test; 384 status = "disabled"; 385 }; 386 387 wdt1: watchdog@1e785000 { 388 compatible = "aspeed,ast2600-wdt"; 389 reg = <0x1e785000 0x40>; 390 }; 391 392 wdt2: watchdog@1e785040 { 393 compatible = "aspeed,ast2600-wdt"; 394 reg = <0x1e785040 0x40>; 395 }; 396 397 wdt3: watchdog@1e785080 { 398 compatible = "aspeed,ast2600-wdt"; 399 reg = <0x1e785080 0x40>; 400 }; 401 402 wdt4: watchdog@1e7850C0 { 403 compatible = "aspeed,ast2600-wdt"; 404 reg = <0x1e7850C0 0x40>; 405 }; 406 407 lpc: lpc@1e789000 { 408 compatible = "aspeed,ast-lpc", "simple-mfd", "syscon"; 409 reg = <0x1e789000 0x200>; 410 411 #address-cells = <1>; 412 #size-cells = <1>; 413 ranges = <0x0 0x1e789000 0x1000>; 414 415 lpc_bmc: lpc-bmc@0 { 416 compatible = "aspeed,ast2600-lpc-bmc", "simple-mfd", "syscon"; 417 reg = <0x0 0x80>; 418 reg-io-width = <4>; 419 #address-cells = <1>; 420 #size-cells = <1>; 421 ranges = <0x0 0x0 0x80>; 422 423 kcs1: kcs1@0 { 424 compatible = "aspeed,ast2600-kcs-bmc"; 425 reg = <0x0 0x80>; 426 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 427 kcs_chan = <1>; 428 kcs_addr = <0xCA0>; 429 status = "disabled"; 430 }; 431 432 kcs2: kcs2@0 { 433 compatible = "aspeed,ast2600-kcs-bmc"; 434 reg = <0x0 0x80>; 435 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 436 kcs_chan = <2>; 437 kcs_addr = <0xCA8>; 438 status = "disabled"; 439 }; 440 441 kcs3: kcs3@0 { 442 compatible = "aspeed,ast2600-kcs-bmc"; 443 reg = <0x0 0x80>; 444 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 445 kcs_chan = <3>; 446 kcs_addr = <0xCA2>; 447 }; 448 449 kcs4: kcs4@0 { 450 compatible = "aspeed,ast2600-kcs-bmc"; 451 reg = <0x0 0x120>; 452 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 453 kcs_chan = <4>; 454 kcs_addr = <0xCA4>; 455 status = "disabled"; 456 }; 457 458 }; 459 460 lpc_host: lpc-host@80 { 461 compatible = "aspeed,ast2600-lpc-host", "simple-mfd", "syscon"; 462 reg = <0x80 0x1e0>; 463 reg-io-width = <4>; 464 465 #address-cells = <1>; 466 #size-cells = <1>; 467 ranges = <0x0 0x80 0x1e0>; 468 469 lpc_ctrl: lpc-ctrl@0 { 470 compatible = "aspeed,ast2600-lpc-ctrl"; 471 reg = <0x0 0x80>; 472 status = "disabled"; 473 }; 474 475 lpc_snoop: lpc-snoop@0 { 476 compatible = "aspeed,ast2600-lpc-snoop"; 477 reg = <0x0 0x80>; 478 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 479 snoop-ports = <0x80>; 480 status = "disabled"; 481 }; 482 483 lhc: lhc@20 { 484 compatible = "aspeed,ast2600-lhc"; 485 reg = <0x20 0x24 0x48 0x8>; 486 }; 487 488 lpc_reset: reset-controller@18 { 489 compatible = "aspeed,ast2600-lpc-reset"; 490 reg = <0x18 0x4>; 491 #reset-cells = <1>; 492 status = "disabled"; 493 }; 494 495 ibt: ibt@c0 { 496 compatible = "aspeed,ast2600-ibt-bmc"; 497 reg = <0xc0 0x18>; 498 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 499 status = "disabled"; 500 }; 501 502 sio_regs: regs { 503 compatible = "aspeed,bmc-misc"; 504 }; 505 506 mbox: mbox@180 { 507 compatible = "aspeed,ast2600-mbox"; 508 reg = <0x180 0x5c>; 509 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 510 #mbox-cells = <1>; 511 status = "disabled"; 512 }; 513 }; 514 }; 515 516 uart2: serial@1e78d000 { 517 compatible = "ns16550a"; 518 reg = <0x1e78d000 0x20>; 519 reg-shift = <2>; 520 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 521 clocks = <&scu ASPEED_CLK_GATE_UART2CLK>; 522 no-loopback-test; 523 status = "disabled"; 524 }; 525 526 uart3: serial@1e78e000 { 527 compatible = "ns16550a"; 528 reg = <0x1e78e000 0x20>; 529 reg-shift = <2>; 530 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 531 clocks = <&scu ASPEED_CLK_GATE_UART3CLK>; 532 no-loopback-test; 533 status = "disabled"; 534 }; 535 536 uart4: serial@1e78f000 { 537 compatible = "ns16550a"; 538 reg = <0x1e78f000 0x20>; 539 reg-shift = <2>; 540 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 541 clocks = <&scu ASPEED_CLK_GATE_UART4CLK>; 542 no-loopback-test; 543 status = "disabled"; 544 }; 545 546 i2c: bus@1e78a000 { 547 compatible = "simple-bus"; 548 #address-cells = <1>; 549 #size-cells = <1>; 550 ranges = <0 0x1e78a000 0x1000>; 551 }; 552 553 uart6: serial@1e790000 { 554 compatible = "ns16550a"; 555 reg = <0x1e790000 0x20>; 556 reg-shift = <2>; 557 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 558 clocks = <&scu ASPEED_CLK_GATE_UART6CLK>; 559 no-loopback-test; 560 status = "disabled"; 561 }; 562 563 uart7: serial@1e790100 { 564 compatible = "ns16550a"; 565 reg = <0x1e790100 0x20>; 566 reg-shift = <2>; 567 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 568 clocks = <&scu ASPEED_CLK_GATE_UART7CLK>; 569 no-loopback-test; 570 status = "disabled"; 571 }; 572 573 uart8: serial@1e790200 { 574 compatible = "ns16550a"; 575 reg = <0x1e790200 0x20>; 576 reg-shift = <2>; 577 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 578 clocks = <&scu ASPEED_CLK_GATE_UART8CLK>; 579 no-loopback-test; 580 status = "disabled"; 581 }; 582 583 uart9: serial@1e790300 { 584 compatible = "ns16550a"; 585 reg = <0x1e790300 0x20>; 586 reg-shift = <2>; 587 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 588 clocks = <&scu ASPEED_CLK_GATE_UART9CLK>; 589 no-loopback-test; 590 status = "disabled"; 591 }; 592 593 uart10: serial@1e790400 { 594 compatible = "ns16550a"; 595 reg = <0x1e790400 0x20>; 596 reg-shift = <2>; 597 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 598 clocks = <&scu ASPEED_CLK_GATE_UART10CLK>; 599 no-loopback-test; 600 status = "disabled"; 601 }; 602 603 uart11: serial@1e790500 { 604 compatible = "ns16550a"; 605 reg = <0x1e790400 0x20>; 606 reg-shift = <2>; 607 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 608 clocks = <&scu ASPEED_CLK_GATE_UART11CLK>; 609 no-loopback-test; 610 status = "disabled"; 611 }; 612 613 uart12: serial@1e790600 { 614 compatible = "ns16550a"; 615 reg = <0x1e790600 0x20>; 616 reg-shift = <2>; 617 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 618 clocks = <&scu ASPEED_CLK_GATE_UART12CLK>; 619 no-loopback-test; 620 status = "disabled"; 621 }; 622 623 uart13: serial@1e790700 { 624 compatible = "ns16550a"; 625 reg = <0x1e790700 0x20>; 626 reg-shift = <2>; 627 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 628 clocks = <&scu ASPEED_CLK_GATE_UART13CLK>; 629 no-loopback-test; 630 status = "disabled"; 631 }; 632 633 634 635 }; 636 637 }; 638 639}; 640 641&i2c { 642 i2cglobal: i2cg@00 { 643 compatible = "aspeed,ast2600-i2c-global"; 644 reg = <0x0 0x40>; 645 resets = <&rst ASPEED_RESET_I2C>; 646#if 0 647 new-mode; 648#endif 649 }; 650 651 i2c0: i2c@80 { 652 #address-cells = <1>; 653 #size-cells = <0>; 654 #interrupt-cells = <1>; 655 656 reg = <0x80 0x80 0xC00 0x20>; 657 compatible = "aspeed,ast2600-i2c-bus"; 658 bus-frequency = <100000>; 659 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 660 clocks = <&scu ASPEED_CLK_APB>; 661 status = "disabled"; 662 }; 663 664 i2c1: i2c@100 { 665 #address-cells = <1>; 666 #size-cells = <0>; 667 #interrupt-cells = <1>; 668 669 reg = <0x100 0x80 0xC20 0x20>; 670 compatible = "aspeed,ast2600-i2c-bus"; 671 bus-frequency = <100000>; 672 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 673 clocks = <&scu ASPEED_CLK_APB>; 674 status = "disabled"; 675 }; 676 677 i2c2: i2c@180 { 678 #address-cells = <1>; 679 #size-cells = <0>; 680 #interrupt-cells = <1>; 681 682 reg = <0x180 0x80 0xC40 0x20>; 683 compatible = "aspeed,ast2600-i2c-bus"; 684 bus-frequency = <100000>; 685 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 686 clocks = <&scu ASPEED_CLK_APB>; 687 }; 688 689 i2c3: i2c@200 { 690 #address-cells = <1>; 691 #size-cells = <0>; 692 #interrupt-cells = <1>; 693 694 reg = <0x200 0x40 0xC60 0x20>; 695 compatible = "aspeed,ast2600-i2c-bus"; 696 bus-frequency = <100000>; 697 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 698 clocks = <&scu ASPEED_CLK_APB>; 699 }; 700 701 i2c4: i2c@280 { 702 #address-cells = <1>; 703 #size-cells = <0>; 704 #interrupt-cells = <1>; 705 706 reg = <0x280 0x80 0xC80 0x20>; 707 compatible = "aspeed,ast2600-i2c-bus"; 708 bus-frequency = <100000>; 709 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 710 clocks = <&scu ASPEED_CLK_APB>; 711 }; 712 713 i2c5: i2c@300 { 714 #address-cells = <1>; 715 #size-cells = <0>; 716 #interrupt-cells = <1>; 717 718 reg = <0x300 0x40 0xCA0 0x20>; 719 compatible = "aspeed,ast2600-i2c-bus"; 720 bus-frequency = <100000>; 721 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 722 clocks = <&scu ASPEED_CLK_APB>; 723 }; 724 725 i2c6: i2c@380 { 726 #address-cells = <1>; 727 #size-cells = <0>; 728 #interrupt-cells = <1>; 729 730 reg = <0x380 0x80 0xCC0 0x20>; 731 compatible = "aspeed,ast2600-i2c-bus"; 732 bus-frequency = <100000>; 733 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 734 clocks = <&scu ASPEED_CLK_APB>; 735 }; 736 737 i2c7: i2c@400 { 738 #address-cells = <1>; 739 #size-cells = <0>; 740 #interrupt-cells = <1>; 741 742 reg = <0x400 0x80 0xCE0 0x20>; 743 compatible = "aspeed,ast2600-i2c-bus"; 744 bus-frequency = <100000>; 745 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 746 clocks = <&scu ASPEED_CLK_APB>; 747 }; 748 749 i2c8: i2c@480 { 750 #address-cells = <1>; 751 #size-cells = <0>; 752 #interrupt-cells = <1>; 753 754 reg = <0x480 0x80 0xD00 0x20>; 755 compatible = "aspeed,ast2600-i2c-bus"; 756 bus-frequency = <100000>; 757 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 758 clocks = <&scu ASPEED_CLK_APB>; 759 }; 760 761 i2c9: i2c@500 { 762 #address-cells = <1>; 763 #size-cells = <0>; 764 #interrupt-cells = <1>; 765 766 reg = <0x500 0x80 0xD20 0x20>; 767 compatible = "aspeed,ast2600-i2c-bus"; 768 bus-frequency = <100000>; 769 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 770 clocks = <&scu ASPEED_CLK_APB>; 771 status = "disabled"; 772 }; 773 774 i2c10: i2c@580 { 775 #address-cells = <1>; 776 #size-cells = <0>; 777 #interrupt-cells = <1>; 778 779 reg = <0x580 0x80 0xD40 0x20>; 780 compatible = "aspeed,ast2600-i2c-bus"; 781 bus-frequency = <100000>; 782 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 783 clocks = <&scu ASPEED_CLK_APB>; 784 status = "disabled"; 785 }; 786 787 i2c11: i2c@600 { 788 #address-cells = <1>; 789 #size-cells = <0>; 790 #interrupt-cells = <1>; 791 792 reg = <0x600 0x80 0xD60 0x20>; 793 compatible = "aspeed,ast2600-i2c-bus"; 794 bus-frequency = <100000>; 795 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 796 clocks = <&scu ASPEED_CLK_APB>; 797 status = "disabled"; 798 }; 799 800 i2c12: i2c@680 { 801 #address-cells = <1>; 802 #size-cells = <0>; 803 #interrupt-cells = <1>; 804 805 reg = <0x680 0x80 0xD80 0x20>; 806 compatible = "aspeed,ast2600-i2c-bus"; 807 bus-frequency = <100000>; 808 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 809 clocks = <&scu ASPEED_CLK_APB>; 810 status = "disabled"; 811 }; 812 813 i2c13: i2c@700 { 814 #address-cells = <1>; 815 #size-cells = <0>; 816 #interrupt-cells = <1>; 817 818 reg = <0x700 0x80 0xDA0 0x20>; 819 compatible = "aspeed,ast2600-i2c-bus"; 820 bus-frequency = <100000>; 821 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 822 clocks = <&scu ASPEED_CLK_APB>; 823 status = "disabled"; 824 }; 825 826 i2c14: i2c@780 { 827 #address-cells = <1>; 828 #size-cells = <0>; 829 #interrupt-cells = <1>; 830 831 reg = <0x780 0x80 0xDC0 0x20>; 832 compatible = "aspeed,ast2600-i2c-bus"; 833 bus-frequency = <100000>; 834 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 835 clocks = <&scu ASPEED_CLK_APB>; 836 status = "disabled"; 837 }; 838 839 i2c15: i2c@800 { 840 #address-cells = <1>; 841 #size-cells = <0>; 842 #interrupt-cells = <1>; 843 844 reg = <0x800 0x80 0xDE0 0x20>; 845 compatible = "aspeed,ast2600-i2c-bus"; 846 bus-frequency = <100000>; 847 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 848 clocks = <&scu ASPEED_CLK_APB>; 849 status = "disabled"; 850 }; 851 852}; 853 854&pinctrl { 855 pinctrl_acpi_default: acpi_default { 856 function = "ACPI"; 857 groups = "ACPI"; 858 }; 859 860 pinctrl_adc0_default: adc0_default { 861 function = "ADC0"; 862 groups = "ADC0"; 863 }; 864 865 pinctrl_adc1_default: adc1_default { 866 function = "ADC1"; 867 groups = "ADC1"; 868 }; 869 870 pinctrl_adc10_default: adc10_default { 871 function = "ADC10"; 872 groups = "ADC10"; 873 }; 874 875 pinctrl_adc11_default: adc11_default { 876 function = "ADC11"; 877 groups = "ADC11"; 878 }; 879 880 pinctrl_adc12_default: adc12_default { 881 function = "ADC12"; 882 groups = "ADC12"; 883 }; 884 885 pinctrl_adc13_default: adc13_default { 886 function = "ADC13"; 887 groups = "ADC13"; 888 }; 889 890 pinctrl_adc14_default: adc14_default { 891 function = "ADC14"; 892 groups = "ADC14"; 893 }; 894 895 pinctrl_adc15_default: adc15_default { 896 function = "ADC15"; 897 groups = "ADC15"; 898 }; 899 900 pinctrl_adc2_default: adc2_default { 901 function = "ADC2"; 902 groups = "ADC2"; 903 }; 904 905 pinctrl_adc3_default: adc3_default { 906 function = "ADC3"; 907 groups = "ADC3"; 908 }; 909 910 pinctrl_adc4_default: adc4_default { 911 function = "ADC4"; 912 groups = "ADC4"; 913 }; 914 915 pinctrl_adc5_default: adc5_default { 916 function = "ADC5"; 917 groups = "ADC5"; 918 }; 919 920 pinctrl_adc6_default: adc6_default { 921 function = "ADC6"; 922 groups = "ADC6"; 923 }; 924 925 pinctrl_adc7_default: adc7_default { 926 function = "ADC7"; 927 groups = "ADC7"; 928 }; 929 930 pinctrl_adc8_default: adc8_default { 931 function = "ADC8"; 932 groups = "ADC8"; 933 }; 934 935 pinctrl_adc9_default: adc9_default { 936 function = "ADC9"; 937 groups = "ADC9"; 938 }; 939 940 pinctrl_bmcint_default: bmcint_default { 941 function = "BMCINT"; 942 groups = "BMCINT"; 943 }; 944 945 pinctrl_ddcclk_default: ddcclk_default { 946 function = "DDCCLK"; 947 groups = "DDCCLK"; 948 }; 949 950 pinctrl_ddcdat_default: ddcdat_default { 951 function = "DDCDAT"; 952 groups = "DDCDAT"; 953 }; 954 955 pinctrl_espi_default: espi_default { 956 function = "ESPI"; 957 groups = "ESPI"; 958 }; 959 960 pinctrl_fwspics1_default: fwspics1_default { 961 function = "FWSPICS1"; 962 groups = "FWSPICS1"; 963 }; 964 965 pinctrl_fwspics2_default: fwspics2_default { 966 function = "FWSPICS2"; 967 groups = "FWSPICS2"; 968 }; 969 970 pinctrl_gpid0_default: gpid0_default { 971 function = "GPID0"; 972 groups = "GPID0"; 973 }; 974 975 pinctrl_gpid2_default: gpid2_default { 976 function = "GPID2"; 977 groups = "GPID2"; 978 }; 979 980 pinctrl_gpid4_default: gpid4_default { 981 function = "GPID4"; 982 groups = "GPID4"; 983 }; 984 985 pinctrl_gpid6_default: gpid6_default { 986 function = "GPID6"; 987 groups = "GPID6"; 988 }; 989 990 pinctrl_gpie0_default: gpie0_default { 991 function = "GPIE0"; 992 groups = "GPIE0"; 993 }; 994 995 pinctrl_gpie2_default: gpie2_default { 996 function = "GPIE2"; 997 groups = "GPIE2"; 998 }; 999 1000 pinctrl_gpie4_default: gpie4_default { 1001 function = "GPIE4"; 1002 groups = "GPIE4"; 1003 }; 1004 1005 pinctrl_gpie6_default: gpie6_default { 1006 function = "GPIE6"; 1007 groups = "GPIE6"; 1008 }; 1009 1010 pinctrl_i2c10_default: i2c10_default { 1011 function = "I2C10"; 1012 groups = "I2C10"; 1013 }; 1014 1015 pinctrl_i2c11_default: i2c11_default { 1016 function = "I2C11"; 1017 groups = "I2C11"; 1018 }; 1019 1020 pinctrl_i2c12_default: i2c12_default { 1021 function = "I2C12"; 1022 groups = "I2C12"; 1023 }; 1024 1025 pinctrl_i2c13_default: i2c13_default { 1026 function = "I2C13"; 1027 groups = "I2C13"; 1028 }; 1029 1030 pinctrl_i2c14_default: i2c14_default { 1031 function = "I2C14"; 1032 groups = "I2C14"; 1033 }; 1034 1035 pinctrl_i2c3_default: i2c3_default { 1036 function = "I2C3"; 1037 groups = "I2C3"; 1038 }; 1039 1040 pinctrl_i2c4_default: i2c4_default { 1041 function = "I2C4"; 1042 groups = "I2C4"; 1043 }; 1044 1045 pinctrl_i2c5_default: i2c5_default { 1046 function = "I2C5"; 1047 groups = "I2C5"; 1048 }; 1049 1050 pinctrl_i2c6_default: i2c6_default { 1051 function = "I2C6"; 1052 groups = "I2C6"; 1053 }; 1054 1055 pinctrl_i2c7_default: i2c7_default { 1056 function = "I2C7"; 1057 groups = "I2C7"; 1058 }; 1059 1060 pinctrl_i2c8_default: i2c8_default { 1061 function = "I2C8"; 1062 groups = "I2C8"; 1063 }; 1064 1065 pinctrl_i2c9_default: i2c9_default { 1066 function = "I2C9"; 1067 groups = "I2C9"; 1068 }; 1069 1070 pinctrl_lad0_default: lad0_default { 1071 function = "LAD0"; 1072 groups = "LAD0"; 1073 }; 1074 1075 pinctrl_lad1_default: lad1_default { 1076 function = "LAD1"; 1077 groups = "LAD1"; 1078 }; 1079 1080 pinctrl_lad2_default: lad2_default { 1081 function = "LAD2"; 1082 groups = "LAD2"; 1083 }; 1084 1085 pinctrl_lad3_default: lad3_default { 1086 function = "LAD3"; 1087 groups = "LAD3"; 1088 }; 1089 1090 pinctrl_lclk_default: lclk_default { 1091 function = "LCLK"; 1092 groups = "LCLK"; 1093 }; 1094 1095 pinctrl_lframe_default: lframe_default { 1096 function = "LFRAME"; 1097 groups = "LFRAME"; 1098 }; 1099 1100 pinctrl_lpchc_default: lpchc_default { 1101 function = "LPCHC"; 1102 groups = "LPCHC"; 1103 }; 1104 1105 pinctrl_lpcpd_default: lpcpd_default { 1106 function = "LPCPD"; 1107 groups = "LPCPD"; 1108 }; 1109 1110 pinctrl_lpcplus_default: lpcplus_default { 1111 function = "LPCPLUS"; 1112 groups = "LPCPLUS"; 1113 }; 1114 1115 pinctrl_lpcpme_default: lpcpme_default { 1116 function = "LPCPME"; 1117 groups = "LPCPME"; 1118 }; 1119 1120 pinctrl_lpcrst_default: lpcrst_default { 1121 function = "LPCRST"; 1122 groups = "LPCRST"; 1123 }; 1124 1125 pinctrl_lpcsmi_default: lpcsmi_default { 1126 function = "LPCSMI"; 1127 groups = "LPCSMI"; 1128 }; 1129 1130 pinctrl_lsirq_default: lsirq_default { 1131 function = "LSIRQ"; 1132 groups = "LSIRQ"; 1133 }; 1134 1135 pinctrl_mac1link_default: mac1link_default { 1136 function = "MAC1LINK"; 1137 groups = "MAC1LINK"; 1138 }; 1139 1140 pinctrl_mac2link_default: mac2link_default { 1141 function = "MAC2LINK"; 1142 groups = "MAC2LINK"; 1143 }; 1144 1145 pinctrl_mac3link_default: mac3link_default { 1146 function = "MAC3LINK"; 1147 groups = "MAC3LINK"; 1148 }; 1149 1150 pinctrl_mac4link_default: mac4link_default { 1151 function = "MAC4LINK"; 1152 groups = "MAC4LINK"; 1153 }; 1154 1155 pinctrl_mdio1_default: mdio1_default { 1156 function = "MDIO1"; 1157 groups = "MDIO1"; 1158 }; 1159 1160 pinctrl_mdio2_default: mdio2_default { 1161 function = "MDIO2"; 1162 groups = "MDIO2"; 1163 }; 1164 1165 pinctrl_mdio3_default: mdio3_default { 1166 function = "MDIO3"; 1167 groups = "MDIO3"; 1168 }; 1169 1170 pinctrl_mdio4_default: mdio4_default { 1171 function = "MDIO4"; 1172 groups = "MDIO4"; 1173 }; 1174 1175 pinctrl_ncts1_default: ncts1_default { 1176 function = "NCTS1"; 1177 groups = "NCTS1"; 1178 }; 1179 1180 pinctrl_ncts2_default: ncts2_default { 1181 function = "NCTS2"; 1182 groups = "NCTS2"; 1183 }; 1184 1185 pinctrl_ncts3_default: ncts3_default { 1186 function = "NCTS3"; 1187 groups = "NCTS3"; 1188 }; 1189 1190 pinctrl_ncts4_default: ncts4_default { 1191 function = "NCTS4"; 1192 groups = "NCTS4"; 1193 }; 1194 1195 pinctrl_ndcd1_default: ndcd1_default { 1196 function = "NDCD1"; 1197 groups = "NDCD1"; 1198 }; 1199 1200 pinctrl_ndcd2_default: ndcd2_default { 1201 function = "NDCD2"; 1202 groups = "NDCD2"; 1203 }; 1204 1205 pinctrl_ndcd3_default: ndcd3_default { 1206 function = "NDCD3"; 1207 groups = "NDCD3"; 1208 }; 1209 1210 pinctrl_ndcd4_default: ndcd4_default { 1211 function = "NDCD4"; 1212 groups = "NDCD4"; 1213 }; 1214 1215 pinctrl_ndsr1_default: ndsr1_default { 1216 function = "NDSR1"; 1217 groups = "NDSR1"; 1218 }; 1219 1220 pinctrl_ndsr2_default: ndsr2_default { 1221 function = "NDSR2"; 1222 groups = "NDSR2"; 1223 }; 1224 1225 pinctrl_ndsr3_default: ndsr3_default { 1226 function = "NDSR3"; 1227 groups = "NDSR3"; 1228 }; 1229 1230 pinctrl_ndsr4_default: ndsr4_default { 1231 function = "NDSR4"; 1232 groups = "NDSR4"; 1233 }; 1234 1235 pinctrl_ndtr1_default: ndtr1_default { 1236 function = "NDTR1"; 1237 groups = "NDTR1"; 1238 }; 1239 1240 pinctrl_ndtr2_default: ndtr2_default { 1241 function = "NDTR2"; 1242 groups = "NDTR2"; 1243 }; 1244 1245 pinctrl_ndtr3_default: ndtr3_default { 1246 function = "NDTR3"; 1247 groups = "NDTR3"; 1248 }; 1249 1250 pinctrl_ndtr4_default: ndtr4_default { 1251 function = "NDTR4"; 1252 groups = "NDTR4"; 1253 }; 1254 1255 pinctrl_nri1_default: nri1_default { 1256 function = "NRI1"; 1257 groups = "NRI1"; 1258 }; 1259 1260 pinctrl_nri2_default: nri2_default { 1261 function = "NRI2"; 1262 groups = "NRI2"; 1263 }; 1264 1265 pinctrl_nri3_default: nri3_default { 1266 function = "NRI3"; 1267 groups = "NRI3"; 1268 }; 1269 1270 pinctrl_nri4_default: nri4_default { 1271 function = "NRI4"; 1272 groups = "NRI4"; 1273 }; 1274 1275 pinctrl_nrts1_default: nrts1_default { 1276 function = "NRTS1"; 1277 groups = "NRTS1"; 1278 }; 1279 1280 pinctrl_nrts2_default: nrts2_default { 1281 function = "NRTS2"; 1282 groups = "NRTS2"; 1283 }; 1284 1285 pinctrl_nrts3_default: nrts3_default { 1286 function = "NRTS3"; 1287 groups = "NRTS3"; 1288 }; 1289 1290 pinctrl_nrts4_default: nrts4_default { 1291 function = "NRTS4"; 1292 groups = "NRTS4"; 1293 }; 1294 1295 pinctrl_oscclk_default: oscclk_default { 1296 function = "OSCCLK"; 1297 groups = "OSCCLK"; 1298 }; 1299 1300 pinctrl_pewake_default: pewake_default { 1301 function = "PEWAKE"; 1302 groups = "PEWAKE"; 1303 }; 1304 1305 pinctrl_pnor_default: pnor_default { 1306 function = "PNOR"; 1307 groups = "PNOR"; 1308 }; 1309 1310 pinctrl_pwm0_default: pwm0_default { 1311 function = "PWM0"; 1312 groups = "PWM0"; 1313 }; 1314 1315 pinctrl_pwm1_default: pwm1_default { 1316 function = "PWM1"; 1317 groups = "PWM1"; 1318 }; 1319 1320 pinctrl_pwm2_default: pwm2_default { 1321 function = "PWM2"; 1322 groups = "PWM2"; 1323 }; 1324 1325 pinctrl_pwm3_default: pwm3_default { 1326 function = "PWM3"; 1327 groups = "PWM3"; 1328 }; 1329 1330 pinctrl_pwm4_default: pwm4_default { 1331 function = "PWM4"; 1332 groups = "PWM4"; 1333 }; 1334 1335 pinctrl_pwm5_default: pwm5_default { 1336 function = "PWM5"; 1337 groups = "PWM5"; 1338 }; 1339 1340 pinctrl_pwm6_default: pwm6_default { 1341 function = "PWM6"; 1342 groups = "PWM6"; 1343 }; 1344 1345 pinctrl_pwm7_default: pwm7_default { 1346 function = "PWM7"; 1347 groups = "PWM7"; 1348 }; 1349 1350 pinctrl_rgmii1_default: rgmii1_default { 1351 function = "RGMII1"; 1352 groups = "RGMII1"; 1353 }; 1354 1355 pinctrl_rgmii2_default: rgmii2_default { 1356 function = "RGMII2"; 1357 groups = "RGMII2"; 1358 }; 1359 1360 pinctrl_rmii1_default: rmii1_default { 1361 function = "RMII1"; 1362 groups = "RMII1"; 1363 }; 1364 1365 pinctrl_rmii2_default: rmii2_default { 1366 function = "RMII2"; 1367 groups = "RMII2"; 1368 }; 1369 1370 pinctrl_rxd1_default: rxd1_default { 1371 function = "RXD1"; 1372 groups = "RXD1"; 1373 }; 1374 1375 pinctrl_rxd2_default: rxd2_default { 1376 function = "RXD2"; 1377 groups = "RXD2"; 1378 }; 1379 1380 pinctrl_rxd3_default: rxd3_default { 1381 function = "RXD3"; 1382 groups = "RXD3"; 1383 }; 1384 1385 pinctrl_rxd4_default: rxd4_default { 1386 function = "RXD4"; 1387 groups = "RXD4"; 1388 }; 1389 1390 pinctrl_salt1_default: salt1_default { 1391 function = "SALT1"; 1392 groups = "SALT1"; 1393 }; 1394 1395 pinctrl_salt10_default: salt10_default { 1396 function = "SALT10"; 1397 groups = "SALT10"; 1398 }; 1399 1400 pinctrl_salt11_default: salt11_default { 1401 function = "SALT11"; 1402 groups = "SALT11"; 1403 }; 1404 1405 pinctrl_salt12_default: salt12_default { 1406 function = "SALT12"; 1407 groups = "SALT12"; 1408 }; 1409 1410 pinctrl_salt13_default: salt13_default { 1411 function = "SALT13"; 1412 groups = "SALT13"; 1413 }; 1414 1415 pinctrl_salt14_default: salt14_default { 1416 function = "SALT14"; 1417 groups = "SALT14"; 1418 }; 1419 1420 pinctrl_salt2_default: salt2_default { 1421 function = "SALT2"; 1422 groups = "SALT2"; 1423 }; 1424 1425 pinctrl_salt3_default: salt3_default { 1426 function = "SALT3"; 1427 groups = "SALT3"; 1428 }; 1429 1430 pinctrl_salt4_default: salt4_default { 1431 function = "SALT4"; 1432 groups = "SALT4"; 1433 }; 1434 1435 pinctrl_salt5_default: salt5_default { 1436 function = "SALT5"; 1437 groups = "SALT5"; 1438 }; 1439 1440 pinctrl_salt6_default: salt6_default { 1441 function = "SALT6"; 1442 groups = "SALT6"; 1443 }; 1444 1445 pinctrl_salt7_default: salt7_default { 1446 function = "SALT7"; 1447 groups = "SALT7"; 1448 }; 1449 1450 pinctrl_salt8_default: salt8_default { 1451 function = "SALT8"; 1452 groups = "SALT8"; 1453 }; 1454 1455 pinctrl_salt9_default: salt9_default { 1456 function = "SALT9"; 1457 groups = "SALT9"; 1458 }; 1459 1460 pinctrl_scl1_default: scl1_default { 1461 function = "SCL1"; 1462 groups = "SCL1"; 1463 }; 1464 1465 pinctrl_scl2_default: scl2_default { 1466 function = "SCL2"; 1467 groups = "SCL2"; 1468 }; 1469 1470 pinctrl_sd1_default: sd1_default { 1471 function = "SD1"; 1472 groups = "SD1"; 1473 }; 1474 1475 pinctrl_sd2_default: sd2_default { 1476 function = "SD2"; 1477 groups = "SD2"; 1478 }; 1479 1480 pinctrl_emmc_default: emmc_default { 1481 function = "EMMC"; 1482 groups = "EMMC"; 1483 }; 1484 1485 pinctrl_sda1_default: sda1_default { 1486 function = "SDA1"; 1487 groups = "SDA1"; 1488 }; 1489 1490 pinctrl_sda2_default: sda2_default { 1491 function = "SDA2"; 1492 groups = "SDA2"; 1493 }; 1494 1495 pinctrl_sgps1_default: sgps1_default { 1496 function = "SGPS1"; 1497 groups = "SGPS1"; 1498 }; 1499 1500 pinctrl_sgps2_default: sgps2_default { 1501 function = "SGPS2"; 1502 groups = "SGPS2"; 1503 }; 1504 1505 pinctrl_sioonctrl_default: sioonctrl_default { 1506 function = "SIOONCTRL"; 1507 groups = "SIOONCTRL"; 1508 }; 1509 1510 pinctrl_siopbi_default: siopbi_default { 1511 function = "SIOPBI"; 1512 groups = "SIOPBI"; 1513 }; 1514 1515 pinctrl_siopbo_default: siopbo_default { 1516 function = "SIOPBO"; 1517 groups = "SIOPBO"; 1518 }; 1519 1520 pinctrl_siopwreq_default: siopwreq_default { 1521 function = "SIOPWREQ"; 1522 groups = "SIOPWREQ"; 1523 }; 1524 1525 pinctrl_siopwrgd_default: siopwrgd_default { 1526 function = "SIOPWRGD"; 1527 groups = "SIOPWRGD"; 1528 }; 1529 1530 pinctrl_sios3_default: sios3_default { 1531 function = "SIOS3"; 1532 groups = "SIOS3"; 1533 }; 1534 1535 pinctrl_sios5_default: sios5_default { 1536 function = "SIOS5"; 1537 groups = "SIOS5"; 1538 }; 1539 1540 pinctrl_siosci_default: siosci_default { 1541 function = "SIOSCI"; 1542 groups = "SIOSCI"; 1543 }; 1544 1545 pinctrl_spi1_default: spi1_default { 1546 function = "SPI1"; 1547 groups = "SPI1"; 1548 }; 1549 1550 pinctrl_spi1cs1_default: spi1cs1_default { 1551 function = "SPI1CS1"; 1552 groups = "SPI1CS1"; 1553 }; 1554 1555 pinctrl_spi1debug_default: spi1debug_default { 1556 function = "SPI1DEBUG"; 1557 groups = "SPI1DEBUG"; 1558 }; 1559 1560 pinctrl_spi1passthru_default: spi1passthru_default { 1561 function = "SPI1PASSTHRU"; 1562 groups = "SPI1PASSTHRU"; 1563 }; 1564 1565 pinctrl_spi2ck_default: spi2ck_default { 1566 function = "SPI2CK"; 1567 groups = "SPI2CK"; 1568 }; 1569 1570 pinctrl_spi2cs0_default: spi2cs0_default { 1571 function = "SPI2CS0"; 1572 groups = "SPI2CS0"; 1573 }; 1574 1575 pinctrl_spi2cs1_default: spi2cs1_default { 1576 function = "SPI2CS1"; 1577 groups = "SPI2CS1"; 1578 }; 1579 1580 pinctrl_spi2miso_default: spi2miso_default { 1581 function = "SPI2MISO"; 1582 groups = "SPI2MISO"; 1583 }; 1584 1585 pinctrl_spi2mosi_default: spi2mosi_default { 1586 function = "SPI2MOSI"; 1587 groups = "SPI2MOSI"; 1588 }; 1589 1590 pinctrl_timer3_default: timer3_default { 1591 function = "TIMER3"; 1592 groups = "TIMER3"; 1593 }; 1594 1595 pinctrl_timer4_default: timer4_default { 1596 function = "TIMER4"; 1597 groups = "TIMER4"; 1598 }; 1599 1600 pinctrl_timer5_default: timer5_default { 1601 function = "TIMER5"; 1602 groups = "TIMER5"; 1603 }; 1604 1605 pinctrl_timer6_default: timer6_default { 1606 function = "TIMER6"; 1607 groups = "TIMER6"; 1608 }; 1609 1610 pinctrl_timer7_default: timer7_default { 1611 function = "TIMER7"; 1612 groups = "TIMER7"; 1613 }; 1614 1615 pinctrl_timer8_default: timer8_default { 1616 function = "TIMER8"; 1617 groups = "TIMER8"; 1618 }; 1619 1620 pinctrl_txd1_default: txd1_default { 1621 function = "TXD1"; 1622 groups = "TXD1"; 1623 }; 1624 1625 pinctrl_txd2_default: txd2_default { 1626 function = "TXD2"; 1627 groups = "TXD2"; 1628 }; 1629 1630 pinctrl_txd3_default: txd3_default { 1631 function = "TXD3"; 1632 groups = "TXD3"; 1633 }; 1634 1635 pinctrl_txd4_default: txd4_default { 1636 function = "TXD4"; 1637 groups = "TXD4"; 1638 }; 1639 1640 pinctrl_uart6_default: uart6_default { 1641 function = "UART6"; 1642 groups = "UART6"; 1643 }; 1644 1645 pinctrl_usbcki_default: usbcki_default { 1646 function = "USBCKI"; 1647 groups = "USBCKI"; 1648 }; 1649 1650 pinctrl_usb2ah_default: usb2ah_default { 1651 function = "USB2AH"; 1652 groups = "USB2AH"; 1653 }; 1654 1655 pinctrl_usb11bhid_default: usb11bhid_default { 1656 function = "USB11BHID"; 1657 groups = "USB11BHID"; 1658 }; 1659 1660 pinctrl_usb2bh_default: usb2bh_default { 1661 function = "USB2BH"; 1662 groups = "USB2BH"; 1663 }; 1664 1665 pinctrl_vgabiosrom_default: vgabiosrom_default { 1666 function = "VGABIOSROM"; 1667 groups = "VGABIOSROM"; 1668 }; 1669 1670 pinctrl_vgahs_default: vgahs_default { 1671 function = "VGAHS"; 1672 groups = "VGAHS"; 1673 }; 1674 1675 pinctrl_vgavs_default: vgavs_default { 1676 function = "VGAVS"; 1677 groups = "VGAVS"; 1678 }; 1679 1680 pinctrl_vpi24_default: vpi24_default { 1681 function = "VPI24"; 1682 groups = "VPI24"; 1683 }; 1684 1685 pinctrl_vpo_default: vpo_default { 1686 function = "VPO"; 1687 groups = "VPO"; 1688 }; 1689 1690 pinctrl_wdtrst1_default: wdtrst1_default { 1691 function = "WDTRST1"; 1692 groups = "WDTRST1"; 1693 }; 1694 1695 pinctrl_wdtrst2_default: wdtrst2_default { 1696 function = "WDTRST2"; 1697 groups = "WDTRST2"; 1698 }; 1699}; 1700