1// SPDX-License-Identifier: GPL-2.0+ 2#include <dt-bindings/interrupt-controller/arm-gic.h> 3#include <dt-bindings/gpio/aspeed-gpio.h> 4#include "skeleton.dtsi" 5 6/ { 7 model = "Aspeed BMC"; 8 compatible = "aspeed,ast2600"; 9 #address-cells = <1>; 10 #size-cells = <1>; 11 interrupt-parent = <&gic>; 12 13 aliases { 14 i2c0 = &i2c0; 15 i2c1 = &i2c1; 16 i2c2 = &i2c2; 17 i2c3 = &i2c3; 18 i2c4 = &i2c4; 19 i2c5 = &i2c5; 20 i2c6 = &i2c6; 21 i2c7 = &i2c7; 22 i2c8 = &i2c8; 23 i2c9 = &i2c9; 24 i2c10 = &i2c10; 25 i2c11 = &i2c11; 26 i2c12 = &i2c12; 27 i2c13 = &i2c13; 28 i2c14 = &i2c14; 29 i2c15 = &i2c15; 30 serial0 = &uart1; 31 serial1 = &uart2; 32 serial2 = &uart3; 33 serial3 = &uart4; 34 serial4 = &uart5; 35 serial5 = &uart6; 36 serial6 = &uart7; 37 serial7 = &uart8; 38 serial8 = &uart9; 39 serial9 = &uart10; 40 serial10 = &uart11; 41 serial11 = &uart12; 42 serial12 = &uart13; 43 }; 44 45 cpus { 46 #address-cells = <1>; 47 #size-cells = <0>; 48 enable-method = "aspeed,ast2600-smp"; 49 50 cpu@0 { 51 compatible = "arm,cortex-a7"; 52 device_type = "cpu"; 53 reg = <0>; 54 }; 55 56 cpu@1 { 57 compatible = "arm,cortex-a7"; 58 device_type = "cpu"; 59 reg = <1>; 60 }; 61 62 }; 63 64 timer { 65 compatible = "arm,armv7-timer"; 66 interrupt-parent = <&gic>; 67 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 68 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 69 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 70 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 71 }; 72 73 reserved-memory { 74 #address-cells = <1>; 75 #size-cells = <1>; 76 ranges; 77 78 gfx_memory: framebuffer { 79 size = <0x01000000>; 80 alignment = <0x01000000>; 81 compatible = "shared-dma-pool"; 82 reusable; 83 }; 84 85 video_memory: video { 86 size = <0x04000000>; 87 alignment = <0x01000000>; 88 compatible = "shared-dma-pool"; 89 no-map; 90 }; 91 }; 92 93 ahb { 94 compatible = "simple-bus"; 95 #address-cells = <1>; 96 #size-cells = <1>; 97 device_type = "soc"; 98 ranges; 99 100 gic: interrupt-controller@40461000 { 101 compatible = "arm,cortex-a7-gic"; 102 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 103 #interrupt-cells = <3>; 104 interrupt-controller; 105 interrupt-parent = <&gic>; 106 reg = <0x40461000 0x1000>, 107 <0x40462000 0x1000>, 108 <0x40464000 0x2000>, 109 <0x40466000 0x2000>; 110 }; 111 112 ahbc: ahbc@1e600000 { 113 compatible = "aspeed,aspeed-ahbc"; 114 reg = < 0x1e600000 0x100>; 115 }; 116 117 fmc: flash-controller@1e620000 { 118 reg = <0x1e620000 0xc4 119 0x20000000 0x10000000>; 120 #address-cells = <1>; 121 #size-cells = <0>; 122 compatible = "aspeed,ast2600-fmc"; 123 status = "disabled"; 124 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 125 clocks = <&scu ASPEED_CLK_AHB>; 126 num-cs = <3>; 127 flash@0 { 128 reg = < 0 >; 129 compatible = "jedec,spi-nor"; 130 status = "disabled"; 131 }; 132 flash@1 { 133 reg = < 1 >; 134 compatible = "jedec,spi-nor"; 135 status = "disabled"; 136 }; 137 flash@2 { 138 reg = < 2 >; 139 compatible = "jedec,spi-nor"; 140 status = "disabled"; 141 }; 142 }; 143 144 spi1: flash-controller@1e630000 { 145 reg = <0x1e630000 0xc4 146 0x30000000 0x10000000>; 147 #address-cells = <1>; 148 #size-cells = <0>; 149 compatible = "aspeed,ast2600-spi"; 150 clocks = <&scu ASPEED_CLK_AHB>; 151 num-cs = <2>; 152 status = "disabled"; 153 flash@0 { 154 reg = < 0 >; 155 compatible = "jedec,spi-nor"; 156 status = "disabled"; 157 }; 158 flash@1 { 159 reg = < 1 >; 160 compatible = "jedec,spi-nor"; 161 status = "disabled"; 162 }; 163 }; 164 165 spi2: flash-controller@1e631000 { 166 reg = <0x1e631000 0xc4 167 0x50000000 0x10000000>; 168 #address-cells = <1>; 169 #size-cells = <0>; 170 compatible = "aspeed,ast2600-spi"; 171 clocks = <&scu ASPEED_CLK_AHB>; 172 num-cs = <3>; 173 status = "disabled"; 174 flash@0 { 175 reg = < 0 >; 176 compatible = "jedec,spi-nor"; 177 status = "disabled"; 178 }; 179 flash@1 { 180 reg = < 1 >; 181 compatible = "jedec,spi-nor"; 182 status = "disabled"; 183 }; 184 flash@2 { 185 reg = < 2 >; 186 compatible = "jedec,spi-nor"; 187 status = "disabled"; 188 }; 189 }; 190 191 edac: sdram@1e6e0000 { 192 compatible = "aspeed,ast2600-sdram-edac"; 193 reg = <0x1e6e0000 0x174>; 194 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 195 }; 196 197 mdio: ethernet@1e650000 { 198 compatible = "aspeed,aspeed-mdio"; 199 reg = <0x1e650000 0x40>; 200 resets = <&rst ASPEED_RESET_MII>; 201 status = "disabled"; 202 }; 203 204 mac0: ftgmac@1e660000 { 205 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 206 reg = <0x1e660000 0x180>, <0x1e650000 0x4>; 207 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 208 clocks = <&scu ASPEED_CLK_GATE_MAC1CLK>; 209 status = "disabled"; 210 }; 211 212 mac1: ftgmac@1e680000 { 213 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 214 reg = <0x1e680000 0x180>, <0x1e650008 0x4>; 215 #address-cells = <1>; 216 #size-cells = <0>; 217 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 218 clocks = <&scu ASPEED_CLK_GATE_MAC2CLK>; 219 status = "disabled"; 220 }; 221 222 mac2: ftgmac@1e670000 { 223 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 224 reg = <0x1e670000 0x180>, <0x1e650010 0x4>; 225 #address-cells = <1>; 226 #size-cells = <0>; 227 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 228 clocks = <&scu ASPEED_CLK_GATE_MAC3CLK>; 229 status = "disabled"; 230 }; 231 232 mac3: ftgmac@1e690000 { 233 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 234 reg = <0x1e690000 0x180>, <0x1e650018 0x4>; 235 #address-cells = <1>; 236 #size-cells = <0>; 237 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 238 clocks = <&scu ASPEED_CLK_GATE_MAC4CLK>; 239 status = "disabled"; 240 }; 241 242 vhub: usb-vhub@1e6a0000 { 243 compatible = "aspeed,ast2600-usb-vhub"; 244 reg = <0x1e6a0000 0x350>; 245 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 246 clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>; 247 resets = <&rst ASPEED_RESET_EHCI_P1>; 248 pinctrl-names = "default"; 249 pinctrl-0 = <&pinctrl_usb2ad_default>; 250 status = "disabled"; 251 }; 252 253 ehci0: usb@1e6a1000 { 254 compatible = "aspeed,aspeed-ehci", "usb-ehci"; 255 reg = <0x1e6a1000 0x100>; 256 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 257 clocks = <&scu ASPEED_CLK_GATE_USBPORT1CLK>; 258 pinctrl-names = "default"; 259 pinctrl-0 = <&pinctrl_usb2ah_default>; 260 status = "disabled"; 261 }; 262 263 ehci1: usb@1e6a3000 { 264 compatible = "aspeed,aspeed-ehci", "usb-ehci"; 265 reg = <0x1e6a3000 0x100>; 266 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 267 clocks = <&scu ASPEED_CLK_GATE_USBPORT2CLK>; 268 pinctrl-names = "default"; 269 pinctrl-0 = <&pinctrl_usb2bh_default>; 270 status = "disabled"; 271 }; 272 273 apb { 274 compatible = "simple-bus"; 275 #address-cells = <1>; 276 #size-cells = <1>; 277 ranges; 278 u-boot,dm-pre-reloc; 279 280 syscon: syscon@1e6e2000 { 281 compatible = "aspeed,g6-scu", "syscon", "simple-mfd"; 282 reg = <0x1e6e2000 0x1000>; 283 #address-cells = <1>; 284 #size-cells = <1>; 285 #clock-cells = <1>; 286 #reset-cells = <1>; 287 ranges = <0 0x1e6e2000 0x1000>; 288 u-boot,dm-pre-reloc; 289 290 pinctrl: pinctrl { 291 compatible = "aspeed,g6-pinctrl"; 292 aspeed,external-nodes = <&gfx &lhc>; 293 u-boot,dm-pre-reloc; 294 }; 295 296 vga_scratch: scratch { 297 compatible = "aspeed,bmc-misc"; 298 }; 299 300 scu_ic0: interrupt-controller@0 { 301 #interrupt-cells = <1>; 302 compatible = "aspeed,ast2600-scu-ic"; 303 reg = <0x560 0x10>; 304 interrupt-parent = <&gic>; 305 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 306 interrupt-controller; 307 }; 308 309 scu_ic1: interrupt-controller@1 { 310 #interrupt-cells = <1>; 311 compatible = "aspeed,ast2600-scu-ic"; 312 reg = <0x570 0x10>; 313 interrupt-parent = <&gic>; 314 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 315 interrupt-controller; 316 }; 317 318 }; 319 320 hace: hace@1e6d0000 { 321 compatible = "aspeed,ast2600-hace"; 322 reg = <0x1e6d0000 0x200>; 323 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 324 clocks = <&scu ASPEED_CLK_GATE_YCLK>; 325 clock-names = "yclk"; 326 status = "disabled"; 327 }; 328 329 acry: acry@1e6fa000 { 330 compatible = "aspeed,ast2600-acry"; 331 reg = <0x1e6fa000 0x1000>; 332 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 333 clocks = <&scu ASPEED_CLK_GATE_RSAECCCLK>; 334 clock-names = "rsaeccclk"; 335 status = "disabled"; 336 }; 337 338 smp-memram@0 { 339 compatible = "aspeed,ast2600-smpmem", "syscon"; 340 reg = <0x1e6e2180 0x40>; 341 }; 342 343 gfx: display@1e6e6000 { 344 compatible = "aspeed,ast2500-gfx", "syscon"; 345 reg = <0x1e6e6000 0x1000>; 346 reg-io-width = <4>; 347 }; 348 349 sdhci: sdhci@1e740000 { 350 #interrupt-cells = <1>; 351 compatible = "aspeed,aspeed-sdhci-irq", "simple-mfd"; 352 reg = <0x1e740000 0x1000>; 353 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 354 interrupt-controller; 355 clocks = <&scu ASPEED_CLK_GATE_SDCLK>, <&scu ASPEED_CLK_GATE_SDEXTCLK>; 356 clock-names = "ctrlclk", "extclk"; 357 #address-cells = <1>; 358 #size-cells = <1>; 359 ranges = <0x0 0x1e740000 0x1000>; 360 361 sdhci_slot0: sdhci_slot0@100 { 362 compatible = "aspeed,sdhci-ast2600"; 363 reg = <0x100 0x100>; 364 interrupts = <0>; 365 interrupt-parent = <&sdhci>; 366 sdhci,auto-cmd12; 367 clocks = <&scu ASPEED_CLK_SDIO>; 368 status = "disabled"; 369 }; 370 371 sdhci_slot1: sdhci_slot1@200 { 372 compatible = "aspeed,sdhci-ast2600"; 373 reg = <0x200 0x100>; 374 interrupts = <1>; 375 interrupt-parent = <&sdhci>; 376 sdhci,auto-cmd12; 377 clocks = <&scu ASPEED_CLK_SDIO>; 378 status = "disabled"; 379 }; 380 }; 381 382 emmc: emmc@1e750000 { 383 #interrupt-cells = <1>; 384 compatible = "aspeed,aspeed-emmc-irq", "simple-mfd"; 385 reg = <0x1e750000 0x1000>; 386 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 387 interrupt-controller; 388 clocks = <&scu ASPEED_CLK_GATE_EMMCCLK>, <&scu ASPEED_CLK_GATE_EMMCEXTCLK>; 389 clock-names = "ctrlclk", "extclk"; 390 #address-cells = <1>; 391 #size-cells = <1>; 392 ranges = <0x0 0x1e750000 0x1000>; 393 394 emmc_slot0: emmc_slot0@100 { 395 compatible = "aspeed,emmc-ast2600"; 396 reg = <0x100 0x100>; 397 interrupts = <0>; 398 interrupt-parent = <&emmc>; 399 clocks = <&scu ASPEED_CLK_EMMC>; 400 status = "disabled"; 401 }; 402 }; 403 404 pcie_rc_bridge0: pcie@1e6ed000 { 405 compatible = "aspeed,ast2600-rc_bridge"; 406 reg = <0x1e6ed000 0x100>; 407 resets = <&rst ASPEED_RESET_PCIE_DEV_O>; 408 pinctrl-names = "default"; 409 pinctrl-0 = <&pinctrl_pcie0rc_default>; 410 status = "disabled"; 411 }; 412 413 pcie_rc_bridge1: pcie@1e6ed200 { 414 compatible = "aspeed,ast2600-rc_bridge"; 415 reg = <0x1e6ed200 0x100>; 416 resets = <&rst ASPEED_RESET_PCIE_RC_O>; 417 pinctrl-names = "default"; 418 pinctrl-0 = <&pinctrl_pcie1rc_default>; 419 status = "disabled"; 420 }; 421 422 pcie_bridge: pcie@1e770000 { 423 compatible = "aspeed,ast2600-pcie"; 424 #address-cells = <3>; 425 #size-cells = <2>; 426 reg = <0x1e770000 0x100>; 427 ranges = <0x81000000 0x0 0x0 0x0 0x0 0x10000 /* downstream I/O */ 428 0x82000000 0x0 0x60000000 0x60000000 0x0 0x20000000>; /* non-prefetchable memory */ 429 device_type = "pci"; 430 bus-range = <0x00 0xff>; 431 resets = <&rst ASPEED_RESET_H2X>; 432 slot0-handle = <&pcie_rc_bridge0>; 433 slot1-handle = <&pcie_rc_bridge1>; 434 status = "disabled"; 435 }; 436 437 gpio0: gpio@1e780000 { 438 compatible = "aspeed,ast2600-gpio"; 439 reg = <0x1e780000 0x400>; 440 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 441 #gpio-cells = <2>; 442 gpio-controller; 443 interrupt-controller; 444 gpio-ranges = <&pinctrl 0 0 208>; 445 ngpios = <208>; 446 }; 447 448 gpio1: gpio@1e780800 { 449 compatible = "aspeed,ast2600-gpio"; 450 reg = <0x1e780800 0x800>; 451 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 452 #gpio-cells = <2>; 453 gpio-controller; 454 interrupt-controller; 455 gpio-ranges = <&pinctrl 0 208 36>; 456 ngpios = <36>; 457 }; 458 459 uart1: serial@1e783000 { 460 compatible = "ns16550a"; 461 reg = <0x1e783000 0x20>; 462 reg-shift = <2>; 463 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 464 clocks = <&scu ASPEED_CLK_GATE_UART1CLK>; 465 clock-frequency = <1846154>; 466 no-loopback-test; 467 u-boot,dm-pre-reloc; 468 pinctrl-names = "default"; 469 pinctrl-0 = <&pinctrl_txd1_default &pinctrl_rxd1_default>; 470 status = "disabled"; 471 }; 472 473 uart5: serial@1e784000 { 474 compatible = "ns16550a"; 475 reg = <0x1e784000 0x1000>; 476 reg-shift = <2>; 477 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 478 clocks = <&scu ASPEED_CLK_GATE_UART5CLK>; 479 clock-frequency = <1846154>; 480 no-loopback-test; 481 u-boot,dm-pre-reloc; 482 status = "disabled"; 483 }; 484 485 wdt1: watchdog@1e785000 { 486 compatible = "aspeed,ast2600-wdt"; 487 reg = <0x1e785000 0x40>; 488 }; 489 490 wdt2: watchdog@1e785040 { 491 compatible = "aspeed,ast2600-wdt"; 492 reg = <0x1e785040 0x40>; 493 }; 494 495 wdt3: watchdog@1e785080 { 496 compatible = "aspeed,ast2600-wdt"; 497 reg = <0x1e785080 0x40>; 498 }; 499 500 wdt4: watchdog@1e7850C0 { 501 compatible = "aspeed,ast2600-wdt"; 502 reg = <0x1e7850C0 0x40>; 503 }; 504 505 lpc: lpc@1e789000 { 506 compatible = "aspeed,ast-lpc", "simple-mfd", "syscon"; 507 reg = <0x1e789000 0x200>; 508 509 #address-cells = <1>; 510 #size-cells = <1>; 511 ranges = <0x0 0x1e789000 0x1000>; 512 513 lpc_bmc: lpc-bmc@0 { 514 compatible = "aspeed,ast2600-lpc-bmc", "simple-mfd", "syscon"; 515 reg = <0x0 0x80>; 516 reg-io-width = <4>; 517 #address-cells = <1>; 518 #size-cells = <1>; 519 ranges = <0x0 0x0 0x80>; 520 521 kcs1: kcs1@0 { 522 compatible = "aspeed,ast2600-kcs-bmc"; 523 reg = <0x0 0x80>; 524 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 525 kcs_chan = <1>; 526 kcs_addr = <0xCA0>; 527 status = "disabled"; 528 }; 529 530 kcs2: kcs2@0 { 531 compatible = "aspeed,ast2600-kcs-bmc"; 532 reg = <0x0 0x80>; 533 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 534 kcs_chan = <2>; 535 kcs_addr = <0xCA8>; 536 status = "disabled"; 537 }; 538 539 kcs3: kcs3@0 { 540 compatible = "aspeed,ast2600-kcs-bmc"; 541 reg = <0x0 0x80>; 542 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 543 kcs_chan = <3>; 544 kcs_addr = <0xCA2>; 545 }; 546 547 kcs4: kcs4@0 { 548 compatible = "aspeed,ast2600-kcs-bmc"; 549 reg = <0x0 0x120>; 550 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 551 kcs_chan = <4>; 552 kcs_addr = <0xCA4>; 553 status = "disabled"; 554 }; 555 556 }; 557 558 lpc_host: lpc-host@80 { 559 compatible = "aspeed,ast2600-lpc-host", "simple-mfd", "syscon"; 560 reg = <0x80 0x1e0>; 561 reg-io-width = <4>; 562 563 #address-cells = <1>; 564 #size-cells = <1>; 565 ranges = <0x0 0x80 0x1e0>; 566 567 lpc_ctrl: lpc-ctrl@0 { 568 compatible = "aspeed,ast2600-lpc-ctrl"; 569 reg = <0x0 0x80>; 570 status = "disabled"; 571 }; 572 573 lpc_snoop: lpc-snoop@0 { 574 compatible = "aspeed,ast2600-lpc-snoop"; 575 reg = <0x0 0x80>; 576 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 577 snoop-ports = <0x80>; 578 status = "disabled"; 579 }; 580 581 lhc: lhc@20 { 582 compatible = "aspeed,ast2600-lhc"; 583 reg = <0x20 0x24 0x48 0x8>; 584 }; 585 586 lpc_reset: reset-controller@18 { 587 compatible = "aspeed,ast2600-lpc-reset"; 588 reg = <0x18 0x4>; 589 #reset-cells = <1>; 590 status = "disabled"; 591 }; 592 593 ibt: ibt@c0 { 594 compatible = "aspeed,ast2600-ibt-bmc"; 595 reg = <0xc0 0x18>; 596 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 597 status = "disabled"; 598 }; 599 600 sio_regs: regs { 601 compatible = "aspeed,bmc-misc"; 602 }; 603 604 mbox: mbox@180 { 605 compatible = "aspeed,ast2600-mbox"; 606 reg = <0x180 0x5c>; 607 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 608 #mbox-cells = <1>; 609 status = "disabled"; 610 }; 611 }; 612 }; 613 614 uart2: serial@1e78d000 { 615 compatible = "ns16550a"; 616 reg = <0x1e78d000 0x20>; 617 reg-shift = <2>; 618 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 619 clocks = <&scu ASPEED_CLK_GATE_UART2CLK>; 620 clock-frequency = <1846154>; 621 no-loopback-test; 622 pinctrl-names = "default"; 623 pinctrl-0 = <&pinctrl_txd2_default &pinctrl_rxd2_default>; 624 u-boot,dm-pre-reloc; 625 status = "disabled"; 626 }; 627 628 uart3: serial@1e78e000 { 629 compatible = "ns16550a"; 630 reg = <0x1e78e000 0x20>; 631 reg-shift = <2>; 632 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 633 clocks = <&scu ASPEED_CLK_GATE_UART3CLK>; 634 clock-frequency = <1846154>; 635 no-loopback-test; 636 pinctrl-names = "default"; 637 pinctrl-0 = <&pinctrl_txd3_default &pinctrl_rxd3_default>; 638 u-boot,dm-pre-reloc; 639 status = "disabled"; 640 }; 641 642 uart4: serial@1e78f000 { 643 compatible = "ns16550a"; 644 reg = <0x1e78f000 0x20>; 645 reg-shift = <2>; 646 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 647 clocks = <&scu ASPEED_CLK_GATE_UART4CLK>; 648 clock-frequency = <1846154>; 649 no-loopback-test; 650 u-boot,dm-pre-reloc; 651 pinctrl-names = "default"; 652 pinctrl-0 = <&pinctrl_txd4_default &pinctrl_rxd4_default>; 653 status = "disabled"; 654 }; 655 656 i2c: bus@1e78a000 { 657 compatible = "simple-bus"; 658 #address-cells = <1>; 659 #size-cells = <1>; 660 ranges = <0 0x1e78a000 0x1000>; 661 }; 662 663 fsim0: fsi@1e79b000 { 664 compatible = "aspeed,ast2600-fsi-master", "fsi-master"; 665 reg = <0x1e79b000 0x94>; 666 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 667 pinctrl-names = "default"; 668 pinctrl-0 = <&pinctrl_fsi1_default>; 669 clocks = <&scu ASPEED_CLK_GATE_FSICLK>; 670 status = "disabled"; 671 }; 672 673 fsim1: fsi@1e79b100 { 674 compatible = "aspeed,ast2600-fsi-master", "fsi-master"; 675 reg = <0x1e79b100 0x94>; 676 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 677 pinctrl-names = "default"; 678 pinctrl-0 = <&pinctrl_fsi2_default>; 679 clocks = <&scu ASPEED_CLK_GATE_FSICLK>; 680 status = "disabled"; 681 }; 682 683 uart6: serial@1e790000 { 684 compatible = "ns16550a"; 685 reg = <0x1e790000 0x20>; 686 reg-shift = <2>; 687 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 688 clocks = <&scu ASPEED_CLK_GATE_UART6CLK>; 689 clock-frequency = <1846154>; 690 no-loopback-test; 691 status = "disabled"; 692 }; 693 694 uart7: serial@1e790100 { 695 compatible = "ns16550a"; 696 reg = <0x1e790100 0x20>; 697 reg-shift = <2>; 698 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 699 clocks = <&scu ASPEED_CLK_GATE_UART7CLK>; 700 clock-frequency = <1846154>; 701 no-loopback-test; 702 status = "disabled"; 703 }; 704 705 uart8: serial@1e790200 { 706 compatible = "ns16550a"; 707 reg = <0x1e790200 0x20>; 708 reg-shift = <2>; 709 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 710 clocks = <&scu ASPEED_CLK_GATE_UART8CLK>; 711 clock-frequency = <1846154>; 712 no-loopback-test; 713 status = "disabled"; 714 }; 715 716 uart9: serial@1e790300 { 717 compatible = "ns16550a"; 718 reg = <0x1e790300 0x20>; 719 reg-shift = <2>; 720 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 721 clocks = <&scu ASPEED_CLK_GATE_UART9CLK>; 722 clock-frequency = <1846154>; 723 no-loopback-test; 724 status = "disabled"; 725 }; 726 727 uart10: serial@1e790400 { 728 compatible = "ns16550a"; 729 reg = <0x1e790400 0x20>; 730 reg-shift = <2>; 731 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 732 clocks = <&scu ASPEED_CLK_GATE_UART10CLK>; 733 clock-frequency = <1846154>; 734 no-loopback-test; 735 status = "disabled"; 736 }; 737 738 uart11: serial@1e790500 { 739 compatible = "ns16550a"; 740 reg = <0x1e790400 0x20>; 741 reg-shift = <2>; 742 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 743 clocks = <&scu ASPEED_CLK_GATE_UART11CLK>; 744 clock-frequency = <1846154>; 745 no-loopback-test; 746 status = "disabled"; 747 }; 748 749 uart12: serial@1e790600 { 750 compatible = "ns16550a"; 751 reg = <0x1e790600 0x20>; 752 reg-shift = <2>; 753 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 754 clocks = <&scu ASPEED_CLK_GATE_UART12CLK>; 755 clock-frequency = <1846154>; 756 no-loopback-test; 757 status = "disabled"; 758 }; 759 760 uart13: serial@1e790700 { 761 compatible = "ns16550a"; 762 reg = <0x1e790700 0x20>; 763 reg-shift = <2>; 764 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 765 clocks = <&scu ASPEED_CLK_GATE_UART13CLK>; 766 clock-frequency = <1846154>; 767 no-loopback-test; 768 status = "disabled"; 769 }; 770 771 display_port: dp@1e6eb000 { 772 compatible = "aspeed,ast2600-displayport"; 773 reg = <0x1e6eb000 0x200>; 774 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 775 resets = <&rst ASPEED_RESET_DP> ,<&rst ASPEED_RESET_DP_MCU>; 776 status = "disabled"; 777 }; 778 779 }; 780 781 }; 782 783}; 784 785&i2c { 786 i2cglobal: i2cg@00 { 787 compatible = "aspeed,ast2600-i2c-global"; 788 reg = <0x0 0x40>; 789 resets = <&rst ASPEED_RESET_I2C>; 790#if 0 791 new-mode; 792#endif 793 }; 794 795 i2c0: i2c@80 { 796 #address-cells = <1>; 797 #size-cells = <0>; 798 #interrupt-cells = <1>; 799 800 reg = <0x80 0x80 0xC00 0x20>; 801 compatible = "aspeed,ast2600-i2c-bus"; 802 bus-frequency = <100000>; 803 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 804 clocks = <&scu ASPEED_CLK_APB2>; 805 status = "disabled"; 806 }; 807 808 i2c1: i2c@100 { 809 #address-cells = <1>; 810 #size-cells = <0>; 811 #interrupt-cells = <1>; 812 813 reg = <0x100 0x80 0xC20 0x20>; 814 compatible = "aspeed,ast2600-i2c-bus"; 815 bus-frequency = <100000>; 816 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 817 clocks = <&scu ASPEED_CLK_APB2>; 818 status = "disabled"; 819 }; 820 821 i2c2: i2c@180 { 822 #address-cells = <1>; 823 #size-cells = <0>; 824 #interrupt-cells = <1>; 825 826 reg = <0x180 0x80 0xC40 0x20>; 827 compatible = "aspeed,ast2600-i2c-bus"; 828 bus-frequency = <100000>; 829 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 830 clocks = <&scu ASPEED_CLK_APB2>; 831 }; 832 833 i2c3: i2c@200 { 834 #address-cells = <1>; 835 #size-cells = <0>; 836 #interrupt-cells = <1>; 837 838 reg = <0x200 0x40 0xC60 0x20>; 839 compatible = "aspeed,ast2600-i2c-bus"; 840 bus-frequency = <100000>; 841 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 842 clocks = <&scu ASPEED_CLK_APB2>; 843 }; 844 845 i2c4: i2c@280 { 846 #address-cells = <1>; 847 #size-cells = <0>; 848 #interrupt-cells = <1>; 849 850 reg = <0x280 0x80 0xC80 0x20>; 851 compatible = "aspeed,ast2600-i2c-bus"; 852 bus-frequency = <100000>; 853 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 854 clocks = <&scu ASPEED_CLK_APB2>; 855 }; 856 857 i2c5: i2c@300 { 858 #address-cells = <1>; 859 #size-cells = <0>; 860 #interrupt-cells = <1>; 861 862 reg = <0x300 0x40 0xCA0 0x20>; 863 compatible = "aspeed,ast2600-i2c-bus"; 864 bus-frequency = <100000>; 865 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 866 clocks = <&scu ASPEED_CLK_APB2>; 867 }; 868 869 i2c6: i2c@380 { 870 #address-cells = <1>; 871 #size-cells = <0>; 872 #interrupt-cells = <1>; 873 874 reg = <0x380 0x80 0xCC0 0x20>; 875 compatible = "aspeed,ast2600-i2c-bus"; 876 bus-frequency = <100000>; 877 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 878 clocks = <&scu ASPEED_CLK_APB2>; 879 }; 880 881 i2c7: i2c@400 { 882 #address-cells = <1>; 883 #size-cells = <0>; 884 #interrupt-cells = <1>; 885 886 reg = <0x400 0x80 0xCE0 0x20>; 887 compatible = "aspeed,ast2600-i2c-bus"; 888 bus-frequency = <100000>; 889 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 890 clocks = <&scu ASPEED_CLK_APB2>; 891 }; 892 893 i2c8: i2c@480 { 894 #address-cells = <1>; 895 #size-cells = <0>; 896 #interrupt-cells = <1>; 897 898 reg = <0x480 0x80 0xD00 0x20>; 899 compatible = "aspeed,ast2600-i2c-bus"; 900 bus-frequency = <100000>; 901 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 902 clocks = <&scu ASPEED_CLK_APB2>; 903 }; 904 905 i2c9: i2c@500 { 906 #address-cells = <1>; 907 #size-cells = <0>; 908 #interrupt-cells = <1>; 909 910 reg = <0x500 0x80 0xD20 0x20>; 911 compatible = "aspeed,ast2600-i2c-bus"; 912 bus-frequency = <100000>; 913 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 914 clocks = <&scu ASPEED_CLK_APB2>; 915 status = "disabled"; 916 }; 917 918 i2c10: i2c@580 { 919 #address-cells = <1>; 920 #size-cells = <0>; 921 #interrupt-cells = <1>; 922 923 reg = <0x580 0x80 0xD40 0x20>; 924 compatible = "aspeed,ast2600-i2c-bus"; 925 bus-frequency = <100000>; 926 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 927 clocks = <&scu ASPEED_CLK_APB2>; 928 status = "disabled"; 929 }; 930 931 i2c11: i2c@600 { 932 #address-cells = <1>; 933 #size-cells = <0>; 934 #interrupt-cells = <1>; 935 936 reg = <0x600 0x80 0xD60 0x20>; 937 compatible = "aspeed,ast2600-i2c-bus"; 938 bus-frequency = <100000>; 939 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 940 clocks = <&scu ASPEED_CLK_APB2>; 941 status = "disabled"; 942 }; 943 944 i2c12: i2c@680 { 945 #address-cells = <1>; 946 #size-cells = <0>; 947 #interrupt-cells = <1>; 948 949 reg = <0x680 0x80 0xD80 0x20>; 950 compatible = "aspeed,ast2600-i2c-bus"; 951 bus-frequency = <100000>; 952 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 953 clocks = <&scu ASPEED_CLK_APB2>; 954 status = "disabled"; 955 }; 956 957 i2c13: i2c@700 { 958 #address-cells = <1>; 959 #size-cells = <0>; 960 #interrupt-cells = <1>; 961 962 reg = <0x700 0x80 0xDA0 0x20>; 963 compatible = "aspeed,ast2600-i2c-bus"; 964 bus-frequency = <100000>; 965 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 966 clocks = <&scu ASPEED_CLK_APB2>; 967 status = "disabled"; 968 }; 969 970 i2c14: i2c@780 { 971 #address-cells = <1>; 972 #size-cells = <0>; 973 #interrupt-cells = <1>; 974 975 reg = <0x780 0x80 0xDC0 0x20>; 976 compatible = "aspeed,ast2600-i2c-bus"; 977 bus-frequency = <100000>; 978 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 979 clocks = <&scu ASPEED_CLK_APB2>; 980 status = "disabled"; 981 }; 982 983 i2c15: i2c@800 { 984 #address-cells = <1>; 985 #size-cells = <0>; 986 #interrupt-cells = <1>; 987 988 reg = <0x800 0x80 0xDE0 0x20>; 989 compatible = "aspeed,ast2600-i2c-bus"; 990 bus-frequency = <100000>; 991 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 992 clocks = <&scu ASPEED_CLK_APB2>; 993 status = "disabled"; 994 }; 995 996}; 997 998&pinctrl { 999 u-boot,dm-pre-reloc; 1000 1001 pinctrl_fmcquad_default: fmcquad_default { 1002 function = "FMCQUAD"; 1003 groups = "FMCQUAD"; 1004 }; 1005 1006 pinctrl_spi1_default: spi1_default { 1007 function = "SPI1"; 1008 groups = "SPI1"; 1009 }; 1010 1011 pinctrl_spi1abr_default: spi1abr_default { 1012 function = "SPI1ABR"; 1013 groups = "SPI1ABR"; 1014 }; 1015 1016 pinctrl_spi1cs1_default: spi1cs1_default { 1017 function = "SPI1CS1"; 1018 groups = "SPI1CS1"; 1019 }; 1020 1021 pinctrl_spi1wp_default: spi1wp_default { 1022 function = "SPI1WP"; 1023 groups = "SPI1WP"; 1024 }; 1025 1026 pinctrl_spi1quad_default: spi1quad_default { 1027 function = "SPI1QUAD"; 1028 groups = "SPI1QUAD"; 1029 }; 1030 1031 pinctrl_spi2_default: spi2_default { 1032 function = "SPI2"; 1033 groups = "SPI2"; 1034 }; 1035 1036 pinctrl_spi2cs1_default: spi2cs1_default { 1037 function = "SPI2CS1"; 1038 groups = "SPI2CS1"; 1039 }; 1040 1041 pinctrl_spi2cs2_default: spi2cs2_default { 1042 function = "SPI2CS2"; 1043 groups = "SPI2CS2"; 1044 }; 1045 1046 pinctrl_spi2quad_default: spi2quad_default { 1047 function = "SPI2QUAD"; 1048 groups = "SPI2QUAD"; 1049 }; 1050 1051 pinctrl_acpi_default: acpi_default { 1052 function = "ACPI"; 1053 groups = "ACPI"; 1054 }; 1055 1056 pinctrl_adc0_default: adc0_default { 1057 function = "ADC0"; 1058 groups = "ADC0"; 1059 }; 1060 1061 pinctrl_adc1_default: adc1_default { 1062 function = "ADC1"; 1063 groups = "ADC1"; 1064 }; 1065 1066 pinctrl_adc10_default: adc10_default { 1067 function = "ADC10"; 1068 groups = "ADC10"; 1069 }; 1070 1071 pinctrl_adc11_default: adc11_default { 1072 function = "ADC11"; 1073 groups = "ADC11"; 1074 }; 1075 1076 pinctrl_adc12_default: adc12_default { 1077 function = "ADC12"; 1078 groups = "ADC12"; 1079 }; 1080 1081 pinctrl_adc13_default: adc13_default { 1082 function = "ADC13"; 1083 groups = "ADC13"; 1084 }; 1085 1086 pinctrl_adc14_default: adc14_default { 1087 function = "ADC14"; 1088 groups = "ADC14"; 1089 }; 1090 1091 pinctrl_adc15_default: adc15_default { 1092 function = "ADC15"; 1093 groups = "ADC15"; 1094 }; 1095 1096 pinctrl_adc2_default: adc2_default { 1097 function = "ADC2"; 1098 groups = "ADC2"; 1099 }; 1100 1101 pinctrl_adc3_default: adc3_default { 1102 function = "ADC3"; 1103 groups = "ADC3"; 1104 }; 1105 1106 pinctrl_adc4_default: adc4_default { 1107 function = "ADC4"; 1108 groups = "ADC4"; 1109 }; 1110 1111 pinctrl_adc5_default: adc5_default { 1112 function = "ADC5"; 1113 groups = "ADC5"; 1114 }; 1115 1116 pinctrl_adc6_default: adc6_default { 1117 function = "ADC6"; 1118 groups = "ADC6"; 1119 }; 1120 1121 pinctrl_adc7_default: adc7_default { 1122 function = "ADC7"; 1123 groups = "ADC7"; 1124 }; 1125 1126 pinctrl_adc8_default: adc8_default { 1127 function = "ADC8"; 1128 groups = "ADC8"; 1129 }; 1130 1131 pinctrl_adc9_default: adc9_default { 1132 function = "ADC9"; 1133 groups = "ADC9"; 1134 }; 1135 1136 pinctrl_bmcint_default: bmcint_default { 1137 function = "BMCINT"; 1138 groups = "BMCINT"; 1139 }; 1140 1141 pinctrl_ddcclk_default: ddcclk_default { 1142 function = "DDCCLK"; 1143 groups = "DDCCLK"; 1144 }; 1145 1146 pinctrl_ddcdat_default: ddcdat_default { 1147 function = "DDCDAT"; 1148 groups = "DDCDAT"; 1149 }; 1150 1151 pinctrl_espi_default: espi_default { 1152 function = "ESPI"; 1153 groups = "ESPI"; 1154 }; 1155 1156 pinctrl_fsi1_default: fsi1_default { 1157 function = "FSI1"; 1158 groups = "FSI1"; 1159 }; 1160 1161 pinctrl_fsi2_default: fsi2_default { 1162 function = "FSI2"; 1163 groups = "FSI2"; 1164 }; 1165 1166 pinctrl_fwspics1_default: fwspics1_default { 1167 function = "FWSPICS1"; 1168 groups = "FWSPICS1"; 1169 }; 1170 1171 pinctrl_fwspics2_default: fwspics2_default { 1172 function = "FWSPICS2"; 1173 groups = "FWSPICS2"; 1174 }; 1175 1176 pinctrl_gpid0_default: gpid0_default { 1177 function = "GPID0"; 1178 groups = "GPID0"; 1179 }; 1180 1181 pinctrl_gpid2_default: gpid2_default { 1182 function = "GPID2"; 1183 groups = "GPID2"; 1184 }; 1185 1186 pinctrl_gpid4_default: gpid4_default { 1187 function = "GPID4"; 1188 groups = "GPID4"; 1189 }; 1190 1191 pinctrl_gpid6_default: gpid6_default { 1192 function = "GPID6"; 1193 groups = "GPID6"; 1194 }; 1195 1196 pinctrl_gpie0_default: gpie0_default { 1197 function = "GPIE0"; 1198 groups = "GPIE0"; 1199 }; 1200 1201 pinctrl_gpie2_default: gpie2_default { 1202 function = "GPIE2"; 1203 groups = "GPIE2"; 1204 }; 1205 1206 pinctrl_gpie4_default: gpie4_default { 1207 function = "GPIE4"; 1208 groups = "GPIE4"; 1209 }; 1210 1211 pinctrl_gpie6_default: gpie6_default { 1212 function = "GPIE6"; 1213 groups = "GPIE6"; 1214 }; 1215 1216 pinctrl_i2c1_default: i2c1_default { 1217 function = "I2C1"; 1218 groups = "I2C1"; 1219 }; 1220 pinctrl_i2c2_default: i2c2_default { 1221 function = "I2C2"; 1222 groups = "I2C2"; 1223 }; 1224 1225 pinctrl_i2c3_default: i2c3_default { 1226 function = "I2C3"; 1227 groups = "I2C3"; 1228 }; 1229 1230 pinctrl_i2c4_default: i2c4_default { 1231 function = "I2C4"; 1232 groups = "I2C4"; 1233 }; 1234 1235 pinctrl_i2c5_default: i2c5_default { 1236 function = "I2C5"; 1237 groups = "I2C5"; 1238 }; 1239 1240 pinctrl_i2c6_default: i2c6_default { 1241 function = "I2C6"; 1242 groups = "I2C6"; 1243 }; 1244 1245 pinctrl_i2c7_default: i2c7_default { 1246 function = "I2C7"; 1247 groups = "I2C7"; 1248 }; 1249 1250 pinctrl_i2c8_default: i2c8_default { 1251 function = "I2C8"; 1252 groups = "I2C8"; 1253 }; 1254 1255 pinctrl_i2c9_default: i2c9_default { 1256 function = "I2C9"; 1257 groups = "I2C9"; 1258 }; 1259 1260 pinctrl_i2c10_default: i2c10_default { 1261 function = "I2C10"; 1262 groups = "I2C10"; 1263 }; 1264 1265 pinctrl_i2c11_default: i2c11_default { 1266 function = "I2C11"; 1267 groups = "I2C11"; 1268 }; 1269 1270 pinctrl_i2c12_default: i2c12_default { 1271 function = "I2C12"; 1272 groups = "I2C12"; 1273 }; 1274 1275 pinctrl_i2c13_default: i2c13_default { 1276 function = "I2C13"; 1277 groups = "I2C13"; 1278 }; 1279 1280 pinctrl_i2c14_default: i2c14_default { 1281 function = "I2C14"; 1282 groups = "I2C14"; 1283 }; 1284 1285 pinctrl_i2c15_default: i2c15_default { 1286 function = "I2C15"; 1287 groups = "I2C15"; 1288 }; 1289 1290 pinctrl_i2c16_default: i2c16_default { 1291 function = "I2C16"; 1292 groups = "I2C16"; 1293 }; 1294 1295 pinctrl_lad0_default: lad0_default { 1296 function = "LAD0"; 1297 groups = "LAD0"; 1298 }; 1299 1300 pinctrl_lad1_default: lad1_default { 1301 function = "LAD1"; 1302 groups = "LAD1"; 1303 }; 1304 1305 pinctrl_lad2_default: lad2_default { 1306 function = "LAD2"; 1307 groups = "LAD2"; 1308 }; 1309 1310 pinctrl_lad3_default: lad3_default { 1311 function = "LAD3"; 1312 groups = "LAD3"; 1313 }; 1314 1315 pinctrl_lclk_default: lclk_default { 1316 function = "LCLK"; 1317 groups = "LCLK"; 1318 }; 1319 1320 pinctrl_lframe_default: lframe_default { 1321 function = "LFRAME"; 1322 groups = "LFRAME"; 1323 }; 1324 1325 pinctrl_lpchc_default: lpchc_default { 1326 function = "LPCHC"; 1327 groups = "LPCHC"; 1328 }; 1329 1330 pinctrl_lpcpd_default: lpcpd_default { 1331 function = "LPCPD"; 1332 groups = "LPCPD"; 1333 }; 1334 1335 pinctrl_lpcplus_default: lpcplus_default { 1336 function = "LPCPLUS"; 1337 groups = "LPCPLUS"; 1338 }; 1339 1340 pinctrl_lpcpme_default: lpcpme_default { 1341 function = "LPCPME"; 1342 groups = "LPCPME"; 1343 }; 1344 1345 pinctrl_lpcrst_default: lpcrst_default { 1346 function = "LPCRST"; 1347 groups = "LPCRST"; 1348 }; 1349 1350 pinctrl_lpcsmi_default: lpcsmi_default { 1351 function = "LPCSMI"; 1352 groups = "LPCSMI"; 1353 }; 1354 1355 pinctrl_lsirq_default: lsirq_default { 1356 function = "LSIRQ"; 1357 groups = "LSIRQ"; 1358 }; 1359 1360 pinctrl_mac1link_default: mac1link_default { 1361 function = "MAC1LINK"; 1362 groups = "MAC1LINK"; 1363 }; 1364 1365 pinctrl_mac2link_default: mac2link_default { 1366 function = "MAC2LINK"; 1367 groups = "MAC2LINK"; 1368 }; 1369 1370 pinctrl_mac3link_default: mac3link_default { 1371 function = "MAC3LINK"; 1372 groups = "MAC3LINK"; 1373 }; 1374 1375 pinctrl_mac4link_default: mac4link_default { 1376 function = "MAC4LINK"; 1377 groups = "MAC4LINK"; 1378 }; 1379 1380 pinctrl_mdio1_default: mdio1_default { 1381 function = "MDIO1"; 1382 groups = "MDIO1"; 1383 }; 1384 1385 pinctrl_mdio2_default: mdio2_default { 1386 function = "MDIO2"; 1387 groups = "MDIO2"; 1388 }; 1389 1390 pinctrl_mdio3_default: mdio3_default { 1391 function = "MDIO3"; 1392 groups = "MDIO3"; 1393 }; 1394 1395 pinctrl_mdio4_default: mdio4_default { 1396 function = "MDIO4"; 1397 groups = "MDIO4"; 1398 }; 1399 1400 pinctrl_rmii1_default: rmii1_default { 1401 function = "RMII1"; 1402 groups = "RMII1"; 1403 }; 1404 1405 pinctrl_rmii2_default: rmii2_default { 1406 function = "RMII2"; 1407 groups = "RMII2"; 1408 }; 1409 1410 pinctrl_rmii3_default: rmii3_default { 1411 function = "RMII3"; 1412 groups = "RMII3"; 1413 }; 1414 1415 pinctrl_rmii4_default: rmii4_default { 1416 function = "RMII4"; 1417 groups = "RMII4"; 1418 }; 1419 1420 pinctrl_rmii1rclk_default: rmii1rclk_default { 1421 function = "RMII1RCLK"; 1422 groups = "RMII1RCLK"; 1423 }; 1424 1425 pinctrl_rmii2rclk_default: rmii2rclk_default { 1426 function = "RMII2RCLK"; 1427 groups = "RMII2RCLK"; 1428 }; 1429 1430 pinctrl_rmii3rclk_default: rmii3rclk_default { 1431 function = "RMII3RCLK"; 1432 groups = "RMII3RCLK"; 1433 }; 1434 1435 pinctrl_rmii4rclk_default: rmii4rclk_default { 1436 function = "RMII4RCLK"; 1437 groups = "RMII4RCLK"; 1438 }; 1439 1440 pinctrl_ncts1_default: ncts1_default { 1441 function = "NCTS1"; 1442 groups = "NCTS1"; 1443 }; 1444 1445 pinctrl_ncts2_default: ncts2_default { 1446 function = "NCTS2"; 1447 groups = "NCTS2"; 1448 }; 1449 1450 pinctrl_ncts3_default: ncts3_default { 1451 function = "NCTS3"; 1452 groups = "NCTS3"; 1453 }; 1454 1455 pinctrl_ncts4_default: ncts4_default { 1456 function = "NCTS4"; 1457 groups = "NCTS4"; 1458 }; 1459 1460 pinctrl_ndcd1_default: ndcd1_default { 1461 function = "NDCD1"; 1462 groups = "NDCD1"; 1463 }; 1464 1465 pinctrl_ndcd2_default: ndcd2_default { 1466 function = "NDCD2"; 1467 groups = "NDCD2"; 1468 }; 1469 1470 pinctrl_ndcd3_default: ndcd3_default { 1471 function = "NDCD3"; 1472 groups = "NDCD3"; 1473 }; 1474 1475 pinctrl_ndcd4_default: ndcd4_default { 1476 function = "NDCD4"; 1477 groups = "NDCD4"; 1478 }; 1479 1480 pinctrl_ndsr1_default: ndsr1_default { 1481 function = "NDSR1"; 1482 groups = "NDSR1"; 1483 }; 1484 1485 pinctrl_ndsr2_default: ndsr2_default { 1486 function = "NDSR2"; 1487 groups = "NDSR2"; 1488 }; 1489 1490 pinctrl_ndsr3_default: ndsr3_default { 1491 function = "NDSR3"; 1492 groups = "NDSR3"; 1493 }; 1494 1495 pinctrl_ndsr4_default: ndsr4_default { 1496 function = "NDSR4"; 1497 groups = "NDSR4"; 1498 }; 1499 1500 pinctrl_ndtr1_default: ndtr1_default { 1501 function = "NDTR1"; 1502 groups = "NDTR1"; 1503 }; 1504 1505 pinctrl_ndtr2_default: ndtr2_default { 1506 function = "NDTR2"; 1507 groups = "NDTR2"; 1508 }; 1509 1510 pinctrl_ndtr3_default: ndtr3_default { 1511 function = "NDTR3"; 1512 groups = "NDTR3"; 1513 }; 1514 1515 pinctrl_ndtr4_default: ndtr4_default { 1516 function = "NDTR4"; 1517 groups = "NDTR4"; 1518 }; 1519 1520 pinctrl_nri1_default: nri1_default { 1521 function = "NRI1"; 1522 groups = "NRI1"; 1523 }; 1524 1525 pinctrl_nri2_default: nri2_default { 1526 function = "NRI2"; 1527 groups = "NRI2"; 1528 }; 1529 1530 pinctrl_nri3_default: nri3_default { 1531 function = "NRI3"; 1532 groups = "NRI3"; 1533 }; 1534 1535 pinctrl_nri4_default: nri4_default { 1536 function = "NRI4"; 1537 groups = "NRI4"; 1538 }; 1539 1540 pinctrl_nrts1_default: nrts1_default { 1541 function = "NRTS1"; 1542 groups = "NRTS1"; 1543 }; 1544 1545 pinctrl_nrts2_default: nrts2_default { 1546 function = "NRTS2"; 1547 groups = "NRTS2"; 1548 }; 1549 1550 pinctrl_nrts3_default: nrts3_default { 1551 function = "NRTS3"; 1552 groups = "NRTS3"; 1553 }; 1554 1555 pinctrl_nrts4_default: nrts4_default { 1556 function = "NRTS4"; 1557 groups = "NRTS4"; 1558 }; 1559 1560 pinctrl_oscclk_default: oscclk_default { 1561 function = "OSCCLK"; 1562 groups = "OSCCLK"; 1563 }; 1564 1565 pinctrl_pewake_default: pewake_default { 1566 function = "PEWAKE"; 1567 groups = "PEWAKE"; 1568 }; 1569 1570 pinctrl_pnor_default: pnor_default { 1571 function = "PNOR"; 1572 groups = "PNOR"; 1573 }; 1574 1575 pinctrl_pwm0_default: pwm0_default { 1576 function = "PWM0"; 1577 groups = "PWM0"; 1578 }; 1579 1580 pinctrl_pwm1_default: pwm1_default { 1581 function = "PWM1"; 1582 groups = "PWM1"; 1583 }; 1584 1585 pinctrl_pwm2_default: pwm2_default { 1586 function = "PWM2"; 1587 groups = "PWM2"; 1588 }; 1589 1590 pinctrl_pwm3_default: pwm3_default { 1591 function = "PWM3"; 1592 groups = "PWM3"; 1593 }; 1594 1595 pinctrl_pwm4_default: pwm4_default { 1596 function = "PWM4"; 1597 groups = "PWM4"; 1598 }; 1599 1600 pinctrl_pwm5_default: pwm5_default { 1601 function = "PWM5"; 1602 groups = "PWM5"; 1603 }; 1604 1605 pinctrl_pwm6_default: pwm6_default { 1606 function = "PWM6"; 1607 groups = "PWM6"; 1608 }; 1609 1610 pinctrl_pwm7_default: pwm7_default { 1611 function = "PWM7"; 1612 groups = "PWM7"; 1613 }; 1614 1615 pinctrl_rgmii1_default: rgmii1_default { 1616 function = "RGMII1"; 1617 groups = "RGMII1"; 1618 }; 1619 1620 pinctrl_rgmii2_default: rgmii2_default { 1621 function = "RGMII2"; 1622 groups = "RGMII2"; 1623 }; 1624 1625 pinctrl_rgmii3_default: rgmii3_default { 1626 function = "RGMII3"; 1627 groups = "RGMII3"; 1628 }; 1629 1630 pinctrl_rgmii4_default: rgmii4_default { 1631 function = "RGMII4"; 1632 groups = "RGMII4"; 1633 }; 1634 1635 pinctrl_rmii1_default: rmii1_default { 1636 function = "RMII1"; 1637 groups = "RMII1"; 1638 }; 1639 1640 pinctrl_rmii2_default: rmii2_default { 1641 function = "RMII2"; 1642 groups = "RMII2"; 1643 }; 1644 1645 pinctrl_rxd1_default: rxd1_default { 1646 function = "RXD1"; 1647 groups = "RXD1"; 1648 u-boot,dm-pre-reloc; 1649 }; 1650 1651 pinctrl_rxd2_default: rxd2_default { 1652 function = "RXD2"; 1653 groups = "RXD2"; 1654 u-boot,dm-pre-reloc; 1655 }; 1656 1657 pinctrl_rxd3_default: rxd3_default { 1658 function = "RXD3"; 1659 groups = "RXD3"; 1660 u-boot,dm-pre-reloc; 1661 }; 1662 1663 pinctrl_rxd4_default: rxd4_default { 1664 function = "RXD4"; 1665 groups = "RXD4"; 1666 u-boot,dm-pre-reloc; 1667 }; 1668 1669 pinctrl_salt1_default: salt1_default { 1670 function = "SALT1"; 1671 groups = "SALT1"; 1672 }; 1673 1674 pinctrl_salt10_default: salt10_default { 1675 function = "SALT10"; 1676 groups = "SALT10"; 1677 }; 1678 1679 pinctrl_salt11_default: salt11_default { 1680 function = "SALT11"; 1681 groups = "SALT11"; 1682 }; 1683 1684 pinctrl_salt12_default: salt12_default { 1685 function = "SALT12"; 1686 groups = "SALT12"; 1687 }; 1688 1689 pinctrl_salt13_default: salt13_default { 1690 function = "SALT13"; 1691 groups = "SALT13"; 1692 }; 1693 1694 pinctrl_salt14_default: salt14_default { 1695 function = "SALT14"; 1696 groups = "SALT14"; 1697 }; 1698 1699 pinctrl_salt2_default: salt2_default { 1700 function = "SALT2"; 1701 groups = "SALT2"; 1702 }; 1703 1704 pinctrl_salt3_default: salt3_default { 1705 function = "SALT3"; 1706 groups = "SALT3"; 1707 }; 1708 1709 pinctrl_salt4_default: salt4_default { 1710 function = "SALT4"; 1711 groups = "SALT4"; 1712 }; 1713 1714 pinctrl_salt5_default: salt5_default { 1715 function = "SALT5"; 1716 groups = "SALT5"; 1717 }; 1718 1719 pinctrl_salt6_default: salt6_default { 1720 function = "SALT6"; 1721 groups = "SALT6"; 1722 }; 1723 1724 pinctrl_salt7_default: salt7_default { 1725 function = "SALT7"; 1726 groups = "SALT7"; 1727 }; 1728 1729 pinctrl_salt8_default: salt8_default { 1730 function = "SALT8"; 1731 groups = "SALT8"; 1732 }; 1733 1734 pinctrl_salt9_default: salt9_default { 1735 function = "SALT9"; 1736 groups = "SALT9"; 1737 }; 1738 1739 pinctrl_scl1_default: scl1_default { 1740 function = "SCL1"; 1741 groups = "SCL1"; 1742 }; 1743 1744 pinctrl_scl2_default: scl2_default { 1745 function = "SCL2"; 1746 groups = "SCL2"; 1747 }; 1748 1749 pinctrl_sd1_default: sd1_default { 1750 function = "SD1"; 1751 groups = "SD1"; 1752 }; 1753 1754 pinctrl_sd2_default: sd2_default { 1755 function = "SD2"; 1756 groups = "SD2"; 1757 }; 1758 1759 pinctrl_emmc_default: emmc_default { 1760 function = "EMMC"; 1761 groups = "EMMC"; 1762 }; 1763 1764 pinctrl_emmcg8_default: emmcg8_default { 1765 function = "EMMCG8"; 1766 groups = "EMMCG8"; 1767 }; 1768 1769 pinctrl_sda1_default: sda1_default { 1770 function = "SDA1"; 1771 groups = "SDA1"; 1772 }; 1773 1774 pinctrl_sda2_default: sda2_default { 1775 function = "SDA2"; 1776 groups = "SDA2"; 1777 }; 1778 1779 pinctrl_sgps1_default: sgps1_default { 1780 function = "SGPS1"; 1781 groups = "SGPS1"; 1782 }; 1783 1784 pinctrl_sgps2_default: sgps2_default { 1785 function = "SGPS2"; 1786 groups = "SGPS2"; 1787 }; 1788 1789 pinctrl_sioonctrl_default: sioonctrl_default { 1790 function = "SIOONCTRL"; 1791 groups = "SIOONCTRL"; 1792 }; 1793 1794 pinctrl_siopbi_default: siopbi_default { 1795 function = "SIOPBI"; 1796 groups = "SIOPBI"; 1797 }; 1798 1799 pinctrl_siopbo_default: siopbo_default { 1800 function = "SIOPBO"; 1801 groups = "SIOPBO"; 1802 }; 1803 1804 pinctrl_siopwreq_default: siopwreq_default { 1805 function = "SIOPWREQ"; 1806 groups = "SIOPWREQ"; 1807 }; 1808 1809 pinctrl_siopwrgd_default: siopwrgd_default { 1810 function = "SIOPWRGD"; 1811 groups = "SIOPWRGD"; 1812 }; 1813 1814 pinctrl_sios3_default: sios3_default { 1815 function = "SIOS3"; 1816 groups = "SIOS3"; 1817 }; 1818 1819 pinctrl_sios5_default: sios5_default { 1820 function = "SIOS5"; 1821 groups = "SIOS5"; 1822 }; 1823 1824 pinctrl_siosci_default: siosci_default { 1825 function = "SIOSCI"; 1826 groups = "SIOSCI"; 1827 }; 1828 1829 pinctrl_spi1_default: spi1_default { 1830 function = "SPI1"; 1831 groups = "SPI1"; 1832 }; 1833 1834 pinctrl_spi1cs1_default: spi1cs1_default { 1835 function = "SPI1CS1"; 1836 groups = "SPI1CS1"; 1837 }; 1838 1839 pinctrl_spi1debug_default: spi1debug_default { 1840 function = "SPI1DEBUG"; 1841 groups = "SPI1DEBUG"; 1842 }; 1843 1844 pinctrl_spi1passthru_default: spi1passthru_default { 1845 function = "SPI1PASSTHRU"; 1846 groups = "SPI1PASSTHRU"; 1847 }; 1848 1849 pinctrl_spi2ck_default: spi2ck_default { 1850 function = "SPI2CK"; 1851 groups = "SPI2CK"; 1852 }; 1853 1854 pinctrl_spi2cs0_default: spi2cs0_default { 1855 function = "SPI2CS0"; 1856 groups = "SPI2CS0"; 1857 }; 1858 1859 pinctrl_spi2cs1_default: spi2cs1_default { 1860 function = "SPI2CS1"; 1861 groups = "SPI2CS1"; 1862 }; 1863 1864 pinctrl_spi2miso_default: spi2miso_default { 1865 function = "SPI2MISO"; 1866 groups = "SPI2MISO"; 1867 }; 1868 1869 pinctrl_spi2mosi_default: spi2mosi_default { 1870 function = "SPI2MOSI"; 1871 groups = "SPI2MOSI"; 1872 }; 1873 1874 pinctrl_timer3_default: timer3_default { 1875 function = "TIMER3"; 1876 groups = "TIMER3"; 1877 }; 1878 1879 pinctrl_timer4_default: timer4_default { 1880 function = "TIMER4"; 1881 groups = "TIMER4"; 1882 }; 1883 1884 pinctrl_timer5_default: timer5_default { 1885 function = "TIMER5"; 1886 groups = "TIMER5"; 1887 }; 1888 1889 pinctrl_timer6_default: timer6_default { 1890 function = "TIMER6"; 1891 groups = "TIMER6"; 1892 }; 1893 1894 pinctrl_timer7_default: timer7_default { 1895 function = "TIMER7"; 1896 groups = "TIMER7"; 1897 }; 1898 1899 pinctrl_timer8_default: timer8_default { 1900 function = "TIMER8"; 1901 groups = "TIMER8"; 1902 }; 1903 1904 pinctrl_txd1_default: txd1_default { 1905 function = "TXD1"; 1906 groups = "TXD1"; 1907 u-boot,dm-pre-reloc; 1908 }; 1909 1910 pinctrl_txd2_default: txd2_default { 1911 function = "TXD2"; 1912 groups = "TXD2"; 1913 u-boot,dm-pre-reloc; 1914 }; 1915 1916 pinctrl_txd3_default: txd3_default { 1917 function = "TXD3"; 1918 groups = "TXD3"; 1919 u-boot,dm-pre-reloc; 1920 }; 1921 1922 pinctrl_txd4_default: txd4_default { 1923 function = "TXD4"; 1924 groups = "TXD4"; 1925 u-boot,dm-pre-reloc; 1926 }; 1927 1928 pinctrl_uart6_default: uart6_default { 1929 function = "UART6"; 1930 groups = "UART6"; 1931 }; 1932 1933 pinctrl_usbcki_default: usbcki_default { 1934 function = "USBCKI"; 1935 groups = "USBCKI"; 1936 }; 1937 1938 pinctrl_usb2ad_default: usb2ad_default { 1939 function = "USB2AD"; 1940 groups = "USB2AD"; 1941 }; 1942 1943 pinctrl_usb2ah_default: usb2ah_default { 1944 function = "USB2AH"; 1945 groups = "USB2AH"; 1946 }; 1947 1948 pinctrl_usb11bhid_default: usb11bhid_default { 1949 function = "USB11BHID"; 1950 groups = "USB11BHID"; 1951 }; 1952 1953 pinctrl_usb2bh_default: usb2bh_default { 1954 function = "USB2BH"; 1955 groups = "USB2BH"; 1956 }; 1957 1958 pinctrl_vgabiosrom_default: vgabiosrom_default { 1959 function = "VGABIOSROM"; 1960 groups = "VGABIOSROM"; 1961 }; 1962 1963 pinctrl_vgahs_default: vgahs_default { 1964 function = "VGAHS"; 1965 groups = "VGAHS"; 1966 }; 1967 1968 pinctrl_vgavs_default: vgavs_default { 1969 function = "VGAVS"; 1970 groups = "VGAVS"; 1971 }; 1972 1973 pinctrl_vpi24_default: vpi24_default { 1974 function = "VPI24"; 1975 groups = "VPI24"; 1976 }; 1977 1978 pinctrl_vpo_default: vpo_default { 1979 function = "VPO"; 1980 groups = "VPO"; 1981 }; 1982 1983 pinctrl_wdtrst1_default: wdtrst1_default { 1984 function = "WDTRST1"; 1985 groups = "WDTRST1"; 1986 }; 1987 1988 pinctrl_wdtrst2_default: wdtrst2_default { 1989 function = "WDTRST2"; 1990 groups = "WDTRST2"; 1991 }; 1992 1993 pinctrl_pcie0rc_default: pcie0rc_default { 1994 function = "PCIE0RC"; 1995 groups = "PCIE0RC"; 1996 }; 1997 1998 pinctrl_pcie1rc_default: pcie1rc_default { 1999 function = "PCIE1RC"; 2000 groups = "PCIE1RC"; 2001 }; 2002}; 2003