1// SPDX-License-Identifier: GPL-2.0+ 2#include <dt-bindings/interrupt-controller/arm-gic.h> 3#include <dt-bindings/gpio/aspeed-gpio.h> 4#include "skeleton.dtsi" 5 6/ { 7 model = "Aspeed BMC"; 8 compatible = "aspeed,ast2600"; 9 #address-cells = <1>; 10 #size-cells = <1>; 11 interrupt-parent = <&gic>; 12 13 aliases { 14 i2c0 = &i2c0; 15 i2c1 = &i2c1; 16 i2c2 = &i2c2; 17 i2c3 = &i2c3; 18 i2c4 = &i2c4; 19 i2c5 = &i2c5; 20 i2c6 = &i2c6; 21 i2c7 = &i2c7; 22 i2c8 = &i2c8; 23 i2c9 = &i2c9; 24 i2c10 = &i2c10; 25 i2c11 = &i2c11; 26 i2c12 = &i2c12; 27 i2c13 = &i2c13; 28 i2c14 = &i2c14; 29 i2c15 = &i2c15; 30 serial0 = &uart1; 31 serial1 = &uart2; 32 serial2 = &uart3; 33 serial3 = &uart4; 34 serial4 = &uart5; 35 serial5 = &uart6; 36 serial6 = &uart7; 37 serial7 = &uart8; 38 serial8 = &uart9; 39 serial9 = &uart10; 40 serial10 = &uart11; 41 serial11 = &uart12; 42 serial12 = &uart13; 43 }; 44 45 cpus { 46 #address-cells = <1>; 47 #size-cells = <0>; 48 enable-method = "aspeed,ast2600-smp"; 49 50 cpu@0 { 51 compatible = "arm,cortex-a7"; 52 device_type = "cpu"; 53 reg = <0>; 54 clock-frequency = <48000000>; 55 }; 56 57 cpu@1 { 58 compatible = "arm,cortex-a7"; 59 device_type = "cpu"; 60 reg = <1>; 61 clock-frequency = <48000000>; 62 }; 63 64 }; 65 66 timer { 67 compatible = "arm,armv7-timer"; 68 interrupt-parent = <&gic>; 69 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 70 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 71 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 72 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 73 clock-frequency = <25000000>; 74 }; 75 76 memory@80000000 { 77 device_type = "memory"; 78 reg = <0x80000000 0>; 79 }; 80 81 reserved-memory { 82 #address-cells = <1>; 83 #size-cells = <1>; 84 ranges; 85 86 gfx_memory: framebuffer { 87 size = <0x01000000>; 88 alignment = <0x01000000>; 89 compatible = "shared-dma-pool"; 90 reusable; 91 }; 92 93 video_memory: video { 94 size = <0x04000000>; 95 alignment = <0x01000000>; 96 compatible = "shared-dma-pool"; 97 no-map; 98 }; 99 }; 100 101 ahb { 102 compatible = "simple-bus"; 103 #address-cells = <1>; 104 #size-cells = <1>; 105 device_type = "soc"; 106 ranges; 107 108 gic: interrupt-controller@40461000 { 109 compatible = "arm,cortex-a7-gic"; 110 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 111 #interrupt-cells = <3>; 112 interrupt-controller; 113 interrupt-parent = <&gic>; 114 reg = <0x40461000 0x1000>, 115 <0x40462000 0x1000>, 116 <0x40464000 0x2000>, 117 <0x40466000 0x2000>; 118 }; 119 120 ahbc: ahbc@1e600000 { 121 compatible = "aspeed,aspeed-ahbc"; 122 reg = < 0x1e600000 0x100>; 123 }; 124 125 fmc: flash-controller@1e620000 { 126 reg = < 0x1e620000 0xc4 127 0x20000000 0x10000000 >; 128 #address-cells = <1>; 129 #size-cells = <0>; 130 compatible = "aspeed,ast2600-fmc"; 131 status = "disabled"; 132 interrupts = <19>; 133 clocks = <&scu ASPEED_CLK_AHB>; 134 flash@0 { 135 reg = < 0 >; 136 compatible = "jedec,spi-nor"; 137 status = "disabled"; 138 }; 139 flash@1 { 140 reg = < 1 >; 141 compatible = "jedec,spi-nor"; 142 status = "disabled"; 143 }; 144 flash@2 { 145 reg = < 2 >; 146 compatible = "jedec,spi-nor"; 147 status = "disabled"; 148 }; 149 }; 150 151 spi1: flash-controller@1e630000 { 152 reg = < 0x1e630000 0xc4 153 0x30000000 0x08000000 >; 154 #address-cells = <1>; 155 #size-cells = <0>; 156 compatible = "aspeed,ast2600-spi"; 157 clocks = <&scu ASPEED_CLK_AHB>; 158 status = "disabled"; 159 flash@0 { 160 reg = < 0 >; 161 compatible = "jedec,spi-nor"; 162 status = "disabled"; 163 }; 164 flash@1 { 165 reg = < 1 >; 166 compatible = "jedec,spi-nor"; 167 status = "disabled"; 168 }; 169 }; 170 171 spi2: flash-controller@1e631000 { 172 reg = < 0x1e631000 0xc4 173 0x38000000 0x08000000 >; 174 #address-cells = <1>; 175 #size-cells = <0>; 176 compatible = "aspeed,ast2600-spi"; 177 clocks = <&scu ASPEED_CLK_AHB>; 178 status = "disabled"; 179 flash@0 { 180 reg = < 0 >; 181 compatible = "jedec,spi-nor"; 182 status = "disabled"; 183 }; 184 flash@1 { 185 reg = < 1 >; 186 compatible = "jedec,spi-nor"; 187 status = "disabled"; 188 }; 189 }; 190 191 edac: sdram@1e6e0000 { 192 compatible = "aspeed,ast2600-sdram-edac"; 193 reg = <0x1e6e0000 0x174>; 194 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 195 }; 196 197 mdio: ethernet@1e650000 { 198 compatible = "aspeed,aspeed-mdio"; 199 reg = <0x1e650000 0x40>; 200 resets = <&rst ASPEED_RESET_MII>; 201 status = "disabled"; 202 }; 203 204 mac0: ethernet@1e660000 { 205 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 206 reg = <0x1e660000 0x180>, <0x1e650000 0x4>; 207 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 208 clocks = <&scu ASPEED_CLK_GATE_MAC1CLK>; 209 status = "disabled"; 210 }; 211 212 mac2: ftgmac@1e670000 { 213 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 214 reg = <0x1e670000 0x180>, <0x1e650010 0x4>; 215 #address-cells = <1>; 216 #size-cells = <0>; 217 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 218 clocks = <&scu ASPEED_CLK_GATE_MAC3CLK>; 219#if 0 220 phy-handle = <&phy0>; 221#endif 222 status = "disabled"; 223 }; 224 225 mac1: ftgmac@1e680000 { 226 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 227 reg = <0x1e680000 0x180>, <0x1e650008 0x4>; 228 #address-cells = <1>; 229 #size-cells = <0>; 230 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 231 clocks = <&scu ASPEED_CLK_GATE_MAC2CLK>; 232#if 0 233 phy-handle = <&phy0>; 234#endif 235 status = "disabled"; 236 }; 237 238 mac3: ftgmac@1e690000 { 239 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 240 reg = <0x1e690000 0x180>, <0x1e650018 0x4>; 241 #address-cells = <1>; 242 #size-cells = <0>; 243 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 244 clocks = <&scu ASPEED_CLK_GATE_MAC4CLK>; 245#if 0 246 phy-handle = <&phy0>; 247#endif 248 status = "disabled"; 249 }; 250 251 252 apb { 253 compatible = "simple-bus"; 254 #address-cells = <1>; 255 #size-cells = <1>; 256 ranges; 257 258 syscon: syscon@1e6e2000 { 259 compatible = "aspeed,g6-scu", "syscon", "simple-mfd"; 260 reg = <0x1e6e2000 0x1000>; 261 #address-cells = <1>; 262 #size-cells = <1>; 263 #clock-cells = <1>; 264 #reset-cells = <1>; 265 ranges = <0 0x1e6e2000 0x1000>; 266 267 pinctrl: pinctrl { 268 compatible = "aspeed,g6-pinctrl"; 269 aspeed,external-nodes = <&gfx &lhc>; 270 271 }; 272 273 vga_scratch: scratch { 274 compatible = "aspeed,bmc-misc"; 275 }; 276 277 scu_ic0: interrupt-controller@0 { 278 #interrupt-cells = <1>; 279 compatible = "aspeed,ast2600-scu-ic"; 280 reg = <0x560 0x10>; 281 interrupt-parent = <&gic>; 282 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 283 interrupt-controller; 284 }; 285 286 scu_ic1: interrupt-controller@1 { 287 #interrupt-cells = <1>; 288 compatible = "aspeed,ast2600-scu-ic"; 289 reg = <0x570 0x10>; 290 interrupt-parent = <&gic>; 291 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 292 interrupt-controller; 293 }; 294 295 }; 296 297 smp-memram@0 { 298 compatible = "aspeed,ast2600-smpmem", "syscon"; 299 reg = <0x1e6e2180 0x40>; 300 }; 301 302 gfx: display@1e6e6000 { 303 compatible = "aspeed,ast2500-gfx", "syscon"; 304 reg = <0x1e6e6000 0x1000>; 305 reg-io-width = <4>; 306 }; 307 308 pcie_bridge: pcie_bridge@0x1e6ed000 { 309 compatible = "aspeed,ast2600-pcie"; 310 reg = <0x1e6ed000 0x100>, <0x60000000 0x20000000>; 311 }; 312 313 sdhci: sdhci@1e740000 { 314 #interrupt-cells = <1>; 315 compatible = "aspeed,aspeed-sdhci-irq", "simple-mfd"; 316 reg = <0x1e740000 0x1000>; 317 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 318 interrupt-controller; 319 clocks = <&scu ASPEED_CLK_GATE_SDCLK>, <&scu ASPEED_CLK_GATE_SDEXTCLK>; 320 clock-names = "ctrlclk", "extclk"; 321 #address-cells = <1>; 322 #size-cells = <1>; 323 ranges = <0x0 0x1e740000 0x1000>; 324 325 sdhci_slot0: sdhci_slot0@100 { 326 compatible = "aspeed,sdhci-ast2600"; 327 reg = <0x100 0x100>; 328 interrupts = <0>; 329 interrupt-parent = <&sdhci>; 330 sdhci,auto-cmd12; 331 clocks = <&scu ASPEED_CLK_SDIO>; 332 pwr-gpios = <&gpio0 ASPEED_GPIO(V, 0) GPIO_ACTIVE_LOW>; 333 pwr-sw-gpios = <&gpio0 ASPEED_GPIO(V, 1) GPIO_ACTIVE_LOW>; 334 status = "disabled"; 335 }; 336 337 sdhci_slot1: sdhci_slot1@200 { 338 compatible = "aspeed,sdhci-ast2600"; 339 reg = <0x200 0x100>; 340 interrupts = <1>; 341 interrupt-parent = <&sdhci>; 342 sdhci,auto-cmd12; 343 clocks = <&scu ASPEED_CLK_SDIO>; 344 pwr-gpios = <&gpio0 ASPEED_GPIO(V, 2) GPIO_ACTIVE_LOW>; 345 pwr-sw-gpios = <&gpio0 ASPEED_GPIO(V, 3) GPIO_ACTIVE_LOW>; 346 status = "disabled"; 347 }; 348 349 }; 350 351 emmc: emmc@1e750000 { 352 #interrupt-cells = <1>; 353 compatible = "aspeed,aspeed-emmc-irq", "simple-mfd"; 354 reg = <0x1e750000 0x1000>; 355 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 356 interrupt-controller; 357 clocks = <&scu ASPEED_CLK_GATE_EMMCCLK>, <&scu ASPEED_CLK_GATE_EMMCEXTCLK>; 358 clock-names = "ctrlclk", "extclk"; 359 #address-cells = <1>; 360 #size-cells = <1>; 361 ranges = <0x0 0x1e750000 0x1000>; 362 363 emmc_slot0: emmc_slot0@100 { 364 compatible = "aspeed,emmc-ast2600"; 365 reg = <0x100 0x100>; 366 interrupts = <0>; 367 interrupt-parent = <&emmc>; 368 clocks = <&scu ASPEED_CLK_EMMC>; 369 status = "disabled"; 370 }; 371 372 }; 373 374 h2x: h2x@1e770000 { 375 compatible = "aspeed,ast2600-h2x"; 376 reg = <0x1e770000 0x100>; 377 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 378 resets = <&rst ASPEED_RESET_H2X>; 379 }; 380 381 gpio0: gpio@1e780000 { 382 compatible = "aspeed,ast2600-gpio"; 383 reg = <0x1e780000 0x1000>; 384 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 385 #gpio-cells = <2>; 386 gpio-controller; 387 interrupt-controller; 388 gpio-ranges = <&pinctrl 0 0 220>; 389 }; 390 391 gpio1: gpio@1e780800 { 392 compatible = "aspeed,ast2600-gpio"; 393 reg = <0x1e780800 0x800>; 394 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 395 #gpio-cells = <2>; 396 gpio-controller; 397 interrupt-controller; 398 gpio-ranges = <&pinctrl 0 0 208>; 399 }; 400 401 uart1: serial@1e783000 { 402 compatible = "ns16550a"; 403 reg = <0x1e783000 0x20>; 404 reg-shift = <2>; 405 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 406 clocks = <&scu ASPEED_CLK_GATE_UART1CLK>; 407 no-loopback-test; 408 status = "disabled"; 409 }; 410 411 uart5: serial@1e784000 { 412 compatible = "ns16550a"; 413 reg = <0x1e784000 0x1000>; 414 reg-shift = <2>; 415 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 416 clocks = <&scu ASPEED_CLK_GATE_UART5CLK>; 417 no-loopback-test; 418 status = "disabled"; 419 }; 420 421 wdt1: watchdog@1e785000 { 422 compatible = "aspeed,ast2600-wdt"; 423 reg = <0x1e785000 0x40>; 424 }; 425 426 wdt2: watchdog@1e785040 { 427 compatible = "aspeed,ast2600-wdt"; 428 reg = <0x1e785040 0x40>; 429 }; 430 431 wdt3: watchdog@1e785080 { 432 compatible = "aspeed,ast2600-wdt"; 433 reg = <0x1e785080 0x40>; 434 }; 435 436 wdt4: watchdog@1e7850C0 { 437 compatible = "aspeed,ast2600-wdt"; 438 reg = <0x1e7850C0 0x40>; 439 }; 440 441 lpc: lpc@1e789000 { 442 compatible = "aspeed,ast-lpc", "simple-mfd", "syscon"; 443 reg = <0x1e789000 0x200>; 444 445 #address-cells = <1>; 446 #size-cells = <1>; 447 ranges = <0x0 0x1e789000 0x1000>; 448 449 lpc_bmc: lpc-bmc@0 { 450 compatible = "aspeed,ast2600-lpc-bmc", "simple-mfd", "syscon"; 451 reg = <0x0 0x80>; 452 reg-io-width = <4>; 453 #address-cells = <1>; 454 #size-cells = <1>; 455 ranges = <0x0 0x0 0x80>; 456 457 kcs1: kcs1@0 { 458 compatible = "aspeed,ast2600-kcs-bmc"; 459 reg = <0x0 0x80>; 460 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 461 kcs_chan = <1>; 462 kcs_addr = <0xCA0>; 463 status = "disabled"; 464 }; 465 466 kcs2: kcs2@0 { 467 compatible = "aspeed,ast2600-kcs-bmc"; 468 reg = <0x0 0x80>; 469 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 470 kcs_chan = <2>; 471 kcs_addr = <0xCA8>; 472 status = "disabled"; 473 }; 474 475 kcs3: kcs3@0 { 476 compatible = "aspeed,ast2600-kcs-bmc"; 477 reg = <0x0 0x80>; 478 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 479 kcs_chan = <3>; 480 kcs_addr = <0xCA2>; 481 }; 482 483 kcs4: kcs4@0 { 484 compatible = "aspeed,ast2600-kcs-bmc"; 485 reg = <0x0 0x120>; 486 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 487 kcs_chan = <4>; 488 kcs_addr = <0xCA4>; 489 status = "disabled"; 490 }; 491 492 }; 493 494 lpc_host: lpc-host@80 { 495 compatible = "aspeed,ast2600-lpc-host", "simple-mfd", "syscon"; 496 reg = <0x80 0x1e0>; 497 reg-io-width = <4>; 498 499 #address-cells = <1>; 500 #size-cells = <1>; 501 ranges = <0x0 0x80 0x1e0>; 502 503 lpc_ctrl: lpc-ctrl@0 { 504 compatible = "aspeed,ast2600-lpc-ctrl"; 505 reg = <0x0 0x80>; 506 status = "disabled"; 507 }; 508 509 lpc_snoop: lpc-snoop@0 { 510 compatible = "aspeed,ast2600-lpc-snoop"; 511 reg = <0x0 0x80>; 512 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 513 snoop-ports = <0x80>; 514 status = "disabled"; 515 }; 516 517 lhc: lhc@20 { 518 compatible = "aspeed,ast2600-lhc"; 519 reg = <0x20 0x24 0x48 0x8>; 520 }; 521 522 lpc_reset: reset-controller@18 { 523 compatible = "aspeed,ast2600-lpc-reset"; 524 reg = <0x18 0x4>; 525 #reset-cells = <1>; 526 status = "disabled"; 527 }; 528 529 ibt: ibt@c0 { 530 compatible = "aspeed,ast2600-ibt-bmc"; 531 reg = <0xc0 0x18>; 532 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 533 status = "disabled"; 534 }; 535 536 sio_regs: regs { 537 compatible = "aspeed,bmc-misc"; 538 }; 539 540 mbox: mbox@180 { 541 compatible = "aspeed,ast2600-mbox"; 542 reg = <0x180 0x5c>; 543 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 544 #mbox-cells = <1>; 545 status = "disabled"; 546 }; 547 }; 548 }; 549 550 uart2: serial@1e78d000 { 551 compatible = "ns16550a"; 552 reg = <0x1e78d000 0x20>; 553 reg-shift = <2>; 554 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 555 clocks = <&scu ASPEED_CLK_GATE_UART2CLK>; 556 no-loopback-test; 557 status = "disabled"; 558 }; 559 560 uart3: serial@1e78e000 { 561 compatible = "ns16550a"; 562 reg = <0x1e78e000 0x20>; 563 reg-shift = <2>; 564 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 565 clocks = <&scu ASPEED_CLK_GATE_UART3CLK>; 566 no-loopback-test; 567 status = "disabled"; 568 }; 569 570 uart4: serial@1e78f000 { 571 compatible = "ns16550a"; 572 reg = <0x1e78f000 0x20>; 573 reg-shift = <2>; 574 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 575 clocks = <&scu ASPEED_CLK_GATE_UART4CLK>; 576 no-loopback-test; 577 status = "disabled"; 578 }; 579 580 i2c: bus@1e78a000 { 581 compatible = "simple-bus"; 582 #address-cells = <1>; 583 #size-cells = <1>; 584 ranges = <0 0x1e78a000 0x1000>; 585 }; 586 587 uart6: serial@1e790000 { 588 compatible = "ns16550a"; 589 reg = <0x1e790000 0x20>; 590 reg-shift = <2>; 591 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 592 clocks = <&scu ASPEED_CLK_GATE_UART6CLK>; 593 no-loopback-test; 594 status = "disabled"; 595 }; 596 597 uart7: serial@1e790100 { 598 compatible = "ns16550a"; 599 reg = <0x1e790100 0x20>; 600 reg-shift = <2>; 601 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 602 clocks = <&scu ASPEED_CLK_GATE_UART7CLK>; 603 no-loopback-test; 604 status = "disabled"; 605 }; 606 607 uart8: serial@1e790200 { 608 compatible = "ns16550a"; 609 reg = <0x1e790200 0x20>; 610 reg-shift = <2>; 611 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 612 clocks = <&scu ASPEED_CLK_GATE_UART8CLK>; 613 no-loopback-test; 614 status = "disabled"; 615 }; 616 617 uart9: serial@1e790300 { 618 compatible = "ns16550a"; 619 reg = <0x1e790300 0x20>; 620 reg-shift = <2>; 621 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 622 clocks = <&scu ASPEED_CLK_GATE_UART9CLK>; 623 no-loopback-test; 624 status = "disabled"; 625 }; 626 627 uart10: serial@1e790400 { 628 compatible = "ns16550a"; 629 reg = <0x1e790400 0x20>; 630 reg-shift = <2>; 631 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 632 clocks = <&scu ASPEED_CLK_GATE_UART10CLK>; 633 no-loopback-test; 634 status = "disabled"; 635 }; 636 637 uart11: serial@1e790500 { 638 compatible = "ns16550a"; 639 reg = <0x1e790400 0x20>; 640 reg-shift = <2>; 641 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 642 clocks = <&scu ASPEED_CLK_GATE_UART11CLK>; 643 no-loopback-test; 644 status = "disabled"; 645 }; 646 647 uart12: serial@1e790600 { 648 compatible = "ns16550a"; 649 reg = <0x1e790600 0x20>; 650 reg-shift = <2>; 651 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 652 clocks = <&scu ASPEED_CLK_GATE_UART12CLK>; 653 no-loopback-test; 654 status = "disabled"; 655 }; 656 657 uart13: serial@1e790700 { 658 compatible = "ns16550a"; 659 reg = <0x1e790700 0x20>; 660 reg-shift = <2>; 661 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 662 clocks = <&scu ASPEED_CLK_GATE_UART13CLK>; 663 no-loopback-test; 664 status = "disabled"; 665 }; 666 667 668 669 }; 670 671 }; 672 673}; 674 675&i2c { 676 i2cglobal: i2cg@00 { 677 compatible = "aspeed,ast2600-i2c-global"; 678 reg = <0x0 0x40>; 679 resets = <&rst ASPEED_RESET_I2C>; 680#if 0 681 new-mode; 682#endif 683 }; 684 685 i2c0: i2c@80 { 686 #address-cells = <1>; 687 #size-cells = <0>; 688 #interrupt-cells = <1>; 689 690 reg = <0x80 0x80 0xC00 0x20>; 691 compatible = "aspeed,ast2600-i2c-bus"; 692 bus-frequency = <100000>; 693 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 694 clocks = <&scu ASPEED_CLK_APB>; 695 status = "disabled"; 696 }; 697 698 i2c1: i2c@100 { 699 #address-cells = <1>; 700 #size-cells = <0>; 701 #interrupt-cells = <1>; 702 703 reg = <0x100 0x80 0xC20 0x20>; 704 compatible = "aspeed,ast2600-i2c-bus"; 705 bus-frequency = <100000>; 706 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 707 clocks = <&scu ASPEED_CLK_APB>; 708 status = "disabled"; 709 }; 710 711 i2c2: i2c@180 { 712 #address-cells = <1>; 713 #size-cells = <0>; 714 #interrupt-cells = <1>; 715 716 reg = <0x180 0x80 0xC40 0x20>; 717 compatible = "aspeed,ast2600-i2c-bus"; 718 bus-frequency = <100000>; 719 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 720 clocks = <&scu ASPEED_CLK_APB>; 721 }; 722 723 i2c3: i2c@200 { 724 #address-cells = <1>; 725 #size-cells = <0>; 726 #interrupt-cells = <1>; 727 728 reg = <0x200 0x40 0xC60 0x20>; 729 compatible = "aspeed,ast2600-i2c-bus"; 730 bus-frequency = <100000>; 731 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 732 clocks = <&scu ASPEED_CLK_APB>; 733 }; 734 735 i2c4: i2c@280 { 736 #address-cells = <1>; 737 #size-cells = <0>; 738 #interrupt-cells = <1>; 739 740 reg = <0x280 0x80 0xC80 0x20>; 741 compatible = "aspeed,ast2600-i2c-bus"; 742 bus-frequency = <100000>; 743 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 744 clocks = <&scu ASPEED_CLK_APB>; 745 }; 746 747 i2c5: i2c@300 { 748 #address-cells = <1>; 749 #size-cells = <0>; 750 #interrupt-cells = <1>; 751 752 reg = <0x300 0x40 0xCA0 0x20>; 753 compatible = "aspeed,ast2600-i2c-bus"; 754 bus-frequency = <100000>; 755 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 756 clocks = <&scu ASPEED_CLK_APB>; 757 }; 758 759 i2c6: i2c@380 { 760 #address-cells = <1>; 761 #size-cells = <0>; 762 #interrupt-cells = <1>; 763 764 reg = <0x380 0x80 0xCC0 0x20>; 765 compatible = "aspeed,ast2600-i2c-bus"; 766 bus-frequency = <100000>; 767 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 768 clocks = <&scu ASPEED_CLK_APB>; 769 }; 770 771 i2c7: i2c@400 { 772 #address-cells = <1>; 773 #size-cells = <0>; 774 #interrupt-cells = <1>; 775 776 reg = <0x400 0x80 0xCE0 0x20>; 777 compatible = "aspeed,ast2600-i2c-bus"; 778 bus-frequency = <100000>; 779 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 780 clocks = <&scu ASPEED_CLK_APB>; 781 }; 782 783 i2c8: i2c@480 { 784 #address-cells = <1>; 785 #size-cells = <0>; 786 #interrupt-cells = <1>; 787 788 reg = <0x480 0x80 0xD00 0x20>; 789 compatible = "aspeed,ast2600-i2c-bus"; 790 bus-frequency = <100000>; 791 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 792 clocks = <&scu ASPEED_CLK_APB>; 793 }; 794 795 i2c9: i2c@500 { 796 #address-cells = <1>; 797 #size-cells = <0>; 798 #interrupt-cells = <1>; 799 800 reg = <0x500 0x80 0xD20 0x20>; 801 compatible = "aspeed,ast2600-i2c-bus"; 802 bus-frequency = <100000>; 803 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 804 clocks = <&scu ASPEED_CLK_APB>; 805 status = "disabled"; 806 }; 807 808 i2c10: i2c@580 { 809 #address-cells = <1>; 810 #size-cells = <0>; 811 #interrupt-cells = <1>; 812 813 reg = <0x580 0x80 0xD40 0x20>; 814 compatible = "aspeed,ast2600-i2c-bus"; 815 bus-frequency = <100000>; 816 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 817 clocks = <&scu ASPEED_CLK_APB>; 818 status = "disabled"; 819 }; 820 821 i2c11: i2c@600 { 822 #address-cells = <1>; 823 #size-cells = <0>; 824 #interrupt-cells = <1>; 825 826 reg = <0x600 0x80 0xD60 0x20>; 827 compatible = "aspeed,ast2600-i2c-bus"; 828 bus-frequency = <100000>; 829 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 830 clocks = <&scu ASPEED_CLK_APB>; 831 status = "disabled"; 832 }; 833 834 i2c12: i2c@680 { 835 #address-cells = <1>; 836 #size-cells = <0>; 837 #interrupt-cells = <1>; 838 839 reg = <0x680 0x80 0xD80 0x20>; 840 compatible = "aspeed,ast2600-i2c-bus"; 841 bus-frequency = <100000>; 842 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 843 clocks = <&scu ASPEED_CLK_APB>; 844 status = "disabled"; 845 }; 846 847 i2c13: i2c@700 { 848 #address-cells = <1>; 849 #size-cells = <0>; 850 #interrupt-cells = <1>; 851 852 reg = <0x700 0x80 0xDA0 0x20>; 853 compatible = "aspeed,ast2600-i2c-bus"; 854 bus-frequency = <100000>; 855 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 856 clocks = <&scu ASPEED_CLK_APB>; 857 status = "disabled"; 858 }; 859 860 i2c14: i2c@780 { 861 #address-cells = <1>; 862 #size-cells = <0>; 863 #interrupt-cells = <1>; 864 865 reg = <0x780 0x80 0xDC0 0x20>; 866 compatible = "aspeed,ast2600-i2c-bus"; 867 bus-frequency = <100000>; 868 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 869 clocks = <&scu ASPEED_CLK_APB>; 870 status = "disabled"; 871 }; 872 873 i2c15: i2c@800 { 874 #address-cells = <1>; 875 #size-cells = <0>; 876 #interrupt-cells = <1>; 877 878 reg = <0x800 0x80 0xDE0 0x20>; 879 compatible = "aspeed,ast2600-i2c-bus"; 880 bus-frequency = <100000>; 881 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 882 clocks = <&scu ASPEED_CLK_APB>; 883 status = "disabled"; 884 }; 885 886}; 887 888&pinctrl { 889 pinctrl_acpi_default: acpi_default { 890 function = "ACPI"; 891 groups = "ACPI"; 892 }; 893 894 pinctrl_adc0_default: adc0_default { 895 function = "ADC0"; 896 groups = "ADC0"; 897 }; 898 899 pinctrl_adc1_default: adc1_default { 900 function = "ADC1"; 901 groups = "ADC1"; 902 }; 903 904 pinctrl_adc10_default: adc10_default { 905 function = "ADC10"; 906 groups = "ADC10"; 907 }; 908 909 pinctrl_adc11_default: adc11_default { 910 function = "ADC11"; 911 groups = "ADC11"; 912 }; 913 914 pinctrl_adc12_default: adc12_default { 915 function = "ADC12"; 916 groups = "ADC12"; 917 }; 918 919 pinctrl_adc13_default: adc13_default { 920 function = "ADC13"; 921 groups = "ADC13"; 922 }; 923 924 pinctrl_adc14_default: adc14_default { 925 function = "ADC14"; 926 groups = "ADC14"; 927 }; 928 929 pinctrl_adc15_default: adc15_default { 930 function = "ADC15"; 931 groups = "ADC15"; 932 }; 933 934 pinctrl_adc2_default: adc2_default { 935 function = "ADC2"; 936 groups = "ADC2"; 937 }; 938 939 pinctrl_adc3_default: adc3_default { 940 function = "ADC3"; 941 groups = "ADC3"; 942 }; 943 944 pinctrl_adc4_default: adc4_default { 945 function = "ADC4"; 946 groups = "ADC4"; 947 }; 948 949 pinctrl_adc5_default: adc5_default { 950 function = "ADC5"; 951 groups = "ADC5"; 952 }; 953 954 pinctrl_adc6_default: adc6_default { 955 function = "ADC6"; 956 groups = "ADC6"; 957 }; 958 959 pinctrl_adc7_default: adc7_default { 960 function = "ADC7"; 961 groups = "ADC7"; 962 }; 963 964 pinctrl_adc8_default: adc8_default { 965 function = "ADC8"; 966 groups = "ADC8"; 967 }; 968 969 pinctrl_adc9_default: adc9_default { 970 function = "ADC9"; 971 groups = "ADC9"; 972 }; 973 974 pinctrl_bmcint_default: bmcint_default { 975 function = "BMCINT"; 976 groups = "BMCINT"; 977 }; 978 979 pinctrl_ddcclk_default: ddcclk_default { 980 function = "DDCCLK"; 981 groups = "DDCCLK"; 982 }; 983 984 pinctrl_ddcdat_default: ddcdat_default { 985 function = "DDCDAT"; 986 groups = "DDCDAT"; 987 }; 988 989 pinctrl_espi_default: espi_default { 990 function = "ESPI"; 991 groups = "ESPI"; 992 }; 993 994 pinctrl_fwspics1_default: fwspics1_default { 995 function = "FWSPICS1"; 996 groups = "FWSPICS1"; 997 }; 998 999 pinctrl_fwspics2_default: fwspics2_default { 1000 function = "FWSPICS2"; 1001 groups = "FWSPICS2"; 1002 }; 1003 1004 pinctrl_gpid0_default: gpid0_default { 1005 function = "GPID0"; 1006 groups = "GPID0"; 1007 }; 1008 1009 pinctrl_gpid2_default: gpid2_default { 1010 function = "GPID2"; 1011 groups = "GPID2"; 1012 }; 1013 1014 pinctrl_gpid4_default: gpid4_default { 1015 function = "GPID4"; 1016 groups = "GPID4"; 1017 }; 1018 1019 pinctrl_gpid6_default: gpid6_default { 1020 function = "GPID6"; 1021 groups = "GPID6"; 1022 }; 1023 1024 pinctrl_gpie0_default: gpie0_default { 1025 function = "GPIE0"; 1026 groups = "GPIE0"; 1027 }; 1028 1029 pinctrl_gpie2_default: gpie2_default { 1030 function = "GPIE2"; 1031 groups = "GPIE2"; 1032 }; 1033 1034 pinctrl_gpie4_default: gpie4_default { 1035 function = "GPIE4"; 1036 groups = "GPIE4"; 1037 }; 1038 1039 pinctrl_gpie6_default: gpie6_default { 1040 function = "GPIE6"; 1041 groups = "GPIE6"; 1042 }; 1043 1044 pinctrl_i2c10_default: i2c10_default { 1045 function = "I2C10"; 1046 groups = "I2C10"; 1047 }; 1048 1049 pinctrl_i2c11_default: i2c11_default { 1050 function = "I2C11"; 1051 groups = "I2C11"; 1052 }; 1053 1054 pinctrl_i2c12_default: i2c12_default { 1055 function = "I2C12"; 1056 groups = "I2C12"; 1057 }; 1058 1059 pinctrl_i2c13_default: i2c13_default { 1060 function = "I2C13"; 1061 groups = "I2C13"; 1062 }; 1063 1064 pinctrl_i2c14_default: i2c14_default { 1065 function = "I2C14"; 1066 groups = "I2C14"; 1067 }; 1068 1069 pinctrl_i2c3_default: i2c3_default { 1070 function = "I2C3"; 1071 groups = "I2C3"; 1072 }; 1073 1074 pinctrl_i2c4_default: i2c4_default { 1075 function = "I2C4"; 1076 groups = "I2C4"; 1077 }; 1078 1079 pinctrl_i2c5_default: i2c5_default { 1080 function = "I2C5"; 1081 groups = "I2C5"; 1082 }; 1083 1084 pinctrl_i2c6_default: i2c6_default { 1085 function = "I2C6"; 1086 groups = "I2C6"; 1087 }; 1088 1089 pinctrl_i2c7_default: i2c7_default { 1090 function = "I2C7"; 1091 groups = "I2C7"; 1092 }; 1093 1094 pinctrl_i2c8_default: i2c8_default { 1095 function = "I2C8"; 1096 groups = "I2C8"; 1097 }; 1098 1099 pinctrl_i2c9_default: i2c9_default { 1100 function = "I2C9"; 1101 groups = "I2C9"; 1102 }; 1103 1104 pinctrl_lad0_default: lad0_default { 1105 function = "LAD0"; 1106 groups = "LAD0"; 1107 }; 1108 1109 pinctrl_lad1_default: lad1_default { 1110 function = "LAD1"; 1111 groups = "LAD1"; 1112 }; 1113 1114 pinctrl_lad2_default: lad2_default { 1115 function = "LAD2"; 1116 groups = "LAD2"; 1117 }; 1118 1119 pinctrl_lad3_default: lad3_default { 1120 function = "LAD3"; 1121 groups = "LAD3"; 1122 }; 1123 1124 pinctrl_lclk_default: lclk_default { 1125 function = "LCLK"; 1126 groups = "LCLK"; 1127 }; 1128 1129 pinctrl_lframe_default: lframe_default { 1130 function = "LFRAME"; 1131 groups = "LFRAME"; 1132 }; 1133 1134 pinctrl_lpchc_default: lpchc_default { 1135 function = "LPCHC"; 1136 groups = "LPCHC"; 1137 }; 1138 1139 pinctrl_lpcpd_default: lpcpd_default { 1140 function = "LPCPD"; 1141 groups = "LPCPD"; 1142 }; 1143 1144 pinctrl_lpcplus_default: lpcplus_default { 1145 function = "LPCPLUS"; 1146 groups = "LPCPLUS"; 1147 }; 1148 1149 pinctrl_lpcpme_default: lpcpme_default { 1150 function = "LPCPME"; 1151 groups = "LPCPME"; 1152 }; 1153 1154 pinctrl_lpcrst_default: lpcrst_default { 1155 function = "LPCRST"; 1156 groups = "LPCRST"; 1157 }; 1158 1159 pinctrl_lpcsmi_default: lpcsmi_default { 1160 function = "LPCSMI"; 1161 groups = "LPCSMI"; 1162 }; 1163 1164 pinctrl_lsirq_default: lsirq_default { 1165 function = "LSIRQ"; 1166 groups = "LSIRQ"; 1167 }; 1168 1169 pinctrl_mac1link_default: mac1link_default { 1170 function = "MAC1LINK"; 1171 groups = "MAC1LINK"; 1172 }; 1173 1174 pinctrl_mac2link_default: mac2link_default { 1175 function = "MAC2LINK"; 1176 groups = "MAC2LINK"; 1177 }; 1178 1179 pinctrl_mac3link_default: mac3link_default { 1180 function = "MAC3LINK"; 1181 groups = "MAC3LINK"; 1182 }; 1183 1184 pinctrl_mac4link_default: mac4link_default { 1185 function = "MAC4LINK"; 1186 groups = "MAC4LINK"; 1187 }; 1188 1189 pinctrl_mdio1_default: mdio1_default { 1190 function = "MDIO1"; 1191 groups = "MDIO1"; 1192 }; 1193 1194 pinctrl_mdio2_default: mdio2_default { 1195 function = "MDIO2"; 1196 groups = "MDIO2"; 1197 }; 1198 1199 pinctrl_mdio3_default: mdio3_default { 1200 function = "MDIO3"; 1201 groups = "MDIO3"; 1202 }; 1203 1204 pinctrl_mdio4_default: mdio4_default { 1205 function = "MDIO4"; 1206 groups = "MDIO4"; 1207 }; 1208 1209 pinctrl_ncts1_default: ncts1_default { 1210 function = "NCTS1"; 1211 groups = "NCTS1"; 1212 }; 1213 1214 pinctrl_ncts2_default: ncts2_default { 1215 function = "NCTS2"; 1216 groups = "NCTS2"; 1217 }; 1218 1219 pinctrl_ncts3_default: ncts3_default { 1220 function = "NCTS3"; 1221 groups = "NCTS3"; 1222 }; 1223 1224 pinctrl_ncts4_default: ncts4_default { 1225 function = "NCTS4"; 1226 groups = "NCTS4"; 1227 }; 1228 1229 pinctrl_ndcd1_default: ndcd1_default { 1230 function = "NDCD1"; 1231 groups = "NDCD1"; 1232 }; 1233 1234 pinctrl_ndcd2_default: ndcd2_default { 1235 function = "NDCD2"; 1236 groups = "NDCD2"; 1237 }; 1238 1239 pinctrl_ndcd3_default: ndcd3_default { 1240 function = "NDCD3"; 1241 groups = "NDCD3"; 1242 }; 1243 1244 pinctrl_ndcd4_default: ndcd4_default { 1245 function = "NDCD4"; 1246 groups = "NDCD4"; 1247 }; 1248 1249 pinctrl_ndsr1_default: ndsr1_default { 1250 function = "NDSR1"; 1251 groups = "NDSR1"; 1252 }; 1253 1254 pinctrl_ndsr2_default: ndsr2_default { 1255 function = "NDSR2"; 1256 groups = "NDSR2"; 1257 }; 1258 1259 pinctrl_ndsr3_default: ndsr3_default { 1260 function = "NDSR3"; 1261 groups = "NDSR3"; 1262 }; 1263 1264 pinctrl_ndsr4_default: ndsr4_default { 1265 function = "NDSR4"; 1266 groups = "NDSR4"; 1267 }; 1268 1269 pinctrl_ndtr1_default: ndtr1_default { 1270 function = "NDTR1"; 1271 groups = "NDTR1"; 1272 }; 1273 1274 pinctrl_ndtr2_default: ndtr2_default { 1275 function = "NDTR2"; 1276 groups = "NDTR2"; 1277 }; 1278 1279 pinctrl_ndtr3_default: ndtr3_default { 1280 function = "NDTR3"; 1281 groups = "NDTR3"; 1282 }; 1283 1284 pinctrl_ndtr4_default: ndtr4_default { 1285 function = "NDTR4"; 1286 groups = "NDTR4"; 1287 }; 1288 1289 pinctrl_nri1_default: nri1_default { 1290 function = "NRI1"; 1291 groups = "NRI1"; 1292 }; 1293 1294 pinctrl_nri2_default: nri2_default { 1295 function = "NRI2"; 1296 groups = "NRI2"; 1297 }; 1298 1299 pinctrl_nri3_default: nri3_default { 1300 function = "NRI3"; 1301 groups = "NRI3"; 1302 }; 1303 1304 pinctrl_nri4_default: nri4_default { 1305 function = "NRI4"; 1306 groups = "NRI4"; 1307 }; 1308 1309 pinctrl_nrts1_default: nrts1_default { 1310 function = "NRTS1"; 1311 groups = "NRTS1"; 1312 }; 1313 1314 pinctrl_nrts2_default: nrts2_default { 1315 function = "NRTS2"; 1316 groups = "NRTS2"; 1317 }; 1318 1319 pinctrl_nrts3_default: nrts3_default { 1320 function = "NRTS3"; 1321 groups = "NRTS3"; 1322 }; 1323 1324 pinctrl_nrts4_default: nrts4_default { 1325 function = "NRTS4"; 1326 groups = "NRTS4"; 1327 }; 1328 1329 pinctrl_oscclk_default: oscclk_default { 1330 function = "OSCCLK"; 1331 groups = "OSCCLK"; 1332 }; 1333 1334 pinctrl_pewake_default: pewake_default { 1335 function = "PEWAKE"; 1336 groups = "PEWAKE"; 1337 }; 1338 1339 pinctrl_pnor_default: pnor_default { 1340 function = "PNOR"; 1341 groups = "PNOR"; 1342 }; 1343 1344 pinctrl_pwm0_default: pwm0_default { 1345 function = "PWM0"; 1346 groups = "PWM0"; 1347 }; 1348 1349 pinctrl_pwm1_default: pwm1_default { 1350 function = "PWM1"; 1351 groups = "PWM1"; 1352 }; 1353 1354 pinctrl_pwm2_default: pwm2_default { 1355 function = "PWM2"; 1356 groups = "PWM2"; 1357 }; 1358 1359 pinctrl_pwm3_default: pwm3_default { 1360 function = "PWM3"; 1361 groups = "PWM3"; 1362 }; 1363 1364 pinctrl_pwm4_default: pwm4_default { 1365 function = "PWM4"; 1366 groups = "PWM4"; 1367 }; 1368 1369 pinctrl_pwm5_default: pwm5_default { 1370 function = "PWM5"; 1371 groups = "PWM5"; 1372 }; 1373 1374 pinctrl_pwm6_default: pwm6_default { 1375 function = "PWM6"; 1376 groups = "PWM6"; 1377 }; 1378 1379 pinctrl_pwm7_default: pwm7_default { 1380 function = "PWM7"; 1381 groups = "PWM7"; 1382 }; 1383 1384 pinctrl_rgmii1_default: rgmii1_default { 1385 function = "RGMII1"; 1386 groups = "RGMII1"; 1387 }; 1388 1389 pinctrl_rgmii2_default: rgmii2_default { 1390 function = "RGMII2"; 1391 groups = "RGMII2"; 1392 }; 1393 1394 pinctrl_rmii1_default: rmii1_default { 1395 function = "RMII1"; 1396 groups = "RMII1"; 1397 }; 1398 1399 pinctrl_rmii2_default: rmii2_default { 1400 function = "RMII2"; 1401 groups = "RMII2"; 1402 }; 1403 1404 pinctrl_rxd1_default: rxd1_default { 1405 function = "RXD1"; 1406 groups = "RXD1"; 1407 }; 1408 1409 pinctrl_rxd2_default: rxd2_default { 1410 function = "RXD2"; 1411 groups = "RXD2"; 1412 }; 1413 1414 pinctrl_rxd3_default: rxd3_default { 1415 function = "RXD3"; 1416 groups = "RXD3"; 1417 }; 1418 1419 pinctrl_rxd4_default: rxd4_default { 1420 function = "RXD4"; 1421 groups = "RXD4"; 1422 }; 1423 1424 pinctrl_salt1_default: salt1_default { 1425 function = "SALT1"; 1426 groups = "SALT1"; 1427 }; 1428 1429 pinctrl_salt10_default: salt10_default { 1430 function = "SALT10"; 1431 groups = "SALT10"; 1432 }; 1433 1434 pinctrl_salt11_default: salt11_default { 1435 function = "SALT11"; 1436 groups = "SALT11"; 1437 }; 1438 1439 pinctrl_salt12_default: salt12_default { 1440 function = "SALT12"; 1441 groups = "SALT12"; 1442 }; 1443 1444 pinctrl_salt13_default: salt13_default { 1445 function = "SALT13"; 1446 groups = "SALT13"; 1447 }; 1448 1449 pinctrl_salt14_default: salt14_default { 1450 function = "SALT14"; 1451 groups = "SALT14"; 1452 }; 1453 1454 pinctrl_salt2_default: salt2_default { 1455 function = "SALT2"; 1456 groups = "SALT2"; 1457 }; 1458 1459 pinctrl_salt3_default: salt3_default { 1460 function = "SALT3"; 1461 groups = "SALT3"; 1462 }; 1463 1464 pinctrl_salt4_default: salt4_default { 1465 function = "SALT4"; 1466 groups = "SALT4"; 1467 }; 1468 1469 pinctrl_salt5_default: salt5_default { 1470 function = "SALT5"; 1471 groups = "SALT5"; 1472 }; 1473 1474 pinctrl_salt6_default: salt6_default { 1475 function = "SALT6"; 1476 groups = "SALT6"; 1477 }; 1478 1479 pinctrl_salt7_default: salt7_default { 1480 function = "SALT7"; 1481 groups = "SALT7"; 1482 }; 1483 1484 pinctrl_salt8_default: salt8_default { 1485 function = "SALT8"; 1486 groups = "SALT8"; 1487 }; 1488 1489 pinctrl_salt9_default: salt9_default { 1490 function = "SALT9"; 1491 groups = "SALT9"; 1492 }; 1493 1494 pinctrl_scl1_default: scl1_default { 1495 function = "SCL1"; 1496 groups = "SCL1"; 1497 }; 1498 1499 pinctrl_scl2_default: scl2_default { 1500 function = "SCL2"; 1501 groups = "SCL2"; 1502 }; 1503 1504 pinctrl_sd1_default: sd1_default { 1505 function = "SD1"; 1506 groups = "SD1"; 1507 }; 1508 1509 pinctrl_sd2_default: sd2_default { 1510 function = "SD2"; 1511 groups = "SD2"; 1512 }; 1513 1514 pinctrl_emmc_default: emmc_default { 1515 function = "EMMC"; 1516 groups = "EMMC"; 1517 }; 1518 1519 pinctrl_sda1_default: sda1_default { 1520 function = "SDA1"; 1521 groups = "SDA1"; 1522 }; 1523 1524 pinctrl_sda2_default: sda2_default { 1525 function = "SDA2"; 1526 groups = "SDA2"; 1527 }; 1528 1529 pinctrl_sgps1_default: sgps1_default { 1530 function = "SGPS1"; 1531 groups = "SGPS1"; 1532 }; 1533 1534 pinctrl_sgps2_default: sgps2_default { 1535 function = "SGPS2"; 1536 groups = "SGPS2"; 1537 }; 1538 1539 pinctrl_sioonctrl_default: sioonctrl_default { 1540 function = "SIOONCTRL"; 1541 groups = "SIOONCTRL"; 1542 }; 1543 1544 pinctrl_siopbi_default: siopbi_default { 1545 function = "SIOPBI"; 1546 groups = "SIOPBI"; 1547 }; 1548 1549 pinctrl_siopbo_default: siopbo_default { 1550 function = "SIOPBO"; 1551 groups = "SIOPBO"; 1552 }; 1553 1554 pinctrl_siopwreq_default: siopwreq_default { 1555 function = "SIOPWREQ"; 1556 groups = "SIOPWREQ"; 1557 }; 1558 1559 pinctrl_siopwrgd_default: siopwrgd_default { 1560 function = "SIOPWRGD"; 1561 groups = "SIOPWRGD"; 1562 }; 1563 1564 pinctrl_sios3_default: sios3_default { 1565 function = "SIOS3"; 1566 groups = "SIOS3"; 1567 }; 1568 1569 pinctrl_sios5_default: sios5_default { 1570 function = "SIOS5"; 1571 groups = "SIOS5"; 1572 }; 1573 1574 pinctrl_siosci_default: siosci_default { 1575 function = "SIOSCI"; 1576 groups = "SIOSCI"; 1577 }; 1578 1579 pinctrl_spi1_default: spi1_default { 1580 function = "SPI1"; 1581 groups = "SPI1"; 1582 }; 1583 1584 pinctrl_spi1cs1_default: spi1cs1_default { 1585 function = "SPI1CS1"; 1586 groups = "SPI1CS1"; 1587 }; 1588 1589 pinctrl_spi1debug_default: spi1debug_default { 1590 function = "SPI1DEBUG"; 1591 groups = "SPI1DEBUG"; 1592 }; 1593 1594 pinctrl_spi1passthru_default: spi1passthru_default { 1595 function = "SPI1PASSTHRU"; 1596 groups = "SPI1PASSTHRU"; 1597 }; 1598 1599 pinctrl_spi2ck_default: spi2ck_default { 1600 function = "SPI2CK"; 1601 groups = "SPI2CK"; 1602 }; 1603 1604 pinctrl_spi2cs0_default: spi2cs0_default { 1605 function = "SPI2CS0"; 1606 groups = "SPI2CS0"; 1607 }; 1608 1609 pinctrl_spi2cs1_default: spi2cs1_default { 1610 function = "SPI2CS1"; 1611 groups = "SPI2CS1"; 1612 }; 1613 1614 pinctrl_spi2miso_default: spi2miso_default { 1615 function = "SPI2MISO"; 1616 groups = "SPI2MISO"; 1617 }; 1618 1619 pinctrl_spi2mosi_default: spi2mosi_default { 1620 function = "SPI2MOSI"; 1621 groups = "SPI2MOSI"; 1622 }; 1623 1624 pinctrl_timer3_default: timer3_default { 1625 function = "TIMER3"; 1626 groups = "TIMER3"; 1627 }; 1628 1629 pinctrl_timer4_default: timer4_default { 1630 function = "TIMER4"; 1631 groups = "TIMER4"; 1632 }; 1633 1634 pinctrl_timer5_default: timer5_default { 1635 function = "TIMER5"; 1636 groups = "TIMER5"; 1637 }; 1638 1639 pinctrl_timer6_default: timer6_default { 1640 function = "TIMER6"; 1641 groups = "TIMER6"; 1642 }; 1643 1644 pinctrl_timer7_default: timer7_default { 1645 function = "TIMER7"; 1646 groups = "TIMER7"; 1647 }; 1648 1649 pinctrl_timer8_default: timer8_default { 1650 function = "TIMER8"; 1651 groups = "TIMER8"; 1652 }; 1653 1654 pinctrl_txd1_default: txd1_default { 1655 function = "TXD1"; 1656 groups = "TXD1"; 1657 }; 1658 1659 pinctrl_txd2_default: txd2_default { 1660 function = "TXD2"; 1661 groups = "TXD2"; 1662 }; 1663 1664 pinctrl_txd3_default: txd3_default { 1665 function = "TXD3"; 1666 groups = "TXD3"; 1667 }; 1668 1669 pinctrl_txd4_default: txd4_default { 1670 function = "TXD4"; 1671 groups = "TXD4"; 1672 }; 1673 1674 pinctrl_uart6_default: uart6_default { 1675 function = "UART6"; 1676 groups = "UART6"; 1677 }; 1678 1679 pinctrl_usbcki_default: usbcki_default { 1680 function = "USBCKI"; 1681 groups = "USBCKI"; 1682 }; 1683 1684 pinctrl_usb2ah_default: usb2ah_default { 1685 function = "USB2AH"; 1686 groups = "USB2AH"; 1687 }; 1688 1689 pinctrl_usb11bhid_default: usb11bhid_default { 1690 function = "USB11BHID"; 1691 groups = "USB11BHID"; 1692 }; 1693 1694 pinctrl_usb2bh_default: usb2bh_default { 1695 function = "USB2BH"; 1696 groups = "USB2BH"; 1697 }; 1698 1699 pinctrl_vgabiosrom_default: vgabiosrom_default { 1700 function = "VGABIOSROM"; 1701 groups = "VGABIOSROM"; 1702 }; 1703 1704 pinctrl_vgahs_default: vgahs_default { 1705 function = "VGAHS"; 1706 groups = "VGAHS"; 1707 }; 1708 1709 pinctrl_vgavs_default: vgavs_default { 1710 function = "VGAVS"; 1711 groups = "VGAVS"; 1712 }; 1713 1714 pinctrl_vpi24_default: vpi24_default { 1715 function = "VPI24"; 1716 groups = "VPI24"; 1717 }; 1718 1719 pinctrl_vpo_default: vpo_default { 1720 function = "VPO"; 1721 groups = "VPO"; 1722 }; 1723 1724 pinctrl_wdtrst1_default: wdtrst1_default { 1725 function = "WDTRST1"; 1726 groups = "WDTRST1"; 1727 }; 1728 1729 pinctrl_wdtrst2_default: wdtrst2_default { 1730 function = "WDTRST2"; 1731 groups = "WDTRST2"; 1732 }; 1733}; 1734