1// SPDX-License-Identifier: GPL-2.0+ 2#include <dt-bindings/interrupt-controller/arm-gic.h> 3#include <dt-bindings/gpio/aspeed-gpio.h> 4#include "skeleton.dtsi" 5 6/ { 7 model = "Aspeed BMC"; 8 compatible = "aspeed,ast2600"; 9 #address-cells = <1>; 10 #size-cells = <1>; 11 interrupt-parent = <&gic>; 12 13 aliases { 14 i2c0 = &i2c0; 15 i2c1 = &i2c1; 16 i2c2 = &i2c2; 17 i2c3 = &i2c3; 18 i2c4 = &i2c4; 19 i2c5 = &i2c5; 20 i2c6 = &i2c6; 21 i2c7 = &i2c7; 22 i2c8 = &i2c8; 23 i2c9 = &i2c9; 24 i2c10 = &i2c10; 25 i2c11 = &i2c11; 26 i2c12 = &i2c12; 27 i2c13 = &i2c13; 28 i2c14 = &i2c14; 29 i2c15 = &i2c15; 30 serial0 = &uart1; 31 serial1 = &uart2; 32 serial2 = &uart3; 33 serial3 = &uart4; 34 serial4 = &uart5; 35 serial5 = &uart6; 36 serial6 = &uart7; 37 serial7 = &uart8; 38 serial8 = &uart9; 39 serial9 = &uart10; 40 serial10 = &uart11; 41 serial11 = &uart12; 42 serial12 = &uart13; 43 }; 44 45 cpus { 46 #address-cells = <1>; 47 #size-cells = <0>; 48 enable-method = "aspeed,ast2600-smp"; 49 50 cpu@0 { 51 compatible = "arm,cortex-a7"; 52 device_type = "cpu"; 53 reg = <0>; 54 clock-frequency = <48000000>; 55 }; 56 57 cpu@1 { 58 compatible = "arm,cortex-a7"; 59 device_type = "cpu"; 60 reg = <1>; 61 clock-frequency = <48000000>; 62 }; 63 64 }; 65 66 timer { 67 compatible = "arm,armv7-timer"; 68 interrupt-parent = <&gic>; 69 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 70 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 71 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 72 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 73 clock-frequency = <25000000>; 74 }; 75 76 memory@80000000 { 77 device_type = "memory"; 78 reg = <0x80000000 0>; 79 }; 80 81 reserved-memory { 82 #address-cells = <1>; 83 #size-cells = <1>; 84 ranges; 85 86 gfx_memory: framebuffer { 87 size = <0x01000000>; 88 alignment = <0x01000000>; 89 compatible = "shared-dma-pool"; 90 reusable; 91 }; 92 93 video_memory: video { 94 size = <0x04000000>; 95 alignment = <0x01000000>; 96 compatible = "shared-dma-pool"; 97 no-map; 98 }; 99 }; 100 101 ahb { 102 compatible = "simple-bus"; 103 #address-cells = <1>; 104 #size-cells = <1>; 105 device_type = "soc"; 106 ranges; 107 108 gic: interrupt-controller@40461000 { 109 compatible = "arm,cortex-a7-gic"; 110 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 111 #interrupt-cells = <3>; 112 interrupt-controller; 113 interrupt-parent = <&gic>; 114 reg = <0x40461000 0x1000>, 115 <0x40462000 0x1000>, 116 <0x40464000 0x2000>, 117 <0x40466000 0x2000>; 118 }; 119 120 ahbc: ahbc@1e600000 { 121 compatible = "aspeed,aspeed-ahbc"; 122 reg = < 0x1e600000 0x100>; 123 }; 124 125 fmc: flash-controller@1e620000 { 126 reg = < 0x1e620000 0xc4 127 0x20000000 0x10000000 >; 128 #address-cells = <1>; 129 #size-cells = <0>; 130 compatible = "aspeed,ast2600-fmc"; 131 status = "disabled"; 132 interrupts = <19>; 133 clocks = <&scu ASPEED_CLK_AHB>; 134 flash@0 { 135 reg = < 0 >; 136 compatible = "jedec,spi-nor"; 137 status = "disabled"; 138 }; 139 flash@1 { 140 reg = < 1 >; 141 compatible = "jedec,spi-nor"; 142 status = "disabled"; 143 }; 144 flash@2 { 145 reg = < 2 >; 146 compatible = "jedec,spi-nor"; 147 status = "disabled"; 148 }; 149 }; 150 151 spi1: flash-controller@1e630000 { 152 reg = < 0x1e630000 0xc4 153 0x30000000 0x08000000 >; 154 #address-cells = <1>; 155 #size-cells = <0>; 156 compatible = "aspeed,ast2600-spi"; 157 clocks = <&scu ASPEED_CLK_AHB>; 158 status = "disabled"; 159 flash@0 { 160 reg = < 0 >; 161 compatible = "jedec,spi-nor"; 162 status = "disabled"; 163 }; 164 flash@1 { 165 reg = < 1 >; 166 compatible = "jedec,spi-nor"; 167 status = "disabled"; 168 }; 169 }; 170 171 spi2: flash-controller@1e631000 { 172 reg = < 0x1e631000 0xc4 173 0x38000000 0x08000000 >; 174 #address-cells = <1>; 175 #size-cells = <0>; 176 compatible = "aspeed,ast2600-spi"; 177 clocks = <&scu ASPEED_CLK_AHB>; 178 status = "disabled"; 179 flash@0 { 180 reg = < 0 >; 181 compatible = "jedec,spi-nor"; 182 status = "disabled"; 183 }; 184 flash@1 { 185 reg = < 1 >; 186 compatible = "jedec,spi-nor"; 187 status = "disabled"; 188 }; 189 }; 190 191 edac: sdram@1e6e0000 { 192 compatible = "aspeed,ast2600-sdram-edac"; 193 reg = <0x1e6e0000 0x174>; 194 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 195 }; 196 197 mdio: ethernet@1e650000 { 198 compatible = "aspeed,aspeed-mdio"; 199 reg = <0x1e650000 0x40>; 200 resets = <&rst ASPEED_RESET_MII>; 201 status = "disabled"; 202 }; 203 204 mac0: ftgmac@1e660000 { 205 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 206 reg = <0x1e660000 0x180>, <0x1e650000 0x4>; 207 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 208 clocks = <&scu ASPEED_CLK_GATE_MAC1CLK>; 209 status = "disabled"; 210 }; 211 212#ifndef CONFIG_FPGA_ASPEED 213 mac1: ftgmac@1e680000 { 214 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 215 reg = <0x1e680000 0x180>, <0x1e650008 0x4>; 216 #address-cells = <1>; 217 #size-cells = <0>; 218 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 219 clocks = <&scu ASPEED_CLK_GATE_MAC2CLK>; 220#if 0 221 phy-handle = <&phy0>; 222#endif 223 status = "disabled"; 224 }; 225 226 mac2: ftgmac@1e670000 { 227 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 228 reg = <0x1e670000 0x180>, <0x1e650010 0x4>; 229 #address-cells = <1>; 230 #size-cells = <0>; 231 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 232 clocks = <&scu ASPEED_CLK_GATE_MAC3CLK>; 233#if 0 234 phy-handle = <&phy0>; 235#endif 236 status = "disabled"; 237 }; 238 239 mac3: ftgmac@1e690000 { 240 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 241 reg = <0x1e690000 0x180>, <0x1e650018 0x4>; 242 #address-cells = <1>; 243 #size-cells = <0>; 244 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 245 clocks = <&scu ASPEED_CLK_GATE_MAC4CLK>; 246#if 0 247 phy-handle = <&phy0>; 248#endif 249 status = "disabled"; 250 }; 251#endif 252 253 apb { 254 compatible = "simple-bus"; 255 #address-cells = <1>; 256 #size-cells = <1>; 257 ranges; 258 259 syscon: syscon@1e6e2000 { 260 compatible = "aspeed,g6-scu", "syscon", "simple-mfd"; 261 reg = <0x1e6e2000 0x1000>; 262 #address-cells = <1>; 263 #size-cells = <1>; 264 #clock-cells = <1>; 265 #reset-cells = <1>; 266 ranges = <0 0x1e6e2000 0x1000>; 267 268 pinctrl: pinctrl { 269 compatible = "aspeed,g6-pinctrl"; 270 aspeed,external-nodes = <&gfx &lhc>; 271 272 }; 273 274 vga_scratch: scratch { 275 compatible = "aspeed,bmc-misc"; 276 }; 277 278 scu_ic0: interrupt-controller@0 { 279 #interrupt-cells = <1>; 280 compatible = "aspeed,ast2600-scu-ic"; 281 reg = <0x560 0x10>; 282 interrupt-parent = <&gic>; 283 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 284 interrupt-controller; 285 }; 286 287 scu_ic1: interrupt-controller@1 { 288 #interrupt-cells = <1>; 289 compatible = "aspeed,ast2600-scu-ic"; 290 reg = <0x570 0x10>; 291 interrupt-parent = <&gic>; 292 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 293 interrupt-controller; 294 }; 295 296 }; 297 298 smp-memram@0 { 299 compatible = "aspeed,ast2600-smpmem", "syscon"; 300 reg = <0x1e6e2180 0x40>; 301 }; 302 303 gfx: display@1e6e6000 { 304 compatible = "aspeed,ast2500-gfx", "syscon"; 305 reg = <0x1e6e6000 0x1000>; 306 reg-io-width = <4>; 307 }; 308 309 pcie_bridge: pcie_bridge@0x1e6ed000 { 310 compatible = "aspeed,ast2600-pcie"; 311 reg = <0x1e6ed000 0x100>, <0x60000000 0x20000000>; 312 }; 313 314 sdhci: sdhci@1e740000 { 315 #interrupt-cells = <1>; 316 compatible = "aspeed,aspeed-sdhci-irq", "simple-mfd"; 317 reg = <0x1e740000 0x1000>; 318 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 319 interrupt-controller; 320 clocks = <&scu ASPEED_CLK_GATE_SDCLK>, <&scu ASPEED_CLK_GATE_SDEXTCLK>; 321 clock-names = "ctrlclk", "extclk"; 322 #address-cells = <1>; 323 #size-cells = <1>; 324 ranges = <0x0 0x1e740000 0x1000>; 325 326 sdhci_slot0: sdhci_slot0@100 { 327 compatible = "aspeed,sdhci-ast2600"; 328 reg = <0x100 0x100>; 329 interrupts = <0>; 330 interrupt-parent = <&sdhci>; 331 sdhci,auto-cmd12; 332 clocks = <&scu ASPEED_CLK_SDIO>; 333 pwr-gpios = <&gpio0 ASPEED_GPIO(V, 0) GPIO_ACTIVE_LOW>; 334 pwr-sw-gpios = <&gpio0 ASPEED_GPIO(V, 1) GPIO_ACTIVE_LOW>; 335 status = "disabled"; 336 }; 337 338 sdhci_slot1: sdhci_slot1@200 { 339 compatible = "aspeed,sdhci-ast2600"; 340 reg = <0x200 0x100>; 341 interrupts = <1>; 342 interrupt-parent = <&sdhci>; 343 sdhci,auto-cmd12; 344 clocks = <&scu ASPEED_CLK_SDIO>; 345 pwr-gpios = <&gpio0 ASPEED_GPIO(V, 2) GPIO_ACTIVE_LOW>; 346 pwr-sw-gpios = <&gpio0 ASPEED_GPIO(V, 3) GPIO_ACTIVE_LOW>; 347 status = "disabled"; 348 }; 349 350 }; 351 352 emmc: emmc@1e750000 { 353 #interrupt-cells = <1>; 354 compatible = "aspeed,aspeed-emmc-irq", "simple-mfd"; 355 reg = <0x1e750000 0x1000>; 356 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 357 interrupt-controller; 358 clocks = <&scu ASPEED_CLK_GATE_EMMCCLK>, <&scu ASPEED_CLK_GATE_EMMCEXTCLK>; 359 clock-names = "ctrlclk", "extclk"; 360 #address-cells = <1>; 361 #size-cells = <1>; 362 ranges = <0x0 0x1e750000 0x1000>; 363 364 emmc_slot0: emmc_slot0@100 { 365 compatible = "aspeed,emmc-ast2600"; 366 reg = <0x100 0x100>; 367 interrupts = <0>; 368 interrupt-parent = <&emmc>; 369 clocks = <&scu ASPEED_CLK_EMMC>; 370 status = "disabled"; 371 }; 372 373 }; 374 375 h2x: h2x@1e770000 { 376 compatible = "aspeed,ast2600-h2x"; 377 reg = <0x1e770000 0x100>; 378 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 379 resets = <&rst ASPEED_RESET_H2X>; 380 }; 381 382 gpio0: gpio@1e780000 { 383 compatible = "aspeed,ast2600-gpio"; 384 reg = <0x1e780000 0x1000>; 385 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 386 #gpio-cells = <2>; 387 gpio-controller; 388 interrupt-controller; 389 gpio-ranges = <&pinctrl 0 0 220>; 390 }; 391 392 gpio1: gpio@1e780800 { 393 compatible = "aspeed,ast2600-gpio"; 394 reg = <0x1e780800 0x800>; 395 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 396 #gpio-cells = <2>; 397 gpio-controller; 398 interrupt-controller; 399 gpio-ranges = <&pinctrl 0 0 208>; 400 }; 401 402 uart1: serial@1e783000 { 403 compatible = "ns16550a"; 404 reg = <0x1e783000 0x20>; 405 reg-shift = <2>; 406 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 407 clocks = <&scu ASPEED_CLK_GATE_UART1CLK>; 408 clock-frequency = <1846154>; 409 no-loopback-test; 410 status = "disabled"; 411 }; 412 413 uart5: serial@1e784000 { 414 compatible = "ns16550a"; 415 reg = <0x1e784000 0x1000>; 416 reg-shift = <2>; 417 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 418 clocks = <&scu ASPEED_CLK_GATE_UART5CLK>; 419 clock-frequency = <1846154>; 420 no-loopback-test; 421 status = "disabled"; 422 }; 423 424 wdt1: watchdog@1e785000 { 425 compatible = "aspeed,ast2600-wdt"; 426 reg = <0x1e785000 0x40>; 427 }; 428 429 wdt2: watchdog@1e785040 { 430 compatible = "aspeed,ast2600-wdt"; 431 reg = <0x1e785040 0x40>; 432 }; 433 434 wdt3: watchdog@1e785080 { 435 compatible = "aspeed,ast2600-wdt"; 436 reg = <0x1e785080 0x40>; 437 }; 438 439 wdt4: watchdog@1e7850C0 { 440 compatible = "aspeed,ast2600-wdt"; 441 reg = <0x1e7850C0 0x40>; 442 }; 443 444 lpc: lpc@1e789000 { 445 compatible = "aspeed,ast-lpc", "simple-mfd", "syscon"; 446 reg = <0x1e789000 0x200>; 447 448 #address-cells = <1>; 449 #size-cells = <1>; 450 ranges = <0x0 0x1e789000 0x1000>; 451 452 lpc_bmc: lpc-bmc@0 { 453 compatible = "aspeed,ast2600-lpc-bmc", "simple-mfd", "syscon"; 454 reg = <0x0 0x80>; 455 reg-io-width = <4>; 456 #address-cells = <1>; 457 #size-cells = <1>; 458 ranges = <0x0 0x0 0x80>; 459 460 kcs1: kcs1@0 { 461 compatible = "aspeed,ast2600-kcs-bmc"; 462 reg = <0x0 0x80>; 463 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 464 kcs_chan = <1>; 465 kcs_addr = <0xCA0>; 466 status = "disabled"; 467 }; 468 469 kcs2: kcs2@0 { 470 compatible = "aspeed,ast2600-kcs-bmc"; 471 reg = <0x0 0x80>; 472 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 473 kcs_chan = <2>; 474 kcs_addr = <0xCA8>; 475 status = "disabled"; 476 }; 477 478 kcs3: kcs3@0 { 479 compatible = "aspeed,ast2600-kcs-bmc"; 480 reg = <0x0 0x80>; 481 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 482 kcs_chan = <3>; 483 kcs_addr = <0xCA2>; 484 }; 485 486 kcs4: kcs4@0 { 487 compatible = "aspeed,ast2600-kcs-bmc"; 488 reg = <0x0 0x120>; 489 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 490 kcs_chan = <4>; 491 kcs_addr = <0xCA4>; 492 status = "disabled"; 493 }; 494 495 }; 496 497 lpc_host: lpc-host@80 { 498 compatible = "aspeed,ast2600-lpc-host", "simple-mfd", "syscon"; 499 reg = <0x80 0x1e0>; 500 reg-io-width = <4>; 501 502 #address-cells = <1>; 503 #size-cells = <1>; 504 ranges = <0x0 0x80 0x1e0>; 505 506 lpc_ctrl: lpc-ctrl@0 { 507 compatible = "aspeed,ast2600-lpc-ctrl"; 508 reg = <0x0 0x80>; 509 status = "disabled"; 510 }; 511 512 lpc_snoop: lpc-snoop@0 { 513 compatible = "aspeed,ast2600-lpc-snoop"; 514 reg = <0x0 0x80>; 515 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 516 snoop-ports = <0x80>; 517 status = "disabled"; 518 }; 519 520 lhc: lhc@20 { 521 compatible = "aspeed,ast2600-lhc"; 522 reg = <0x20 0x24 0x48 0x8>; 523 }; 524 525 lpc_reset: reset-controller@18 { 526 compatible = "aspeed,ast2600-lpc-reset"; 527 reg = <0x18 0x4>; 528 #reset-cells = <1>; 529 status = "disabled"; 530 }; 531 532 ibt: ibt@c0 { 533 compatible = "aspeed,ast2600-ibt-bmc"; 534 reg = <0xc0 0x18>; 535 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 536 status = "disabled"; 537 }; 538 539 sio_regs: regs { 540 compatible = "aspeed,bmc-misc"; 541 }; 542 543 mbox: mbox@180 { 544 compatible = "aspeed,ast2600-mbox"; 545 reg = <0x180 0x5c>; 546 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 547 #mbox-cells = <1>; 548 status = "disabled"; 549 }; 550 }; 551 }; 552 553 uart2: serial@1e78d000 { 554 compatible = "ns16550a"; 555 reg = <0x1e78d000 0x20>; 556 reg-shift = <2>; 557 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 558 clocks = <&scu ASPEED_CLK_GATE_UART2CLK>; 559 clock-frequency = <1846154>; 560 no-loopback-test; 561 status = "disabled"; 562 }; 563 564 uart3: serial@1e78e000 { 565 compatible = "ns16550a"; 566 reg = <0x1e78e000 0x20>; 567 reg-shift = <2>; 568 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 569 clocks = <&scu ASPEED_CLK_GATE_UART3CLK>; 570 clock-frequency = <1846154>; 571 no-loopback-test; 572 status = "disabled"; 573 }; 574 575 uart4: serial@1e78f000 { 576 compatible = "ns16550a"; 577 reg = <0x1e78f000 0x20>; 578 reg-shift = <2>; 579 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 580 clocks = <&scu ASPEED_CLK_GATE_UART4CLK>; 581 clock-frequency = <1846154>; 582 no-loopback-test; 583 status = "disabled"; 584 }; 585 586 i2c: bus@1e78a000 { 587 compatible = "simple-bus"; 588 #address-cells = <1>; 589 #size-cells = <1>; 590 ranges = <0 0x1e78a000 0x1000>; 591 }; 592 593 uart6: serial@1e790000 { 594 compatible = "ns16550a"; 595 reg = <0x1e790000 0x20>; 596 reg-shift = <2>; 597 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 598 clocks = <&scu ASPEED_CLK_GATE_UART6CLK>; 599 clock-frequency = <1846154>; 600 no-loopback-test; 601 status = "disabled"; 602 }; 603 604 uart7: serial@1e790100 { 605 compatible = "ns16550a"; 606 reg = <0x1e790100 0x20>; 607 reg-shift = <2>; 608 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 609 clocks = <&scu ASPEED_CLK_GATE_UART7CLK>; 610 clock-frequency = <1846154>; 611 no-loopback-test; 612 status = "disabled"; 613 }; 614 615 uart8: serial@1e790200 { 616 compatible = "ns16550a"; 617 reg = <0x1e790200 0x20>; 618 reg-shift = <2>; 619 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 620 clocks = <&scu ASPEED_CLK_GATE_UART8CLK>; 621 clock-frequency = <1846154>; 622 no-loopback-test; 623 status = "disabled"; 624 }; 625 626 uart9: serial@1e790300 { 627 compatible = "ns16550a"; 628 reg = <0x1e790300 0x20>; 629 reg-shift = <2>; 630 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 631 clocks = <&scu ASPEED_CLK_GATE_UART9CLK>; 632 clock-frequency = <1846154>; 633 no-loopback-test; 634 status = "disabled"; 635 }; 636 637 uart10: serial@1e790400 { 638 compatible = "ns16550a"; 639 reg = <0x1e790400 0x20>; 640 reg-shift = <2>; 641 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 642 clocks = <&scu ASPEED_CLK_GATE_UART10CLK>; 643 clock-frequency = <1846154>; 644 no-loopback-test; 645 status = "disabled"; 646 }; 647 648 uart11: serial@1e790500 { 649 compatible = "ns16550a"; 650 reg = <0x1e790400 0x20>; 651 reg-shift = <2>; 652 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 653 clocks = <&scu ASPEED_CLK_GATE_UART11CLK>; 654 clock-frequency = <1846154>; 655 no-loopback-test; 656 status = "disabled"; 657 }; 658 659 uart12: serial@1e790600 { 660 compatible = "ns16550a"; 661 reg = <0x1e790600 0x20>; 662 reg-shift = <2>; 663 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 664 clocks = <&scu ASPEED_CLK_GATE_UART12CLK>; 665 clock-frequency = <1846154>; 666 no-loopback-test; 667 status = "disabled"; 668 }; 669 670 uart13: serial@1e790700 { 671 compatible = "ns16550a"; 672 reg = <0x1e790700 0x20>; 673 reg-shift = <2>; 674 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 675 clocks = <&scu ASPEED_CLK_GATE_UART13CLK>; 676 clock-frequency = <1846154>; 677 no-loopback-test; 678 status = "disabled"; 679 }; 680 681 682 683 }; 684 685 }; 686 687}; 688 689&i2c { 690 i2cglobal: i2cg@00 { 691 compatible = "aspeed,ast2600-i2c-global"; 692 reg = <0x0 0x40>; 693 resets = <&rst ASPEED_RESET_I2C>; 694#if 0 695 new-mode; 696#endif 697 }; 698 699 i2c0: i2c@80 { 700 #address-cells = <1>; 701 #size-cells = <0>; 702 #interrupt-cells = <1>; 703 704 reg = <0x80 0x80 0xC00 0x20>; 705 compatible = "aspeed,ast2600-i2c-bus"; 706 bus-frequency = <100000>; 707 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 708 clocks = <&scu ASPEED_CLK_APB2>; 709 status = "disabled"; 710 }; 711 712 i2c1: i2c@100 { 713 #address-cells = <1>; 714 #size-cells = <0>; 715 #interrupt-cells = <1>; 716 717 reg = <0x100 0x80 0xC20 0x20>; 718 compatible = "aspeed,ast2600-i2c-bus"; 719 bus-frequency = <100000>; 720 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 721 clocks = <&scu ASPEED_CLK_APB2>; 722 status = "disabled"; 723 }; 724 725 i2c2: i2c@180 { 726 #address-cells = <1>; 727 #size-cells = <0>; 728 #interrupt-cells = <1>; 729 730 reg = <0x180 0x80 0xC40 0x20>; 731 compatible = "aspeed,ast2600-i2c-bus"; 732 bus-frequency = <100000>; 733 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 734 clocks = <&scu ASPEED_CLK_APB2>; 735 }; 736 737 i2c3: i2c@200 { 738 #address-cells = <1>; 739 #size-cells = <0>; 740 #interrupt-cells = <1>; 741 742 reg = <0x200 0x40 0xC60 0x20>; 743 compatible = "aspeed,ast2600-i2c-bus"; 744 bus-frequency = <100000>; 745 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 746 clocks = <&scu ASPEED_CLK_APB2>; 747 }; 748 749 i2c4: i2c@280 { 750 #address-cells = <1>; 751 #size-cells = <0>; 752 #interrupt-cells = <1>; 753 754 reg = <0x280 0x80 0xC80 0x20>; 755 compatible = "aspeed,ast2600-i2c-bus"; 756 bus-frequency = <100000>; 757 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 758 clocks = <&scu ASPEED_CLK_APB2>; 759 }; 760 761 i2c5: i2c@300 { 762 #address-cells = <1>; 763 #size-cells = <0>; 764 #interrupt-cells = <1>; 765 766 reg = <0x300 0x40 0xCA0 0x20>; 767 compatible = "aspeed,ast2600-i2c-bus"; 768 bus-frequency = <100000>; 769 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 770 clocks = <&scu ASPEED_CLK_APB2>; 771 }; 772 773 i2c6: i2c@380 { 774 #address-cells = <1>; 775 #size-cells = <0>; 776 #interrupt-cells = <1>; 777 778 reg = <0x380 0x80 0xCC0 0x20>; 779 compatible = "aspeed,ast2600-i2c-bus"; 780 bus-frequency = <100000>; 781 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 782 clocks = <&scu ASPEED_CLK_APB2>; 783 }; 784 785 i2c7: i2c@400 { 786 #address-cells = <1>; 787 #size-cells = <0>; 788 #interrupt-cells = <1>; 789 790 reg = <0x400 0x80 0xCE0 0x20>; 791 compatible = "aspeed,ast2600-i2c-bus"; 792 bus-frequency = <100000>; 793 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 794 clocks = <&scu ASPEED_CLK_APB2>; 795 }; 796 797 i2c8: i2c@480 { 798 #address-cells = <1>; 799 #size-cells = <0>; 800 #interrupt-cells = <1>; 801 802 reg = <0x480 0x80 0xD00 0x20>; 803 compatible = "aspeed,ast2600-i2c-bus"; 804 bus-frequency = <100000>; 805 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 806 clocks = <&scu ASPEED_CLK_APB2>; 807 }; 808 809 i2c9: i2c@500 { 810 #address-cells = <1>; 811 #size-cells = <0>; 812 #interrupt-cells = <1>; 813 814 reg = <0x500 0x80 0xD20 0x20>; 815 compatible = "aspeed,ast2600-i2c-bus"; 816 bus-frequency = <100000>; 817 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 818 clocks = <&scu ASPEED_CLK_APB2>; 819 status = "disabled"; 820 }; 821 822 i2c10: i2c@580 { 823 #address-cells = <1>; 824 #size-cells = <0>; 825 #interrupt-cells = <1>; 826 827 reg = <0x580 0x80 0xD40 0x20>; 828 compatible = "aspeed,ast2600-i2c-bus"; 829 bus-frequency = <100000>; 830 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 831 clocks = <&scu ASPEED_CLK_APB2>; 832 status = "disabled"; 833 }; 834 835 i2c11: i2c@600 { 836 #address-cells = <1>; 837 #size-cells = <0>; 838 #interrupt-cells = <1>; 839 840 reg = <0x600 0x80 0xD60 0x20>; 841 compatible = "aspeed,ast2600-i2c-bus"; 842 bus-frequency = <100000>; 843 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 844 clocks = <&scu ASPEED_CLK_APB2>; 845 status = "disabled"; 846 }; 847 848 i2c12: i2c@680 { 849 #address-cells = <1>; 850 #size-cells = <0>; 851 #interrupt-cells = <1>; 852 853 reg = <0x680 0x80 0xD80 0x20>; 854 compatible = "aspeed,ast2600-i2c-bus"; 855 bus-frequency = <100000>; 856 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 857 clocks = <&scu ASPEED_CLK_APB2>; 858 status = "disabled"; 859 }; 860 861 i2c13: i2c@700 { 862 #address-cells = <1>; 863 #size-cells = <0>; 864 #interrupt-cells = <1>; 865 866 reg = <0x700 0x80 0xDA0 0x20>; 867 compatible = "aspeed,ast2600-i2c-bus"; 868 bus-frequency = <100000>; 869 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 870 clocks = <&scu ASPEED_CLK_APB2>; 871 status = "disabled"; 872 }; 873 874 i2c14: i2c@780 { 875 #address-cells = <1>; 876 #size-cells = <0>; 877 #interrupt-cells = <1>; 878 879 reg = <0x780 0x80 0xDC0 0x20>; 880 compatible = "aspeed,ast2600-i2c-bus"; 881 bus-frequency = <100000>; 882 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 883 clocks = <&scu ASPEED_CLK_APB2>; 884 status = "disabled"; 885 }; 886 887 i2c15: i2c@800 { 888 #address-cells = <1>; 889 #size-cells = <0>; 890 #interrupt-cells = <1>; 891 892 reg = <0x800 0x80 0xDE0 0x20>; 893 compatible = "aspeed,ast2600-i2c-bus"; 894 bus-frequency = <100000>; 895 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 896 clocks = <&scu ASPEED_CLK_APB2>; 897 status = "disabled"; 898 }; 899 900}; 901 902&pinctrl { 903 pinctrl_acpi_default: acpi_default { 904 function = "ACPI"; 905 groups = "ACPI"; 906 }; 907 908 pinctrl_adc0_default: adc0_default { 909 function = "ADC0"; 910 groups = "ADC0"; 911 }; 912 913 pinctrl_adc1_default: adc1_default { 914 function = "ADC1"; 915 groups = "ADC1"; 916 }; 917 918 pinctrl_adc10_default: adc10_default { 919 function = "ADC10"; 920 groups = "ADC10"; 921 }; 922 923 pinctrl_adc11_default: adc11_default { 924 function = "ADC11"; 925 groups = "ADC11"; 926 }; 927 928 pinctrl_adc12_default: adc12_default { 929 function = "ADC12"; 930 groups = "ADC12"; 931 }; 932 933 pinctrl_adc13_default: adc13_default { 934 function = "ADC13"; 935 groups = "ADC13"; 936 }; 937 938 pinctrl_adc14_default: adc14_default { 939 function = "ADC14"; 940 groups = "ADC14"; 941 }; 942 943 pinctrl_adc15_default: adc15_default { 944 function = "ADC15"; 945 groups = "ADC15"; 946 }; 947 948 pinctrl_adc2_default: adc2_default { 949 function = "ADC2"; 950 groups = "ADC2"; 951 }; 952 953 pinctrl_adc3_default: adc3_default { 954 function = "ADC3"; 955 groups = "ADC3"; 956 }; 957 958 pinctrl_adc4_default: adc4_default { 959 function = "ADC4"; 960 groups = "ADC4"; 961 }; 962 963 pinctrl_adc5_default: adc5_default { 964 function = "ADC5"; 965 groups = "ADC5"; 966 }; 967 968 pinctrl_adc6_default: adc6_default { 969 function = "ADC6"; 970 groups = "ADC6"; 971 }; 972 973 pinctrl_adc7_default: adc7_default { 974 function = "ADC7"; 975 groups = "ADC7"; 976 }; 977 978 pinctrl_adc8_default: adc8_default { 979 function = "ADC8"; 980 groups = "ADC8"; 981 }; 982 983 pinctrl_adc9_default: adc9_default { 984 function = "ADC9"; 985 groups = "ADC9"; 986 }; 987 988 pinctrl_bmcint_default: bmcint_default { 989 function = "BMCINT"; 990 groups = "BMCINT"; 991 }; 992 993 pinctrl_ddcclk_default: ddcclk_default { 994 function = "DDCCLK"; 995 groups = "DDCCLK"; 996 }; 997 998 pinctrl_ddcdat_default: ddcdat_default { 999 function = "DDCDAT"; 1000 groups = "DDCDAT"; 1001 }; 1002 1003 pinctrl_espi_default: espi_default { 1004 function = "ESPI"; 1005 groups = "ESPI"; 1006 }; 1007 1008 pinctrl_fwspics1_default: fwspics1_default { 1009 function = "FWSPICS1"; 1010 groups = "FWSPICS1"; 1011 }; 1012 1013 pinctrl_fwspics2_default: fwspics2_default { 1014 function = "FWSPICS2"; 1015 groups = "FWSPICS2"; 1016 }; 1017 1018 pinctrl_gpid0_default: gpid0_default { 1019 function = "GPID0"; 1020 groups = "GPID0"; 1021 }; 1022 1023 pinctrl_gpid2_default: gpid2_default { 1024 function = "GPID2"; 1025 groups = "GPID2"; 1026 }; 1027 1028 pinctrl_gpid4_default: gpid4_default { 1029 function = "GPID4"; 1030 groups = "GPID4"; 1031 }; 1032 1033 pinctrl_gpid6_default: gpid6_default { 1034 function = "GPID6"; 1035 groups = "GPID6"; 1036 }; 1037 1038 pinctrl_gpie0_default: gpie0_default { 1039 function = "GPIE0"; 1040 groups = "GPIE0"; 1041 }; 1042 1043 pinctrl_gpie2_default: gpie2_default { 1044 function = "GPIE2"; 1045 groups = "GPIE2"; 1046 }; 1047 1048 pinctrl_gpie4_default: gpie4_default { 1049 function = "GPIE4"; 1050 groups = "GPIE4"; 1051 }; 1052 1053 pinctrl_gpie6_default: gpie6_default { 1054 function = "GPIE6"; 1055 groups = "GPIE6"; 1056 }; 1057 1058 pinctrl_i2c10_default: i2c10_default { 1059 function = "I2C10"; 1060 groups = "I2C10"; 1061 }; 1062 1063 pinctrl_i2c11_default: i2c11_default { 1064 function = "I2C11"; 1065 groups = "I2C11"; 1066 }; 1067 1068 pinctrl_i2c12_default: i2c12_default { 1069 function = "I2C12"; 1070 groups = "I2C12"; 1071 }; 1072 1073 pinctrl_i2c13_default: i2c13_default { 1074 function = "I2C13"; 1075 groups = "I2C13"; 1076 }; 1077 1078 pinctrl_i2c14_default: i2c14_default { 1079 function = "I2C14"; 1080 groups = "I2C14"; 1081 }; 1082 1083 pinctrl_i2c3_default: i2c3_default { 1084 function = "I2C3"; 1085 groups = "I2C3"; 1086 }; 1087 1088 pinctrl_i2c4_default: i2c4_default { 1089 function = "I2C4"; 1090 groups = "I2C4"; 1091 }; 1092 1093 pinctrl_i2c5_default: i2c5_default { 1094 function = "I2C5"; 1095 groups = "I2C5"; 1096 }; 1097 1098 pinctrl_i2c6_default: i2c6_default { 1099 function = "I2C6"; 1100 groups = "I2C6"; 1101 }; 1102 1103 pinctrl_i2c7_default: i2c7_default { 1104 function = "I2C7"; 1105 groups = "I2C7"; 1106 }; 1107 1108 pinctrl_i2c8_default: i2c8_default { 1109 function = "I2C8"; 1110 groups = "I2C8"; 1111 }; 1112 1113 pinctrl_i2c9_default: i2c9_default { 1114 function = "I2C9"; 1115 groups = "I2C9"; 1116 }; 1117 1118 pinctrl_lad0_default: lad0_default { 1119 function = "LAD0"; 1120 groups = "LAD0"; 1121 }; 1122 1123 pinctrl_lad1_default: lad1_default { 1124 function = "LAD1"; 1125 groups = "LAD1"; 1126 }; 1127 1128 pinctrl_lad2_default: lad2_default { 1129 function = "LAD2"; 1130 groups = "LAD2"; 1131 }; 1132 1133 pinctrl_lad3_default: lad3_default { 1134 function = "LAD3"; 1135 groups = "LAD3"; 1136 }; 1137 1138 pinctrl_lclk_default: lclk_default { 1139 function = "LCLK"; 1140 groups = "LCLK"; 1141 }; 1142 1143 pinctrl_lframe_default: lframe_default { 1144 function = "LFRAME"; 1145 groups = "LFRAME"; 1146 }; 1147 1148 pinctrl_lpchc_default: lpchc_default { 1149 function = "LPCHC"; 1150 groups = "LPCHC"; 1151 }; 1152 1153 pinctrl_lpcpd_default: lpcpd_default { 1154 function = "LPCPD"; 1155 groups = "LPCPD"; 1156 }; 1157 1158 pinctrl_lpcplus_default: lpcplus_default { 1159 function = "LPCPLUS"; 1160 groups = "LPCPLUS"; 1161 }; 1162 1163 pinctrl_lpcpme_default: lpcpme_default { 1164 function = "LPCPME"; 1165 groups = "LPCPME"; 1166 }; 1167 1168 pinctrl_lpcrst_default: lpcrst_default { 1169 function = "LPCRST"; 1170 groups = "LPCRST"; 1171 }; 1172 1173 pinctrl_lpcsmi_default: lpcsmi_default { 1174 function = "LPCSMI"; 1175 groups = "LPCSMI"; 1176 }; 1177 1178 pinctrl_lsirq_default: lsirq_default { 1179 function = "LSIRQ"; 1180 groups = "LSIRQ"; 1181 }; 1182 1183 pinctrl_mac1link_default: mac1link_default { 1184 function = "MAC1LINK"; 1185 groups = "MAC1LINK"; 1186 }; 1187 1188 pinctrl_mac2link_default: mac2link_default { 1189 function = "MAC2LINK"; 1190 groups = "MAC2LINK"; 1191 }; 1192 1193 pinctrl_mac3link_default: mac3link_default { 1194 function = "MAC3LINK"; 1195 groups = "MAC3LINK"; 1196 }; 1197 1198 pinctrl_mac4link_default: mac4link_default { 1199 function = "MAC4LINK"; 1200 groups = "MAC4LINK"; 1201 }; 1202 1203 pinctrl_mdio1_default: mdio1_default { 1204 function = "MDIO1"; 1205 groups = "MDIO1"; 1206 }; 1207 1208 pinctrl_mdio2_default: mdio2_default { 1209 function = "MDIO2"; 1210 groups = "MDIO2"; 1211 }; 1212 1213 pinctrl_mdio3_default: mdio3_default { 1214 function = "MDIO3"; 1215 groups = "MDIO3"; 1216 }; 1217 1218 pinctrl_mdio4_default: mdio4_default { 1219 function = "MDIO4"; 1220 groups = "MDIO4"; 1221 }; 1222 1223 pinctrl_ncts1_default: ncts1_default { 1224 function = "NCTS1"; 1225 groups = "NCTS1"; 1226 }; 1227 1228 pinctrl_ncts2_default: ncts2_default { 1229 function = "NCTS2"; 1230 groups = "NCTS2"; 1231 }; 1232 1233 pinctrl_ncts3_default: ncts3_default { 1234 function = "NCTS3"; 1235 groups = "NCTS3"; 1236 }; 1237 1238 pinctrl_ncts4_default: ncts4_default { 1239 function = "NCTS4"; 1240 groups = "NCTS4"; 1241 }; 1242 1243 pinctrl_ndcd1_default: ndcd1_default { 1244 function = "NDCD1"; 1245 groups = "NDCD1"; 1246 }; 1247 1248 pinctrl_ndcd2_default: ndcd2_default { 1249 function = "NDCD2"; 1250 groups = "NDCD2"; 1251 }; 1252 1253 pinctrl_ndcd3_default: ndcd3_default { 1254 function = "NDCD3"; 1255 groups = "NDCD3"; 1256 }; 1257 1258 pinctrl_ndcd4_default: ndcd4_default { 1259 function = "NDCD4"; 1260 groups = "NDCD4"; 1261 }; 1262 1263 pinctrl_ndsr1_default: ndsr1_default { 1264 function = "NDSR1"; 1265 groups = "NDSR1"; 1266 }; 1267 1268 pinctrl_ndsr2_default: ndsr2_default { 1269 function = "NDSR2"; 1270 groups = "NDSR2"; 1271 }; 1272 1273 pinctrl_ndsr3_default: ndsr3_default { 1274 function = "NDSR3"; 1275 groups = "NDSR3"; 1276 }; 1277 1278 pinctrl_ndsr4_default: ndsr4_default { 1279 function = "NDSR4"; 1280 groups = "NDSR4"; 1281 }; 1282 1283 pinctrl_ndtr1_default: ndtr1_default { 1284 function = "NDTR1"; 1285 groups = "NDTR1"; 1286 }; 1287 1288 pinctrl_ndtr2_default: ndtr2_default { 1289 function = "NDTR2"; 1290 groups = "NDTR2"; 1291 }; 1292 1293 pinctrl_ndtr3_default: ndtr3_default { 1294 function = "NDTR3"; 1295 groups = "NDTR3"; 1296 }; 1297 1298 pinctrl_ndtr4_default: ndtr4_default { 1299 function = "NDTR4"; 1300 groups = "NDTR4"; 1301 }; 1302 1303 pinctrl_nri1_default: nri1_default { 1304 function = "NRI1"; 1305 groups = "NRI1"; 1306 }; 1307 1308 pinctrl_nri2_default: nri2_default { 1309 function = "NRI2"; 1310 groups = "NRI2"; 1311 }; 1312 1313 pinctrl_nri3_default: nri3_default { 1314 function = "NRI3"; 1315 groups = "NRI3"; 1316 }; 1317 1318 pinctrl_nri4_default: nri4_default { 1319 function = "NRI4"; 1320 groups = "NRI4"; 1321 }; 1322 1323 pinctrl_nrts1_default: nrts1_default { 1324 function = "NRTS1"; 1325 groups = "NRTS1"; 1326 }; 1327 1328 pinctrl_nrts2_default: nrts2_default { 1329 function = "NRTS2"; 1330 groups = "NRTS2"; 1331 }; 1332 1333 pinctrl_nrts3_default: nrts3_default { 1334 function = "NRTS3"; 1335 groups = "NRTS3"; 1336 }; 1337 1338 pinctrl_nrts4_default: nrts4_default { 1339 function = "NRTS4"; 1340 groups = "NRTS4"; 1341 }; 1342 1343 pinctrl_oscclk_default: oscclk_default { 1344 function = "OSCCLK"; 1345 groups = "OSCCLK"; 1346 }; 1347 1348 pinctrl_pewake_default: pewake_default { 1349 function = "PEWAKE"; 1350 groups = "PEWAKE"; 1351 }; 1352 1353 pinctrl_pnor_default: pnor_default { 1354 function = "PNOR"; 1355 groups = "PNOR"; 1356 }; 1357 1358 pinctrl_pwm0_default: pwm0_default { 1359 function = "PWM0"; 1360 groups = "PWM0"; 1361 }; 1362 1363 pinctrl_pwm1_default: pwm1_default { 1364 function = "PWM1"; 1365 groups = "PWM1"; 1366 }; 1367 1368 pinctrl_pwm2_default: pwm2_default { 1369 function = "PWM2"; 1370 groups = "PWM2"; 1371 }; 1372 1373 pinctrl_pwm3_default: pwm3_default { 1374 function = "PWM3"; 1375 groups = "PWM3"; 1376 }; 1377 1378 pinctrl_pwm4_default: pwm4_default { 1379 function = "PWM4"; 1380 groups = "PWM4"; 1381 }; 1382 1383 pinctrl_pwm5_default: pwm5_default { 1384 function = "PWM5"; 1385 groups = "PWM5"; 1386 }; 1387 1388 pinctrl_pwm6_default: pwm6_default { 1389 function = "PWM6"; 1390 groups = "PWM6"; 1391 }; 1392 1393 pinctrl_pwm7_default: pwm7_default { 1394 function = "PWM7"; 1395 groups = "PWM7"; 1396 }; 1397 1398 pinctrl_rgmii1_default: rgmii1_default { 1399 function = "RGMII1"; 1400 groups = "RGMII1"; 1401 }; 1402 1403 pinctrl_rgmii2_default: rgmii2_default { 1404 function = "RGMII2"; 1405 groups = "RGMII2"; 1406 }; 1407 1408 pinctrl_rmii1_default: rmii1_default { 1409 function = "RMII1"; 1410 groups = "RMII1"; 1411 }; 1412 1413 pinctrl_rmii2_default: rmii2_default { 1414 function = "RMII2"; 1415 groups = "RMII2"; 1416 }; 1417 1418 pinctrl_rxd1_default: rxd1_default { 1419 function = "RXD1"; 1420 groups = "RXD1"; 1421 }; 1422 1423 pinctrl_rxd2_default: rxd2_default { 1424 function = "RXD2"; 1425 groups = "RXD2"; 1426 }; 1427 1428 pinctrl_rxd3_default: rxd3_default { 1429 function = "RXD3"; 1430 groups = "RXD3"; 1431 }; 1432 1433 pinctrl_rxd4_default: rxd4_default { 1434 function = "RXD4"; 1435 groups = "RXD4"; 1436 }; 1437 1438 pinctrl_salt1_default: salt1_default { 1439 function = "SALT1"; 1440 groups = "SALT1"; 1441 }; 1442 1443 pinctrl_salt10_default: salt10_default { 1444 function = "SALT10"; 1445 groups = "SALT10"; 1446 }; 1447 1448 pinctrl_salt11_default: salt11_default { 1449 function = "SALT11"; 1450 groups = "SALT11"; 1451 }; 1452 1453 pinctrl_salt12_default: salt12_default { 1454 function = "SALT12"; 1455 groups = "SALT12"; 1456 }; 1457 1458 pinctrl_salt13_default: salt13_default { 1459 function = "SALT13"; 1460 groups = "SALT13"; 1461 }; 1462 1463 pinctrl_salt14_default: salt14_default { 1464 function = "SALT14"; 1465 groups = "SALT14"; 1466 }; 1467 1468 pinctrl_salt2_default: salt2_default { 1469 function = "SALT2"; 1470 groups = "SALT2"; 1471 }; 1472 1473 pinctrl_salt3_default: salt3_default { 1474 function = "SALT3"; 1475 groups = "SALT3"; 1476 }; 1477 1478 pinctrl_salt4_default: salt4_default { 1479 function = "SALT4"; 1480 groups = "SALT4"; 1481 }; 1482 1483 pinctrl_salt5_default: salt5_default { 1484 function = "SALT5"; 1485 groups = "SALT5"; 1486 }; 1487 1488 pinctrl_salt6_default: salt6_default { 1489 function = "SALT6"; 1490 groups = "SALT6"; 1491 }; 1492 1493 pinctrl_salt7_default: salt7_default { 1494 function = "SALT7"; 1495 groups = "SALT7"; 1496 }; 1497 1498 pinctrl_salt8_default: salt8_default { 1499 function = "SALT8"; 1500 groups = "SALT8"; 1501 }; 1502 1503 pinctrl_salt9_default: salt9_default { 1504 function = "SALT9"; 1505 groups = "SALT9"; 1506 }; 1507 1508 pinctrl_scl1_default: scl1_default { 1509 function = "SCL1"; 1510 groups = "SCL1"; 1511 }; 1512 1513 pinctrl_scl2_default: scl2_default { 1514 function = "SCL2"; 1515 groups = "SCL2"; 1516 }; 1517 1518 pinctrl_sd1_default: sd1_default { 1519 function = "SD1"; 1520 groups = "SD1"; 1521 }; 1522 1523 pinctrl_sd2_default: sd2_default { 1524 function = "SD2"; 1525 groups = "SD2"; 1526 }; 1527 1528 pinctrl_emmc_default: emmc_default { 1529 function = "EMMC"; 1530 groups = "EMMC"; 1531 }; 1532 1533 pinctrl_sda1_default: sda1_default { 1534 function = "SDA1"; 1535 groups = "SDA1"; 1536 }; 1537 1538 pinctrl_sda2_default: sda2_default { 1539 function = "SDA2"; 1540 groups = "SDA2"; 1541 }; 1542 1543 pinctrl_sgps1_default: sgps1_default { 1544 function = "SGPS1"; 1545 groups = "SGPS1"; 1546 }; 1547 1548 pinctrl_sgps2_default: sgps2_default { 1549 function = "SGPS2"; 1550 groups = "SGPS2"; 1551 }; 1552 1553 pinctrl_sioonctrl_default: sioonctrl_default { 1554 function = "SIOONCTRL"; 1555 groups = "SIOONCTRL"; 1556 }; 1557 1558 pinctrl_siopbi_default: siopbi_default { 1559 function = "SIOPBI"; 1560 groups = "SIOPBI"; 1561 }; 1562 1563 pinctrl_siopbo_default: siopbo_default { 1564 function = "SIOPBO"; 1565 groups = "SIOPBO"; 1566 }; 1567 1568 pinctrl_siopwreq_default: siopwreq_default { 1569 function = "SIOPWREQ"; 1570 groups = "SIOPWREQ"; 1571 }; 1572 1573 pinctrl_siopwrgd_default: siopwrgd_default { 1574 function = "SIOPWRGD"; 1575 groups = "SIOPWRGD"; 1576 }; 1577 1578 pinctrl_sios3_default: sios3_default { 1579 function = "SIOS3"; 1580 groups = "SIOS3"; 1581 }; 1582 1583 pinctrl_sios5_default: sios5_default { 1584 function = "SIOS5"; 1585 groups = "SIOS5"; 1586 }; 1587 1588 pinctrl_siosci_default: siosci_default { 1589 function = "SIOSCI"; 1590 groups = "SIOSCI"; 1591 }; 1592 1593 pinctrl_spi1_default: spi1_default { 1594 function = "SPI1"; 1595 groups = "SPI1"; 1596 }; 1597 1598 pinctrl_spi1cs1_default: spi1cs1_default { 1599 function = "SPI1CS1"; 1600 groups = "SPI1CS1"; 1601 }; 1602 1603 pinctrl_spi1debug_default: spi1debug_default { 1604 function = "SPI1DEBUG"; 1605 groups = "SPI1DEBUG"; 1606 }; 1607 1608 pinctrl_spi1passthru_default: spi1passthru_default { 1609 function = "SPI1PASSTHRU"; 1610 groups = "SPI1PASSTHRU"; 1611 }; 1612 1613 pinctrl_spi2ck_default: spi2ck_default { 1614 function = "SPI2CK"; 1615 groups = "SPI2CK"; 1616 }; 1617 1618 pinctrl_spi2cs0_default: spi2cs0_default { 1619 function = "SPI2CS0"; 1620 groups = "SPI2CS0"; 1621 }; 1622 1623 pinctrl_spi2cs1_default: spi2cs1_default { 1624 function = "SPI2CS1"; 1625 groups = "SPI2CS1"; 1626 }; 1627 1628 pinctrl_spi2miso_default: spi2miso_default { 1629 function = "SPI2MISO"; 1630 groups = "SPI2MISO"; 1631 }; 1632 1633 pinctrl_spi2mosi_default: spi2mosi_default { 1634 function = "SPI2MOSI"; 1635 groups = "SPI2MOSI"; 1636 }; 1637 1638 pinctrl_timer3_default: timer3_default { 1639 function = "TIMER3"; 1640 groups = "TIMER3"; 1641 }; 1642 1643 pinctrl_timer4_default: timer4_default { 1644 function = "TIMER4"; 1645 groups = "TIMER4"; 1646 }; 1647 1648 pinctrl_timer5_default: timer5_default { 1649 function = "TIMER5"; 1650 groups = "TIMER5"; 1651 }; 1652 1653 pinctrl_timer6_default: timer6_default { 1654 function = "TIMER6"; 1655 groups = "TIMER6"; 1656 }; 1657 1658 pinctrl_timer7_default: timer7_default { 1659 function = "TIMER7"; 1660 groups = "TIMER7"; 1661 }; 1662 1663 pinctrl_timer8_default: timer8_default { 1664 function = "TIMER8"; 1665 groups = "TIMER8"; 1666 }; 1667 1668 pinctrl_txd1_default: txd1_default { 1669 function = "TXD1"; 1670 groups = "TXD1"; 1671 }; 1672 1673 pinctrl_txd2_default: txd2_default { 1674 function = "TXD2"; 1675 groups = "TXD2"; 1676 }; 1677 1678 pinctrl_txd3_default: txd3_default { 1679 function = "TXD3"; 1680 groups = "TXD3"; 1681 }; 1682 1683 pinctrl_txd4_default: txd4_default { 1684 function = "TXD4"; 1685 groups = "TXD4"; 1686 }; 1687 1688 pinctrl_uart6_default: uart6_default { 1689 function = "UART6"; 1690 groups = "UART6"; 1691 }; 1692 1693 pinctrl_usbcki_default: usbcki_default { 1694 function = "USBCKI"; 1695 groups = "USBCKI"; 1696 }; 1697 1698 pinctrl_usb2ah_default: usb2ah_default { 1699 function = "USB2AH"; 1700 groups = "USB2AH"; 1701 }; 1702 1703 pinctrl_usb11bhid_default: usb11bhid_default { 1704 function = "USB11BHID"; 1705 groups = "USB11BHID"; 1706 }; 1707 1708 pinctrl_usb2bh_default: usb2bh_default { 1709 function = "USB2BH"; 1710 groups = "USB2BH"; 1711 }; 1712 1713 pinctrl_vgabiosrom_default: vgabiosrom_default { 1714 function = "VGABIOSROM"; 1715 groups = "VGABIOSROM"; 1716 }; 1717 1718 pinctrl_vgahs_default: vgahs_default { 1719 function = "VGAHS"; 1720 groups = "VGAHS"; 1721 }; 1722 1723 pinctrl_vgavs_default: vgavs_default { 1724 function = "VGAVS"; 1725 groups = "VGAVS"; 1726 }; 1727 1728 pinctrl_vpi24_default: vpi24_default { 1729 function = "VPI24"; 1730 groups = "VPI24"; 1731 }; 1732 1733 pinctrl_vpo_default: vpo_default { 1734 function = "VPO"; 1735 groups = "VPO"; 1736 }; 1737 1738 pinctrl_wdtrst1_default: wdtrst1_default { 1739 function = "WDTRST1"; 1740 groups = "WDTRST1"; 1741 }; 1742 1743 pinctrl_wdtrst2_default: wdtrst2_default { 1744 function = "WDTRST2"; 1745 groups = "WDTRST2"; 1746 }; 1747}; 1748