1// SPDX-License-Identifier: GPL-2.0+ 2#include <dt-bindings/interrupt-controller/arm-gic.h> 3#include <dt-bindings/gpio/aspeed-gpio.h> 4#include "skeleton.dtsi" 5 6/ { 7 model = "Aspeed BMC"; 8 compatible = "aspeed,ast2600"; 9 #address-cells = <1>; 10 #size-cells = <1>; 11 interrupt-parent = <&gic>; 12 13 aliases { 14 i2c0 = &i2c0; 15 i2c1 = &i2c1; 16 i2c2 = &i2c2; 17 i2c3 = &i2c3; 18 i2c4 = &i2c4; 19 i2c5 = &i2c5; 20 i2c6 = &i2c6; 21 i2c7 = &i2c7; 22 i2c8 = &i2c8; 23 i2c9 = &i2c9; 24 i2c10 = &i2c10; 25 i2c11 = &i2c11; 26 i2c12 = &i2c12; 27 i2c13 = &i2c13; 28 i2c14 = &i2c14; 29 i2c15 = &i2c15; 30 serial0 = &uart1; 31 serial1 = &uart2; 32 serial2 = &uart3; 33 serial3 = &uart4; 34 serial4 = &uart5; 35 serial5 = &uart6; 36 serial6 = &uart7; 37 serial7 = &uart8; 38 serial8 = &uart9; 39 serial9 = &uart10; 40 serial10 = &uart11; 41 serial11 = &uart12; 42 serial12 = &uart13; 43 }; 44 45 cpus { 46 #address-cells = <1>; 47 #size-cells = <0>; 48 enable-method = "aspeed,ast2600-smp"; 49 50 cpu@0 { 51 compatible = "arm,cortex-a7"; 52 device_type = "cpu"; 53 reg = <0>; 54 }; 55 56 cpu@1 { 57 compatible = "arm,cortex-a7"; 58 device_type = "cpu"; 59 reg = <1>; 60 }; 61 62 }; 63 64 timer { 65 compatible = "arm,armv7-timer"; 66 interrupt-parent = <&gic>; 67 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 68 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 69 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 70 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 71 }; 72 73 reserved-memory { 74 #address-cells = <1>; 75 #size-cells = <1>; 76 ranges; 77 78 gfx_memory: framebuffer { 79 size = <0x01000000>; 80 alignment = <0x01000000>; 81 compatible = "shared-dma-pool"; 82 reusable; 83 }; 84 85 video_memory: video { 86 size = <0x04000000>; 87 alignment = <0x01000000>; 88 compatible = "shared-dma-pool"; 89 no-map; 90 }; 91 }; 92 93 ahb { 94 compatible = "simple-bus"; 95 #address-cells = <1>; 96 #size-cells = <1>; 97 device_type = "soc"; 98 ranges; 99 100 gic: interrupt-controller@40461000 { 101 compatible = "arm,cortex-a7-gic"; 102 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 103 #interrupt-cells = <3>; 104 interrupt-controller; 105 interrupt-parent = <&gic>; 106 reg = <0x40461000 0x1000>, 107 <0x40462000 0x1000>, 108 <0x40464000 0x2000>, 109 <0x40466000 0x2000>; 110 }; 111 112 ahbc: ahbc@1e600000 { 113 compatible = "aspeed,aspeed-ahbc"; 114 reg = < 0x1e600000 0x100>; 115 }; 116 117 fmc: flash-controller@1e620000 { 118 reg = < 0x1e620000 0xc4 119 0x20000000 0x10000000 >; 120 #address-cells = <1>; 121 #size-cells = <0>; 122 compatible = "aspeed,ast2600-fmc"; 123 status = "disabled"; 124 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 125 clocks = <&scu ASPEED_CLK_AHB>; 126 num-cs = <3>; 127 flash@0 { 128 reg = < 0 >; 129 compatible = "jedec,spi-nor"; 130 status = "disabled"; 131 }; 132 flash@1 { 133 reg = < 1 >; 134 compatible = "jedec,spi-nor"; 135 status = "disabled"; 136 }; 137 flash@2 { 138 reg = < 2 >; 139 compatible = "jedec,spi-nor"; 140 status = "disabled"; 141 }; 142 }; 143 144 spi1: flash-controller@1e630000 { 145 reg = < 0x1e630000 0xc4 146 0x30000000 0x08000000 >; 147 #address-cells = <1>; 148 #size-cells = <0>; 149 compatible = "aspeed,ast2600-spi"; 150 clocks = <&scu ASPEED_CLK_AHB>; 151 num-cs = <2>; 152 status = "disabled"; 153 flash@0 { 154 reg = < 0 >; 155 compatible = "jedec,spi-nor"; 156 status = "disabled"; 157 }; 158 flash@1 { 159 reg = < 1 >; 160 compatible = "jedec,spi-nor"; 161 status = "disabled"; 162 }; 163 }; 164 165 spi2: flash-controller@1e631000 { 166 reg = < 0x1e631000 0xc4 167 0x50000000 0x08000000 >; 168 #address-cells = <1>; 169 #size-cells = <0>; 170 compatible = "aspeed,ast2600-spi"; 171 clocks = <&scu ASPEED_CLK_AHB>; 172 num-cs = <3>; 173 status = "disabled"; 174 flash@0 { 175 reg = < 0 >; 176 compatible = "jedec,spi-nor"; 177 status = "disabled"; 178 }; 179 flash@1 { 180 reg = < 1 >; 181 compatible = "jedec,spi-nor"; 182 status = "disabled"; 183 }; 184 flash@2 { 185 reg = < 2 >; 186 compatible = "jedec,spi-nor"; 187 status = "disabled"; 188 }; 189 }; 190 191 edac: sdram@1e6e0000 { 192 compatible = "aspeed,ast2600-sdram-edac"; 193 reg = <0x1e6e0000 0x174>; 194 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 195 }; 196 197 mdio: ethernet@1e650000 { 198 compatible = "aspeed,aspeed-mdio"; 199 reg = <0x1e650000 0x40>; 200 resets = <&rst ASPEED_RESET_MII>; 201 status = "disabled"; 202 }; 203 204 mac0: ftgmac@1e660000 { 205 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 206 reg = <0x1e660000 0x180>, <0x1e650000 0x4>; 207 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 208 clocks = <&scu ASPEED_CLK_GATE_MAC1CLK>; 209 status = "disabled"; 210 }; 211 212 mac1: ftgmac@1e680000 { 213 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 214 reg = <0x1e680000 0x180>, <0x1e650008 0x4>; 215 #address-cells = <1>; 216 #size-cells = <0>; 217 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 218 clocks = <&scu ASPEED_CLK_GATE_MAC2CLK>; 219 status = "disabled"; 220 }; 221 222 mac2: ftgmac@1e670000 { 223 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 224 reg = <0x1e670000 0x180>, <0x1e650010 0x4>; 225 #address-cells = <1>; 226 #size-cells = <0>; 227 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 228 clocks = <&scu ASPEED_CLK_GATE_MAC3CLK>; 229 status = "disabled"; 230 }; 231 232 mac3: ftgmac@1e690000 { 233 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 234 reg = <0x1e690000 0x180>, <0x1e650018 0x4>; 235 #address-cells = <1>; 236 #size-cells = <0>; 237 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 238 clocks = <&scu ASPEED_CLK_GATE_MAC4CLK>; 239 status = "disabled"; 240 }; 241 242 ehci0: usb@1e6a1000 { 243 compatible = "aspeed,aspeed-ehci", "usb-ehci"; 244 reg = <0x1e6a1000 0x100>; 245 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 246 clocks = <&scu ASPEED_CLK_GATE_USBPORT1CLK>; 247 pinctrl-names = "default"; 248 pinctrl-0 = <&pinctrl_usb2ah_default>; 249 status = "disabled"; 250 }; 251 252 ehci1: usb@1e6a3000 { 253 compatible = "aspeed,aspeed-ehci", "usb-ehci"; 254 reg = <0x1e6a3000 0x100>; 255 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 256 clocks = <&scu ASPEED_CLK_GATE_USBPORT2CLK>; 257 pinctrl-names = "default"; 258 pinctrl-0 = <&pinctrl_usb2bh_default>; 259 status = "disabled"; 260 }; 261 262 apb { 263 compatible = "simple-bus"; 264 #address-cells = <1>; 265 #size-cells = <1>; 266 ranges; 267 268 syscon: syscon@1e6e2000 { 269 compatible = "aspeed,g6-scu", "syscon", "simple-mfd"; 270 reg = <0x1e6e2000 0x1000>; 271 #address-cells = <1>; 272 #size-cells = <1>; 273 #clock-cells = <1>; 274 #reset-cells = <1>; 275 ranges = <0 0x1e6e2000 0x1000>; 276 277 pinctrl: pinctrl { 278 compatible = "aspeed,g6-pinctrl"; 279 aspeed,external-nodes = <&gfx &lhc>; 280 281 }; 282 283 vga_scratch: scratch { 284 compatible = "aspeed,bmc-misc"; 285 }; 286 287 scu_ic0: interrupt-controller@0 { 288 #interrupt-cells = <1>; 289 compatible = "aspeed,ast2600-scu-ic"; 290 reg = <0x560 0x10>; 291 interrupt-parent = <&gic>; 292 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 293 interrupt-controller; 294 }; 295 296 scu_ic1: interrupt-controller@1 { 297 #interrupt-cells = <1>; 298 compatible = "aspeed,ast2600-scu-ic"; 299 reg = <0x570 0x10>; 300 interrupt-parent = <&gic>; 301 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 302 interrupt-controller; 303 }; 304 305 }; 306 307 hace: hace@1e6d0000 { 308 compatible = "aspeed,ast2600-hace"; 309 reg = <0x1e6d0000 0x200>; 310 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 311 clocks = <&scu ASPEED_CLK_GATE_YCLK>; 312 clock-names = "yclk"; 313 status = "disabled"; 314 }; 315 316 arcy: arcy@1e6fa000 { 317 compatible = "aspeed,ast2600-arcy"; 318 reg = <0x1e6fa000 0x1000>; 319 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 320 clocks = <&scu ASPEED_CLK_GATE_RSAECCCLK>; 321 clock-names = "rsaeccclk"; 322 status = "disabled"; 323 }; 324 325 smp-memram@0 { 326 compatible = "aspeed,ast2600-smpmem", "syscon"; 327 reg = <0x1e6e2180 0x40>; 328 }; 329 330 gfx: display@1e6e6000 { 331 compatible = "aspeed,ast2500-gfx", "syscon"; 332 reg = <0x1e6e6000 0x1000>; 333 reg-io-width = <4>; 334 }; 335 336 pcie_bridge0: pcie@1e6ed000 { 337 compatible = "aspeed,ast2600-pcie"; 338 #address-cells = <3>; 339 #size-cells = <2>; 340 reg = <0x1e6ed000 0x100>; 341 ranges = <0x81000000 0x0 0x0 0x0 0x0 0x10000 /* downstream I/O */ 342 0x82000000 0x0 0x60000000 0x60000000 0x0 0x10000000>; /* non-prefetchable memory */ 343 device_type = "pci"; 344 bus-range = <0x00 0xff>; 345 resets = <&rst ASPEED_RESET_PCIE_DEV_O>; 346 cfg-handle = <&pcie_cfg0>; 347 pinctrl-names = "default"; 348 pinctrl-0 = <&pinctrl_pcie0rc_default>; 349 350 status = "disabled"; 351 }; 352 353 pcie_bridge1: pcie@1e6ed200 { 354 compatible = "aspeed,ast2600-pcie"; 355 #address-cells = <3>; 356 #size-cells = <2>; 357 reg = <0x1e6ed200 0x100>; 358 ranges = <0x81000000 0x0 0x0 0x10000 0x00 0x10000 /* downstream I/O */ 359 0x82000000 0x0 0x70000000 0x70000000 0x0 0x10000000>; /* non-prefetchable memory */ 360 device_type = "pci"; 361 bus-range = <0x00 0xff>; 362 resets = <&rst ASPEED_RESET_PCIE_RC_O>; 363 cfg-handle = <&pcie_cfg1>; 364 pinctrl-names = "default"; 365 pinctrl-0 = <&pinctrl_pcie1rc_default>; 366 367 status = "disabled"; 368 }; 369 370 sdhci: sdhci@1e740000 { 371 #interrupt-cells = <1>; 372 compatible = "aspeed,aspeed-sdhci-irq", "simple-mfd"; 373 reg = <0x1e740000 0x1000>; 374 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 375 interrupt-controller; 376 clocks = <&scu ASPEED_CLK_GATE_SDCLK>, <&scu ASPEED_CLK_GATE_SDEXTCLK>; 377 clock-names = "ctrlclk", "extclk"; 378 #address-cells = <1>; 379 #size-cells = <1>; 380 ranges = <0x0 0x1e740000 0x1000>; 381 382 sdhci_slot0: sdhci_slot0@100 { 383 compatible = "aspeed,sdhci-ast2600"; 384 reg = <0x100 0x100>; 385 interrupts = <0>; 386 interrupt-parent = <&sdhci>; 387 sdhci,auto-cmd12; 388 clocks = <&scu ASPEED_CLK_SDIO>; 389 status = "disabled"; 390 }; 391 392 sdhci_slot1: sdhci_slot1@200 { 393 compatible = "aspeed,sdhci-ast2600"; 394 reg = <0x200 0x100>; 395 interrupts = <1>; 396 interrupt-parent = <&sdhci>; 397 sdhci,auto-cmd12; 398 clocks = <&scu ASPEED_CLK_SDIO>; 399 status = "disabled"; 400 }; 401 }; 402 403 emmc: emmc@1e750000 { 404 #interrupt-cells = <1>; 405 compatible = "aspeed,aspeed-emmc-irq", "simple-mfd"; 406 reg = <0x1e750000 0x1000>; 407 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 408 interrupt-controller; 409 clocks = <&scu ASPEED_CLK_GATE_EMMCCLK>, <&scu ASPEED_CLK_GATE_EMMCEXTCLK>; 410 clock-names = "ctrlclk", "extclk"; 411 #address-cells = <1>; 412 #size-cells = <1>; 413 ranges = <0x0 0x1e750000 0x1000>; 414 415 emmc_slot0: emmc_slot0@100 { 416 compatible = "aspeed,emmc-ast2600"; 417 reg = <0x100 0x100>; 418 interrupts = <0>; 419 interrupt-parent = <&emmc>; 420 clocks = <&scu ASPEED_CLK_EMMC>; 421 status = "disabled"; 422 }; 423 }; 424 425 h2x: h2x@1e770000 { 426 compatible = "aspeed,ast2600-h2x"; 427 reg = <0x1e770000 0x100>; 428 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 429 resets = <&rst ASPEED_RESET_H2X>; 430 #address-cells = <1>; 431 #size-cells = <1>; 432 ranges = <0x0 0x1e770000 0x100>; 433 434 status = "disabled"; 435 436 pcie_cfg0: cfg0@80 { 437 reg = <0x80 0x80>; 438 compatible = "aspeed,ast2600-pcie-cfg"; 439 }; 440 441 pcie_cfg1: cfg1@C0 { 442 compatible = "aspeed,ast2600-pcie-cfg"; 443 reg = <0xC0 0x80>; 444 }; 445 }; 446 447 gpio0: gpio@1e780000 { 448 compatible = "aspeed,ast2600-gpio"; 449 reg = <0x1e780000 0x400>; 450 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 451 #gpio-cells = <2>; 452 gpio-controller; 453 interrupt-controller; 454 gpio-ranges = <&pinctrl 0 0 208>; 455 ngpios = <208>; 456 }; 457 458 gpio1: gpio@1e780800 { 459 compatible = "aspeed,ast2600-gpio"; 460 reg = <0x1e780800 0x800>; 461 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 462 #gpio-cells = <2>; 463 gpio-controller; 464 interrupt-controller; 465 gpio-ranges = <&pinctrl 0 208 36>; 466 ngpios = <36>; 467 }; 468 469 uart1: serial@1e783000 { 470 compatible = "ns16550a"; 471 reg = <0x1e783000 0x20>; 472 reg-shift = <2>; 473 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 474 clocks = <&scu ASPEED_CLK_GATE_UART1CLK>; 475 clock-frequency = <1846154>; 476 no-loopback-test; 477 status = "disabled"; 478 }; 479 480 uart5: serial@1e784000 { 481 compatible = "ns16550a"; 482 reg = <0x1e784000 0x1000>; 483 reg-shift = <2>; 484 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 485 clocks = <&scu ASPEED_CLK_GATE_UART5CLK>; 486 clock-frequency = <1846154>; 487 no-loopback-test; 488 status = "disabled"; 489 }; 490 491 wdt1: watchdog@1e785000 { 492 compatible = "aspeed,ast2600-wdt"; 493 reg = <0x1e785000 0x40>; 494 }; 495 496 wdt2: watchdog@1e785040 { 497 compatible = "aspeed,ast2600-wdt"; 498 reg = <0x1e785040 0x40>; 499 }; 500 501 wdt3: watchdog@1e785080 { 502 compatible = "aspeed,ast2600-wdt"; 503 reg = <0x1e785080 0x40>; 504 }; 505 506 wdt4: watchdog@1e7850C0 { 507 compatible = "aspeed,ast2600-wdt"; 508 reg = <0x1e7850C0 0x40>; 509 }; 510 511 lpc: lpc@1e789000 { 512 compatible = "aspeed,ast-lpc", "simple-mfd", "syscon"; 513 reg = <0x1e789000 0x200>; 514 515 #address-cells = <1>; 516 #size-cells = <1>; 517 ranges = <0x0 0x1e789000 0x1000>; 518 519 lpc_bmc: lpc-bmc@0 { 520 compatible = "aspeed,ast2600-lpc-bmc", "simple-mfd", "syscon"; 521 reg = <0x0 0x80>; 522 reg-io-width = <4>; 523 #address-cells = <1>; 524 #size-cells = <1>; 525 ranges = <0x0 0x0 0x80>; 526 527 kcs1: kcs1@0 { 528 compatible = "aspeed,ast2600-kcs-bmc"; 529 reg = <0x0 0x80>; 530 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 531 kcs_chan = <1>; 532 kcs_addr = <0xCA0>; 533 status = "disabled"; 534 }; 535 536 kcs2: kcs2@0 { 537 compatible = "aspeed,ast2600-kcs-bmc"; 538 reg = <0x0 0x80>; 539 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 540 kcs_chan = <2>; 541 kcs_addr = <0xCA8>; 542 status = "disabled"; 543 }; 544 545 kcs3: kcs3@0 { 546 compatible = "aspeed,ast2600-kcs-bmc"; 547 reg = <0x0 0x80>; 548 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 549 kcs_chan = <3>; 550 kcs_addr = <0xCA2>; 551 }; 552 553 kcs4: kcs4@0 { 554 compatible = "aspeed,ast2600-kcs-bmc"; 555 reg = <0x0 0x120>; 556 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 557 kcs_chan = <4>; 558 kcs_addr = <0xCA4>; 559 status = "disabled"; 560 }; 561 562 }; 563 564 lpc_host: lpc-host@80 { 565 compatible = "aspeed,ast2600-lpc-host", "simple-mfd", "syscon"; 566 reg = <0x80 0x1e0>; 567 reg-io-width = <4>; 568 569 #address-cells = <1>; 570 #size-cells = <1>; 571 ranges = <0x0 0x80 0x1e0>; 572 573 lpc_ctrl: lpc-ctrl@0 { 574 compatible = "aspeed,ast2600-lpc-ctrl"; 575 reg = <0x0 0x80>; 576 status = "disabled"; 577 }; 578 579 lpc_snoop: lpc-snoop@0 { 580 compatible = "aspeed,ast2600-lpc-snoop"; 581 reg = <0x0 0x80>; 582 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 583 snoop-ports = <0x80>; 584 status = "disabled"; 585 }; 586 587 lhc: lhc@20 { 588 compatible = "aspeed,ast2600-lhc"; 589 reg = <0x20 0x24 0x48 0x8>; 590 }; 591 592 lpc_reset: reset-controller@18 { 593 compatible = "aspeed,ast2600-lpc-reset"; 594 reg = <0x18 0x4>; 595 #reset-cells = <1>; 596 status = "disabled"; 597 }; 598 599 ibt: ibt@c0 { 600 compatible = "aspeed,ast2600-ibt-bmc"; 601 reg = <0xc0 0x18>; 602 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 603 status = "disabled"; 604 }; 605 606 sio_regs: regs { 607 compatible = "aspeed,bmc-misc"; 608 }; 609 610 mbox: mbox@180 { 611 compatible = "aspeed,ast2600-mbox"; 612 reg = <0x180 0x5c>; 613 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 614 #mbox-cells = <1>; 615 status = "disabled"; 616 }; 617 }; 618 }; 619 620 uart2: serial@1e78d000 { 621 compatible = "ns16550a"; 622 reg = <0x1e78d000 0x20>; 623 reg-shift = <2>; 624 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 625 clocks = <&scu ASPEED_CLK_GATE_UART2CLK>; 626 clock-frequency = <1846154>; 627 no-loopback-test; 628 status = "disabled"; 629 }; 630 631 uart3: serial@1e78e000 { 632 compatible = "ns16550a"; 633 reg = <0x1e78e000 0x20>; 634 reg-shift = <2>; 635 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 636 clocks = <&scu ASPEED_CLK_GATE_UART3CLK>; 637 clock-frequency = <1846154>; 638 no-loopback-test; 639 status = "disabled"; 640 }; 641 642 uart4: serial@1e78f000 { 643 compatible = "ns16550a"; 644 reg = <0x1e78f000 0x20>; 645 reg-shift = <2>; 646 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 647 clocks = <&scu ASPEED_CLK_GATE_UART4CLK>; 648 clock-frequency = <1846154>; 649 no-loopback-test; 650 status = "disabled"; 651 }; 652 653 i2c: bus@1e78a000 { 654 compatible = "simple-bus"; 655 #address-cells = <1>; 656 #size-cells = <1>; 657 ranges = <0 0x1e78a000 0x1000>; 658 }; 659 660 fsim0: fsi@1e79b000 { 661 compatible = "aspeed,ast2600-fsi-master", "fsi-master"; 662 reg = <0x1e79b000 0x94>; 663 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 664 pinctrl-names = "default"; 665 pinctrl-0 = <&pinctrl_fsi1_default>; 666 clocks = <&scu ASPEED_CLK_GATE_FSICLK>; 667 status = "disabled"; 668 }; 669 670 fsim1: fsi@1e79b100 { 671 compatible = "aspeed,ast2600-fsi-master", "fsi-master"; 672 reg = <0x1e79b100 0x94>; 673 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 674 pinctrl-names = "default"; 675 pinctrl-0 = <&pinctrl_fsi2_default>; 676 clocks = <&scu ASPEED_CLK_GATE_FSICLK>; 677 status = "disabled"; 678 }; 679 680 uart6: serial@1e790000 { 681 compatible = "ns16550a"; 682 reg = <0x1e790000 0x20>; 683 reg-shift = <2>; 684 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 685 clocks = <&scu ASPEED_CLK_GATE_UART6CLK>; 686 clock-frequency = <1846154>; 687 no-loopback-test; 688 status = "disabled"; 689 }; 690 691 uart7: serial@1e790100 { 692 compatible = "ns16550a"; 693 reg = <0x1e790100 0x20>; 694 reg-shift = <2>; 695 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 696 clocks = <&scu ASPEED_CLK_GATE_UART7CLK>; 697 clock-frequency = <1846154>; 698 no-loopback-test; 699 status = "disabled"; 700 }; 701 702 uart8: serial@1e790200 { 703 compatible = "ns16550a"; 704 reg = <0x1e790200 0x20>; 705 reg-shift = <2>; 706 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 707 clocks = <&scu ASPEED_CLK_GATE_UART8CLK>; 708 clock-frequency = <1846154>; 709 no-loopback-test; 710 status = "disabled"; 711 }; 712 713 uart9: serial@1e790300 { 714 compatible = "ns16550a"; 715 reg = <0x1e790300 0x20>; 716 reg-shift = <2>; 717 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 718 clocks = <&scu ASPEED_CLK_GATE_UART9CLK>; 719 clock-frequency = <1846154>; 720 no-loopback-test; 721 status = "disabled"; 722 }; 723 724 uart10: serial@1e790400 { 725 compatible = "ns16550a"; 726 reg = <0x1e790400 0x20>; 727 reg-shift = <2>; 728 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 729 clocks = <&scu ASPEED_CLK_GATE_UART10CLK>; 730 clock-frequency = <1846154>; 731 no-loopback-test; 732 status = "disabled"; 733 }; 734 735 uart11: serial@1e790500 { 736 compatible = "ns16550a"; 737 reg = <0x1e790400 0x20>; 738 reg-shift = <2>; 739 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 740 clocks = <&scu ASPEED_CLK_GATE_UART11CLK>; 741 clock-frequency = <1846154>; 742 no-loopback-test; 743 status = "disabled"; 744 }; 745 746 uart12: serial@1e790600 { 747 compatible = "ns16550a"; 748 reg = <0x1e790600 0x20>; 749 reg-shift = <2>; 750 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 751 clocks = <&scu ASPEED_CLK_GATE_UART12CLK>; 752 clock-frequency = <1846154>; 753 no-loopback-test; 754 status = "disabled"; 755 }; 756 757 uart13: serial@1e790700 { 758 compatible = "ns16550a"; 759 reg = <0x1e790700 0x20>; 760 reg-shift = <2>; 761 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 762 clocks = <&scu ASPEED_CLK_GATE_UART13CLK>; 763 clock-frequency = <1846154>; 764 no-loopback-test; 765 status = "disabled"; 766 }; 767 768 display_port: dp@1e6eb000 { 769 compatible = "aspeed,ast2600-displayport"; 770 reg = <0x1e6eb000 0x200>; 771 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 772 resets = <&rst ASPEED_RESET_DP> ,<&rst ASPEED_RESET_DP_MCU>; 773 status = "disabled"; 774 }; 775 776 }; 777 778 }; 779 780}; 781 782&i2c { 783 i2cglobal: i2cg@00 { 784 compatible = "aspeed,ast2600-i2c-global"; 785 reg = <0x0 0x40>; 786 resets = <&rst ASPEED_RESET_I2C>; 787#if 0 788 new-mode; 789#endif 790 }; 791 792 i2c0: i2c@80 { 793 #address-cells = <1>; 794 #size-cells = <0>; 795 #interrupt-cells = <1>; 796 797 reg = <0x80 0x80 0xC00 0x20>; 798 compatible = "aspeed,ast2600-i2c-bus"; 799 bus-frequency = <100000>; 800 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 801 clocks = <&scu ASPEED_CLK_APB2>; 802 status = "disabled"; 803 }; 804 805 i2c1: i2c@100 { 806 #address-cells = <1>; 807 #size-cells = <0>; 808 #interrupt-cells = <1>; 809 810 reg = <0x100 0x80 0xC20 0x20>; 811 compatible = "aspeed,ast2600-i2c-bus"; 812 bus-frequency = <100000>; 813 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 814 clocks = <&scu ASPEED_CLK_APB2>; 815 status = "disabled"; 816 }; 817 818 i2c2: i2c@180 { 819 #address-cells = <1>; 820 #size-cells = <0>; 821 #interrupt-cells = <1>; 822 823 reg = <0x180 0x80 0xC40 0x20>; 824 compatible = "aspeed,ast2600-i2c-bus"; 825 bus-frequency = <100000>; 826 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 827 clocks = <&scu ASPEED_CLK_APB2>; 828 }; 829 830 i2c3: i2c@200 { 831 #address-cells = <1>; 832 #size-cells = <0>; 833 #interrupt-cells = <1>; 834 835 reg = <0x200 0x40 0xC60 0x20>; 836 compatible = "aspeed,ast2600-i2c-bus"; 837 bus-frequency = <100000>; 838 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 839 clocks = <&scu ASPEED_CLK_APB2>; 840 }; 841 842 i2c4: i2c@280 { 843 #address-cells = <1>; 844 #size-cells = <0>; 845 #interrupt-cells = <1>; 846 847 reg = <0x280 0x80 0xC80 0x20>; 848 compatible = "aspeed,ast2600-i2c-bus"; 849 bus-frequency = <100000>; 850 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 851 clocks = <&scu ASPEED_CLK_APB2>; 852 }; 853 854 i2c5: i2c@300 { 855 #address-cells = <1>; 856 #size-cells = <0>; 857 #interrupt-cells = <1>; 858 859 reg = <0x300 0x40 0xCA0 0x20>; 860 compatible = "aspeed,ast2600-i2c-bus"; 861 bus-frequency = <100000>; 862 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 863 clocks = <&scu ASPEED_CLK_APB2>; 864 }; 865 866 i2c6: i2c@380 { 867 #address-cells = <1>; 868 #size-cells = <0>; 869 #interrupt-cells = <1>; 870 871 reg = <0x380 0x80 0xCC0 0x20>; 872 compatible = "aspeed,ast2600-i2c-bus"; 873 bus-frequency = <100000>; 874 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 875 clocks = <&scu ASPEED_CLK_APB2>; 876 }; 877 878 i2c7: i2c@400 { 879 #address-cells = <1>; 880 #size-cells = <0>; 881 #interrupt-cells = <1>; 882 883 reg = <0x400 0x80 0xCE0 0x20>; 884 compatible = "aspeed,ast2600-i2c-bus"; 885 bus-frequency = <100000>; 886 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 887 clocks = <&scu ASPEED_CLK_APB2>; 888 }; 889 890 i2c8: i2c@480 { 891 #address-cells = <1>; 892 #size-cells = <0>; 893 #interrupt-cells = <1>; 894 895 reg = <0x480 0x80 0xD00 0x20>; 896 compatible = "aspeed,ast2600-i2c-bus"; 897 bus-frequency = <100000>; 898 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 899 clocks = <&scu ASPEED_CLK_APB2>; 900 }; 901 902 i2c9: i2c@500 { 903 #address-cells = <1>; 904 #size-cells = <0>; 905 #interrupt-cells = <1>; 906 907 reg = <0x500 0x80 0xD20 0x20>; 908 compatible = "aspeed,ast2600-i2c-bus"; 909 bus-frequency = <100000>; 910 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 911 clocks = <&scu ASPEED_CLK_APB2>; 912 status = "disabled"; 913 }; 914 915 i2c10: i2c@580 { 916 #address-cells = <1>; 917 #size-cells = <0>; 918 #interrupt-cells = <1>; 919 920 reg = <0x580 0x80 0xD40 0x20>; 921 compatible = "aspeed,ast2600-i2c-bus"; 922 bus-frequency = <100000>; 923 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 924 clocks = <&scu ASPEED_CLK_APB2>; 925 status = "disabled"; 926 }; 927 928 i2c11: i2c@600 { 929 #address-cells = <1>; 930 #size-cells = <0>; 931 #interrupt-cells = <1>; 932 933 reg = <0x600 0x80 0xD60 0x20>; 934 compatible = "aspeed,ast2600-i2c-bus"; 935 bus-frequency = <100000>; 936 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 937 clocks = <&scu ASPEED_CLK_APB2>; 938 status = "disabled"; 939 }; 940 941 i2c12: i2c@680 { 942 #address-cells = <1>; 943 #size-cells = <0>; 944 #interrupt-cells = <1>; 945 946 reg = <0x680 0x80 0xD80 0x20>; 947 compatible = "aspeed,ast2600-i2c-bus"; 948 bus-frequency = <100000>; 949 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 950 clocks = <&scu ASPEED_CLK_APB2>; 951 status = "disabled"; 952 }; 953 954 i2c13: i2c@700 { 955 #address-cells = <1>; 956 #size-cells = <0>; 957 #interrupt-cells = <1>; 958 959 reg = <0x700 0x80 0xDA0 0x20>; 960 compatible = "aspeed,ast2600-i2c-bus"; 961 bus-frequency = <100000>; 962 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 963 clocks = <&scu ASPEED_CLK_APB2>; 964 status = "disabled"; 965 }; 966 967 i2c14: i2c@780 { 968 #address-cells = <1>; 969 #size-cells = <0>; 970 #interrupt-cells = <1>; 971 972 reg = <0x780 0x80 0xDC0 0x20>; 973 compatible = "aspeed,ast2600-i2c-bus"; 974 bus-frequency = <100000>; 975 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 976 clocks = <&scu ASPEED_CLK_APB2>; 977 status = "disabled"; 978 }; 979 980 i2c15: i2c@800 { 981 #address-cells = <1>; 982 #size-cells = <0>; 983 #interrupt-cells = <1>; 984 985 reg = <0x800 0x80 0xDE0 0x20>; 986 compatible = "aspeed,ast2600-i2c-bus"; 987 bus-frequency = <100000>; 988 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 989 clocks = <&scu ASPEED_CLK_APB2>; 990 status = "disabled"; 991 }; 992 993}; 994 995&pinctrl { 996 pinctrl_fmcquad_default: fmcquad_default { 997 function = "FMCQUAD"; 998 groups = "FMCQUAD"; 999 }; 1000 1001 pinctrl_spi1_default: spi1_default { 1002 function = "SPI1"; 1003 groups = "SPI1"; 1004 }; 1005 1006 pinctrl_spi1abr_default: spi1abr_default { 1007 function = "SPI1ABR"; 1008 groups = "SPI1ABR"; 1009 }; 1010 1011 pinctrl_spi1cs1_default: spi1cs1_default { 1012 function = "SPI1CS1"; 1013 groups = "SPI1CS1"; 1014 }; 1015 1016 pinctrl_spi1wp_default: spi1wp_default { 1017 function = "SPI1WP"; 1018 groups = "SPI1WP"; 1019 }; 1020 1021 pinctrl_spi1quad_default: spi1quad_default { 1022 function = "SPI1QUAD"; 1023 groups = "SPI1QUAD"; 1024 }; 1025 1026 pinctrl_spi2_default: spi2_default { 1027 function = "SPI2"; 1028 groups = "SPI2"; 1029 }; 1030 1031 pinctrl_spi2cs1_default: spi2cs1_default { 1032 function = "SPI2CS1"; 1033 groups = "SPI2CS1"; 1034 }; 1035 1036 pinctrl_spi2cs2_default: spi2cs2_default { 1037 function = "SPI2CS2"; 1038 groups = "SPI2CS2"; 1039 }; 1040 1041 pinctrl_spi2quad_default: spi2quad_default { 1042 function = "SPI2QUAD"; 1043 groups = "SPI2QUAD"; 1044 }; 1045 1046 pinctrl_acpi_default: acpi_default { 1047 function = "ACPI"; 1048 groups = "ACPI"; 1049 }; 1050 1051 pinctrl_adc0_default: adc0_default { 1052 function = "ADC0"; 1053 groups = "ADC0"; 1054 }; 1055 1056 pinctrl_adc1_default: adc1_default { 1057 function = "ADC1"; 1058 groups = "ADC1"; 1059 }; 1060 1061 pinctrl_adc10_default: adc10_default { 1062 function = "ADC10"; 1063 groups = "ADC10"; 1064 }; 1065 1066 pinctrl_adc11_default: adc11_default { 1067 function = "ADC11"; 1068 groups = "ADC11"; 1069 }; 1070 1071 pinctrl_adc12_default: adc12_default { 1072 function = "ADC12"; 1073 groups = "ADC12"; 1074 }; 1075 1076 pinctrl_adc13_default: adc13_default { 1077 function = "ADC13"; 1078 groups = "ADC13"; 1079 }; 1080 1081 pinctrl_adc14_default: adc14_default { 1082 function = "ADC14"; 1083 groups = "ADC14"; 1084 }; 1085 1086 pinctrl_adc15_default: adc15_default { 1087 function = "ADC15"; 1088 groups = "ADC15"; 1089 }; 1090 1091 pinctrl_adc2_default: adc2_default { 1092 function = "ADC2"; 1093 groups = "ADC2"; 1094 }; 1095 1096 pinctrl_adc3_default: adc3_default { 1097 function = "ADC3"; 1098 groups = "ADC3"; 1099 }; 1100 1101 pinctrl_adc4_default: adc4_default { 1102 function = "ADC4"; 1103 groups = "ADC4"; 1104 }; 1105 1106 pinctrl_adc5_default: adc5_default { 1107 function = "ADC5"; 1108 groups = "ADC5"; 1109 }; 1110 1111 pinctrl_adc6_default: adc6_default { 1112 function = "ADC6"; 1113 groups = "ADC6"; 1114 }; 1115 1116 pinctrl_adc7_default: adc7_default { 1117 function = "ADC7"; 1118 groups = "ADC7"; 1119 }; 1120 1121 pinctrl_adc8_default: adc8_default { 1122 function = "ADC8"; 1123 groups = "ADC8"; 1124 }; 1125 1126 pinctrl_adc9_default: adc9_default { 1127 function = "ADC9"; 1128 groups = "ADC9"; 1129 }; 1130 1131 pinctrl_bmcint_default: bmcint_default { 1132 function = "BMCINT"; 1133 groups = "BMCINT"; 1134 }; 1135 1136 pinctrl_ddcclk_default: ddcclk_default { 1137 function = "DDCCLK"; 1138 groups = "DDCCLK"; 1139 }; 1140 1141 pinctrl_ddcdat_default: ddcdat_default { 1142 function = "DDCDAT"; 1143 groups = "DDCDAT"; 1144 }; 1145 1146 pinctrl_espi_default: espi_default { 1147 function = "ESPI"; 1148 groups = "ESPI"; 1149 }; 1150 1151 pinctrl_fsi1_default: fsi1_default { 1152 function = "FSI1"; 1153 groups = "FSI1"; 1154 }; 1155 1156 pinctrl_fsi2_default: fsi2_default { 1157 function = "FSI2"; 1158 groups = "FSI2"; 1159 }; 1160 1161 pinctrl_fwspics1_default: fwspics1_default { 1162 function = "FWSPICS1"; 1163 groups = "FWSPICS1"; 1164 }; 1165 1166 pinctrl_fwspics2_default: fwspics2_default { 1167 function = "FWSPICS2"; 1168 groups = "FWSPICS2"; 1169 }; 1170 1171 pinctrl_gpid0_default: gpid0_default { 1172 function = "GPID0"; 1173 groups = "GPID0"; 1174 }; 1175 1176 pinctrl_gpid2_default: gpid2_default { 1177 function = "GPID2"; 1178 groups = "GPID2"; 1179 }; 1180 1181 pinctrl_gpid4_default: gpid4_default { 1182 function = "GPID4"; 1183 groups = "GPID4"; 1184 }; 1185 1186 pinctrl_gpid6_default: gpid6_default { 1187 function = "GPID6"; 1188 groups = "GPID6"; 1189 }; 1190 1191 pinctrl_gpie0_default: gpie0_default { 1192 function = "GPIE0"; 1193 groups = "GPIE0"; 1194 }; 1195 1196 pinctrl_gpie2_default: gpie2_default { 1197 function = "GPIE2"; 1198 groups = "GPIE2"; 1199 }; 1200 1201 pinctrl_gpie4_default: gpie4_default { 1202 function = "GPIE4"; 1203 groups = "GPIE4"; 1204 }; 1205 1206 pinctrl_gpie6_default: gpie6_default { 1207 function = "GPIE6"; 1208 groups = "GPIE6"; 1209 }; 1210 1211 pinctrl_i2c1_default: i2c1_default { 1212 function = "I2C1"; 1213 groups = "I2C1"; 1214 }; 1215 pinctrl_i2c2_default: i2c2_default { 1216 function = "I2C2"; 1217 groups = "I2C2"; 1218 }; 1219 1220 pinctrl_i2c3_default: i2c3_default { 1221 function = "I2C3"; 1222 groups = "I2C3"; 1223 }; 1224 1225 pinctrl_i2c4_default: i2c4_default { 1226 function = "I2C4"; 1227 groups = "I2C4"; 1228 }; 1229 1230 pinctrl_i2c5_default: i2c5_default { 1231 function = "I2C5"; 1232 groups = "I2C5"; 1233 }; 1234 1235 pinctrl_i2c6_default: i2c6_default { 1236 function = "I2C6"; 1237 groups = "I2C6"; 1238 }; 1239 1240 pinctrl_i2c7_default: i2c7_default { 1241 function = "I2C7"; 1242 groups = "I2C7"; 1243 }; 1244 1245 pinctrl_i2c8_default: i2c8_default { 1246 function = "I2C8"; 1247 groups = "I2C8"; 1248 }; 1249 1250 pinctrl_i2c9_default: i2c9_default { 1251 function = "I2C9"; 1252 groups = "I2C9"; 1253 }; 1254 1255 pinctrl_i2c10_default: i2c10_default { 1256 function = "I2C10"; 1257 groups = "I2C10"; 1258 }; 1259 1260 pinctrl_i2c11_default: i2c11_default { 1261 function = "I2C11"; 1262 groups = "I2C11"; 1263 }; 1264 1265 pinctrl_i2c12_default: i2c12_default { 1266 function = "I2C12"; 1267 groups = "I2C12"; 1268 }; 1269 1270 pinctrl_i2c13_default: i2c13_default { 1271 function = "I2C13"; 1272 groups = "I2C13"; 1273 }; 1274 1275 pinctrl_i2c14_default: i2c14_default { 1276 function = "I2C14"; 1277 groups = "I2C14"; 1278 }; 1279 1280 pinctrl_i2c15_default: i2c15_default { 1281 function = "I2C15"; 1282 groups = "I2C15"; 1283 }; 1284 1285 pinctrl_i2c16_default: i2c16_default { 1286 function = "I2C16"; 1287 groups = "I2C16"; 1288 }; 1289 1290 pinctrl_lad0_default: lad0_default { 1291 function = "LAD0"; 1292 groups = "LAD0"; 1293 }; 1294 1295 pinctrl_lad1_default: lad1_default { 1296 function = "LAD1"; 1297 groups = "LAD1"; 1298 }; 1299 1300 pinctrl_lad2_default: lad2_default { 1301 function = "LAD2"; 1302 groups = "LAD2"; 1303 }; 1304 1305 pinctrl_lad3_default: lad3_default { 1306 function = "LAD3"; 1307 groups = "LAD3"; 1308 }; 1309 1310 pinctrl_lclk_default: lclk_default { 1311 function = "LCLK"; 1312 groups = "LCLK"; 1313 }; 1314 1315 pinctrl_lframe_default: lframe_default { 1316 function = "LFRAME"; 1317 groups = "LFRAME"; 1318 }; 1319 1320 pinctrl_lpchc_default: lpchc_default { 1321 function = "LPCHC"; 1322 groups = "LPCHC"; 1323 }; 1324 1325 pinctrl_lpcpd_default: lpcpd_default { 1326 function = "LPCPD"; 1327 groups = "LPCPD"; 1328 }; 1329 1330 pinctrl_lpcplus_default: lpcplus_default { 1331 function = "LPCPLUS"; 1332 groups = "LPCPLUS"; 1333 }; 1334 1335 pinctrl_lpcpme_default: lpcpme_default { 1336 function = "LPCPME"; 1337 groups = "LPCPME"; 1338 }; 1339 1340 pinctrl_lpcrst_default: lpcrst_default { 1341 function = "LPCRST"; 1342 groups = "LPCRST"; 1343 }; 1344 1345 pinctrl_lpcsmi_default: lpcsmi_default { 1346 function = "LPCSMI"; 1347 groups = "LPCSMI"; 1348 }; 1349 1350 pinctrl_lsirq_default: lsirq_default { 1351 function = "LSIRQ"; 1352 groups = "LSIRQ"; 1353 }; 1354 1355 pinctrl_mac1link_default: mac1link_default { 1356 function = "MAC1LINK"; 1357 groups = "MAC1LINK"; 1358 }; 1359 1360 pinctrl_mac2link_default: mac2link_default { 1361 function = "MAC2LINK"; 1362 groups = "MAC2LINK"; 1363 }; 1364 1365 pinctrl_mac3link_default: mac3link_default { 1366 function = "MAC3LINK"; 1367 groups = "MAC3LINK"; 1368 }; 1369 1370 pinctrl_mac4link_default: mac4link_default { 1371 function = "MAC4LINK"; 1372 groups = "MAC4LINK"; 1373 }; 1374 1375 pinctrl_mdio1_default: mdio1_default { 1376 function = "MDIO1"; 1377 groups = "MDIO1"; 1378 }; 1379 1380 pinctrl_mdio2_default: mdio2_default { 1381 function = "MDIO2"; 1382 groups = "MDIO2"; 1383 }; 1384 1385 pinctrl_mdio3_default: mdio3_default { 1386 function = "MDIO3"; 1387 groups = "MDIO3"; 1388 }; 1389 1390 pinctrl_mdio4_default: mdio4_default { 1391 function = "MDIO4"; 1392 groups = "MDIO4"; 1393 }; 1394 1395 pinctrl_rmii1_default: rmii1_default { 1396 function = "RMII1"; 1397 groups = "RMII1"; 1398 }; 1399 1400 pinctrl_rmii2_default: rmii2_default { 1401 function = "RMII2"; 1402 groups = "RMII2"; 1403 }; 1404 1405 pinctrl_rmii3_default: rmii3_default { 1406 function = "RMII3"; 1407 groups = "RMII3"; 1408 }; 1409 1410 pinctrl_rmii4_default: rmii4_default { 1411 function = "RMII4"; 1412 groups = "RMII4"; 1413 }; 1414 1415 pinctrl_rmii1rclk_default: rmii1rclk_default { 1416 function = "RMII1RCLK"; 1417 groups = "RMII1RCLK"; 1418 }; 1419 1420 pinctrl_rmii2rclk_default: rmii2rclk_default { 1421 function = "RMII2RCLK"; 1422 groups = "RMII2RCLK"; 1423 }; 1424 1425 pinctrl_rmii3rclk_default: rmii3rclk_default { 1426 function = "RMII3RCLK"; 1427 groups = "RMII3RCLK"; 1428 }; 1429 1430 pinctrl_rmii4rclk_default: rmii4rclk_default { 1431 function = "RMII4RCLK"; 1432 groups = "RMII4RCLK"; 1433 }; 1434 1435 pinctrl_ncts1_default: ncts1_default { 1436 function = "NCTS1"; 1437 groups = "NCTS1"; 1438 }; 1439 1440 pinctrl_ncts2_default: ncts2_default { 1441 function = "NCTS2"; 1442 groups = "NCTS2"; 1443 }; 1444 1445 pinctrl_ncts3_default: ncts3_default { 1446 function = "NCTS3"; 1447 groups = "NCTS3"; 1448 }; 1449 1450 pinctrl_ncts4_default: ncts4_default { 1451 function = "NCTS4"; 1452 groups = "NCTS4"; 1453 }; 1454 1455 pinctrl_ndcd1_default: ndcd1_default { 1456 function = "NDCD1"; 1457 groups = "NDCD1"; 1458 }; 1459 1460 pinctrl_ndcd2_default: ndcd2_default { 1461 function = "NDCD2"; 1462 groups = "NDCD2"; 1463 }; 1464 1465 pinctrl_ndcd3_default: ndcd3_default { 1466 function = "NDCD3"; 1467 groups = "NDCD3"; 1468 }; 1469 1470 pinctrl_ndcd4_default: ndcd4_default { 1471 function = "NDCD4"; 1472 groups = "NDCD4"; 1473 }; 1474 1475 pinctrl_ndsr1_default: ndsr1_default { 1476 function = "NDSR1"; 1477 groups = "NDSR1"; 1478 }; 1479 1480 pinctrl_ndsr2_default: ndsr2_default { 1481 function = "NDSR2"; 1482 groups = "NDSR2"; 1483 }; 1484 1485 pinctrl_ndsr3_default: ndsr3_default { 1486 function = "NDSR3"; 1487 groups = "NDSR3"; 1488 }; 1489 1490 pinctrl_ndsr4_default: ndsr4_default { 1491 function = "NDSR4"; 1492 groups = "NDSR4"; 1493 }; 1494 1495 pinctrl_ndtr1_default: ndtr1_default { 1496 function = "NDTR1"; 1497 groups = "NDTR1"; 1498 }; 1499 1500 pinctrl_ndtr2_default: ndtr2_default { 1501 function = "NDTR2"; 1502 groups = "NDTR2"; 1503 }; 1504 1505 pinctrl_ndtr3_default: ndtr3_default { 1506 function = "NDTR3"; 1507 groups = "NDTR3"; 1508 }; 1509 1510 pinctrl_ndtr4_default: ndtr4_default { 1511 function = "NDTR4"; 1512 groups = "NDTR4"; 1513 }; 1514 1515 pinctrl_nri1_default: nri1_default { 1516 function = "NRI1"; 1517 groups = "NRI1"; 1518 }; 1519 1520 pinctrl_nri2_default: nri2_default { 1521 function = "NRI2"; 1522 groups = "NRI2"; 1523 }; 1524 1525 pinctrl_nri3_default: nri3_default { 1526 function = "NRI3"; 1527 groups = "NRI3"; 1528 }; 1529 1530 pinctrl_nri4_default: nri4_default { 1531 function = "NRI4"; 1532 groups = "NRI4"; 1533 }; 1534 1535 pinctrl_nrts1_default: nrts1_default { 1536 function = "NRTS1"; 1537 groups = "NRTS1"; 1538 }; 1539 1540 pinctrl_nrts2_default: nrts2_default { 1541 function = "NRTS2"; 1542 groups = "NRTS2"; 1543 }; 1544 1545 pinctrl_nrts3_default: nrts3_default { 1546 function = "NRTS3"; 1547 groups = "NRTS3"; 1548 }; 1549 1550 pinctrl_nrts4_default: nrts4_default { 1551 function = "NRTS4"; 1552 groups = "NRTS4"; 1553 }; 1554 1555 pinctrl_oscclk_default: oscclk_default { 1556 function = "OSCCLK"; 1557 groups = "OSCCLK"; 1558 }; 1559 1560 pinctrl_pewake_default: pewake_default { 1561 function = "PEWAKE"; 1562 groups = "PEWAKE"; 1563 }; 1564 1565 pinctrl_pnor_default: pnor_default { 1566 function = "PNOR"; 1567 groups = "PNOR"; 1568 }; 1569 1570 pinctrl_pwm0_default: pwm0_default { 1571 function = "PWM0"; 1572 groups = "PWM0"; 1573 }; 1574 1575 pinctrl_pwm1_default: pwm1_default { 1576 function = "PWM1"; 1577 groups = "PWM1"; 1578 }; 1579 1580 pinctrl_pwm2_default: pwm2_default { 1581 function = "PWM2"; 1582 groups = "PWM2"; 1583 }; 1584 1585 pinctrl_pwm3_default: pwm3_default { 1586 function = "PWM3"; 1587 groups = "PWM3"; 1588 }; 1589 1590 pinctrl_pwm4_default: pwm4_default { 1591 function = "PWM4"; 1592 groups = "PWM4"; 1593 }; 1594 1595 pinctrl_pwm5_default: pwm5_default { 1596 function = "PWM5"; 1597 groups = "PWM5"; 1598 }; 1599 1600 pinctrl_pwm6_default: pwm6_default { 1601 function = "PWM6"; 1602 groups = "PWM6"; 1603 }; 1604 1605 pinctrl_pwm7_default: pwm7_default { 1606 function = "PWM7"; 1607 groups = "PWM7"; 1608 }; 1609 1610 pinctrl_rgmii1_default: rgmii1_default { 1611 function = "RGMII1"; 1612 groups = "RGMII1"; 1613 }; 1614 1615 pinctrl_rgmii2_default: rgmii2_default { 1616 function = "RGMII2"; 1617 groups = "RGMII2"; 1618 }; 1619 1620 pinctrl_rgmii3_default: rgmii3_default { 1621 function = "RGMII3"; 1622 groups = "RGMII3"; 1623 }; 1624 1625 pinctrl_rgmii4_default: rgmii4_default { 1626 function = "RGMII4"; 1627 groups = "RGMII4"; 1628 }; 1629 1630 pinctrl_rmii1_default: rmii1_default { 1631 function = "RMII1"; 1632 groups = "RMII1"; 1633 }; 1634 1635 pinctrl_rmii2_default: rmii2_default { 1636 function = "RMII2"; 1637 groups = "RMII2"; 1638 }; 1639 1640 pinctrl_rxd1_default: rxd1_default { 1641 function = "RXD1"; 1642 groups = "RXD1"; 1643 }; 1644 1645 pinctrl_rxd2_default: rxd2_default { 1646 function = "RXD2"; 1647 groups = "RXD2"; 1648 }; 1649 1650 pinctrl_rxd3_default: rxd3_default { 1651 function = "RXD3"; 1652 groups = "RXD3"; 1653 }; 1654 1655 pinctrl_rxd4_default: rxd4_default { 1656 function = "RXD4"; 1657 groups = "RXD4"; 1658 }; 1659 1660 pinctrl_salt1_default: salt1_default { 1661 function = "SALT1"; 1662 groups = "SALT1"; 1663 }; 1664 1665 pinctrl_salt10_default: salt10_default { 1666 function = "SALT10"; 1667 groups = "SALT10"; 1668 }; 1669 1670 pinctrl_salt11_default: salt11_default { 1671 function = "SALT11"; 1672 groups = "SALT11"; 1673 }; 1674 1675 pinctrl_salt12_default: salt12_default { 1676 function = "SALT12"; 1677 groups = "SALT12"; 1678 }; 1679 1680 pinctrl_salt13_default: salt13_default { 1681 function = "SALT13"; 1682 groups = "SALT13"; 1683 }; 1684 1685 pinctrl_salt14_default: salt14_default { 1686 function = "SALT14"; 1687 groups = "SALT14"; 1688 }; 1689 1690 pinctrl_salt2_default: salt2_default { 1691 function = "SALT2"; 1692 groups = "SALT2"; 1693 }; 1694 1695 pinctrl_salt3_default: salt3_default { 1696 function = "SALT3"; 1697 groups = "SALT3"; 1698 }; 1699 1700 pinctrl_salt4_default: salt4_default { 1701 function = "SALT4"; 1702 groups = "SALT4"; 1703 }; 1704 1705 pinctrl_salt5_default: salt5_default { 1706 function = "SALT5"; 1707 groups = "SALT5"; 1708 }; 1709 1710 pinctrl_salt6_default: salt6_default { 1711 function = "SALT6"; 1712 groups = "SALT6"; 1713 }; 1714 1715 pinctrl_salt7_default: salt7_default { 1716 function = "SALT7"; 1717 groups = "SALT7"; 1718 }; 1719 1720 pinctrl_salt8_default: salt8_default { 1721 function = "SALT8"; 1722 groups = "SALT8"; 1723 }; 1724 1725 pinctrl_salt9_default: salt9_default { 1726 function = "SALT9"; 1727 groups = "SALT9"; 1728 }; 1729 1730 pinctrl_scl1_default: scl1_default { 1731 function = "SCL1"; 1732 groups = "SCL1"; 1733 }; 1734 1735 pinctrl_scl2_default: scl2_default { 1736 function = "SCL2"; 1737 groups = "SCL2"; 1738 }; 1739 1740 pinctrl_sd1_default: sd1_default { 1741 function = "SD1"; 1742 groups = "SD1"; 1743 }; 1744 1745 pinctrl_sd2_default: sd2_default { 1746 function = "SD2"; 1747 groups = "SD2"; 1748 }; 1749 1750 pinctrl_emmc_default: emmc_default { 1751 function = "EMMC"; 1752 groups = "EMMC"; 1753 }; 1754 1755 pinctrl_emmcg8_default: emmcg8_default { 1756 function = "EMMCG8"; 1757 groups = "EMMCG8"; 1758 }; 1759 1760 pinctrl_sda1_default: sda1_default { 1761 function = "SDA1"; 1762 groups = "SDA1"; 1763 }; 1764 1765 pinctrl_sda2_default: sda2_default { 1766 function = "SDA2"; 1767 groups = "SDA2"; 1768 }; 1769 1770 pinctrl_sgps1_default: sgps1_default { 1771 function = "SGPS1"; 1772 groups = "SGPS1"; 1773 }; 1774 1775 pinctrl_sgps2_default: sgps2_default { 1776 function = "SGPS2"; 1777 groups = "SGPS2"; 1778 }; 1779 1780 pinctrl_sioonctrl_default: sioonctrl_default { 1781 function = "SIOONCTRL"; 1782 groups = "SIOONCTRL"; 1783 }; 1784 1785 pinctrl_siopbi_default: siopbi_default { 1786 function = "SIOPBI"; 1787 groups = "SIOPBI"; 1788 }; 1789 1790 pinctrl_siopbo_default: siopbo_default { 1791 function = "SIOPBO"; 1792 groups = "SIOPBO"; 1793 }; 1794 1795 pinctrl_siopwreq_default: siopwreq_default { 1796 function = "SIOPWREQ"; 1797 groups = "SIOPWREQ"; 1798 }; 1799 1800 pinctrl_siopwrgd_default: siopwrgd_default { 1801 function = "SIOPWRGD"; 1802 groups = "SIOPWRGD"; 1803 }; 1804 1805 pinctrl_sios3_default: sios3_default { 1806 function = "SIOS3"; 1807 groups = "SIOS3"; 1808 }; 1809 1810 pinctrl_sios5_default: sios5_default { 1811 function = "SIOS5"; 1812 groups = "SIOS5"; 1813 }; 1814 1815 pinctrl_siosci_default: siosci_default { 1816 function = "SIOSCI"; 1817 groups = "SIOSCI"; 1818 }; 1819 1820 pinctrl_spi1_default: spi1_default { 1821 function = "SPI1"; 1822 groups = "SPI1"; 1823 }; 1824 1825 pinctrl_spi1cs1_default: spi1cs1_default { 1826 function = "SPI1CS1"; 1827 groups = "SPI1CS1"; 1828 }; 1829 1830 pinctrl_spi1debug_default: spi1debug_default { 1831 function = "SPI1DEBUG"; 1832 groups = "SPI1DEBUG"; 1833 }; 1834 1835 pinctrl_spi1passthru_default: spi1passthru_default { 1836 function = "SPI1PASSTHRU"; 1837 groups = "SPI1PASSTHRU"; 1838 }; 1839 1840 pinctrl_spi2ck_default: spi2ck_default { 1841 function = "SPI2CK"; 1842 groups = "SPI2CK"; 1843 }; 1844 1845 pinctrl_spi2cs0_default: spi2cs0_default { 1846 function = "SPI2CS0"; 1847 groups = "SPI2CS0"; 1848 }; 1849 1850 pinctrl_spi2cs1_default: spi2cs1_default { 1851 function = "SPI2CS1"; 1852 groups = "SPI2CS1"; 1853 }; 1854 1855 pinctrl_spi2miso_default: spi2miso_default { 1856 function = "SPI2MISO"; 1857 groups = "SPI2MISO"; 1858 }; 1859 1860 pinctrl_spi2mosi_default: spi2mosi_default { 1861 function = "SPI2MOSI"; 1862 groups = "SPI2MOSI"; 1863 }; 1864 1865 pinctrl_timer3_default: timer3_default { 1866 function = "TIMER3"; 1867 groups = "TIMER3"; 1868 }; 1869 1870 pinctrl_timer4_default: timer4_default { 1871 function = "TIMER4"; 1872 groups = "TIMER4"; 1873 }; 1874 1875 pinctrl_timer5_default: timer5_default { 1876 function = "TIMER5"; 1877 groups = "TIMER5"; 1878 }; 1879 1880 pinctrl_timer6_default: timer6_default { 1881 function = "TIMER6"; 1882 groups = "TIMER6"; 1883 }; 1884 1885 pinctrl_timer7_default: timer7_default { 1886 function = "TIMER7"; 1887 groups = "TIMER7"; 1888 }; 1889 1890 pinctrl_timer8_default: timer8_default { 1891 function = "TIMER8"; 1892 groups = "TIMER8"; 1893 }; 1894 1895 pinctrl_txd1_default: txd1_default { 1896 function = "TXD1"; 1897 groups = "TXD1"; 1898 }; 1899 1900 pinctrl_txd2_default: txd2_default { 1901 function = "TXD2"; 1902 groups = "TXD2"; 1903 }; 1904 1905 pinctrl_txd3_default: txd3_default { 1906 function = "TXD3"; 1907 groups = "TXD3"; 1908 }; 1909 1910 pinctrl_txd4_default: txd4_default { 1911 function = "TXD4"; 1912 groups = "TXD4"; 1913 }; 1914 1915 pinctrl_uart6_default: uart6_default { 1916 function = "UART6"; 1917 groups = "UART6"; 1918 }; 1919 1920 pinctrl_usbcki_default: usbcki_default { 1921 function = "USBCKI"; 1922 groups = "USBCKI"; 1923 }; 1924 1925 pinctrl_usb2ah_default: usb2ah_default { 1926 function = "USB2AH"; 1927 groups = "USB2AH"; 1928 }; 1929 1930 pinctrl_usb11bhid_default: usb11bhid_default { 1931 function = "USB11BHID"; 1932 groups = "USB11BHID"; 1933 }; 1934 1935 pinctrl_usb2bh_default: usb2bh_default { 1936 function = "USB2BH"; 1937 groups = "USB2BH"; 1938 }; 1939 1940 pinctrl_vgabiosrom_default: vgabiosrom_default { 1941 function = "VGABIOSROM"; 1942 groups = "VGABIOSROM"; 1943 }; 1944 1945 pinctrl_vgahs_default: vgahs_default { 1946 function = "VGAHS"; 1947 groups = "VGAHS"; 1948 }; 1949 1950 pinctrl_vgavs_default: vgavs_default { 1951 function = "VGAVS"; 1952 groups = "VGAVS"; 1953 }; 1954 1955 pinctrl_vpi24_default: vpi24_default { 1956 function = "VPI24"; 1957 groups = "VPI24"; 1958 }; 1959 1960 pinctrl_vpo_default: vpo_default { 1961 function = "VPO"; 1962 groups = "VPO"; 1963 }; 1964 1965 pinctrl_wdtrst1_default: wdtrst1_default { 1966 function = "WDTRST1"; 1967 groups = "WDTRST1"; 1968 }; 1969 1970 pinctrl_wdtrst2_default: wdtrst2_default { 1971 function = "WDTRST2"; 1972 groups = "WDTRST2"; 1973 }; 1974 1975 pinctrl_pcie0rc_default: pcie0rc_default { 1976 function = "PCIE0RC"; 1977 groups = "PCIE0RC"; 1978 }; 1979 1980 pinctrl_pcie1rc_default: pcie1rc_default { 1981 function = "PCIE1RC"; 1982 groups = "PCIE1RC"; 1983 }; 1984}; 1985