1// SPDX-License-Identifier: GPL-2.0+ 2#include <dt-bindings/interrupt-controller/arm-gic.h> 3#include "skeleton.dtsi" 4 5/ { 6 model = "Aspeed BMC"; 7 compatible = "aspeed,ast2600"; 8 #address-cells = <1>; 9 #size-cells = <1>; 10 interrupt-parent = <&gic>; 11 12 aliases { 13 i2c0 = &i2c0; 14 i2c1 = &i2c1; 15 i2c2 = &i2c2; 16 i2c3 = &i2c3; 17 i2c4 = &i2c4; 18 i2c5 = &i2c5; 19 i2c6 = &i2c6; 20 i2c7 = &i2c7; 21 i2c8 = &i2c8; 22 i2c9 = &i2c9; 23 i2c10 = &i2c10; 24 i2c11 = &i2c11; 25 i2c12 = &i2c12; 26 i2c13 = &i2c13; 27 i2c14 = &i2c14; 28 i2c15 = &i2c15; 29 serial0 = &uart1; 30 serial1 = &uart2; 31 serial2 = &uart3; 32 serial3 = &uart4; 33 serial4 = &uart5; 34 serial5 = &uart6; 35 serial6 = &uart7; 36 serial7 = &uart8; 37 serial8 = &uart9; 38 serial9 = &uart10; 39 serial10 = &uart11; 40 serial11 = &uart12; 41 serial12 = &uart13; 42 }; 43 44 cpus { 45 #address-cells = <1>; 46 #size-cells = <0>; 47 enable-method = "aspeed,ast2600-smp"; 48 49 cpu@0 { 50 compatible = "arm,cortex-a7"; 51 device_type = "cpu"; 52 reg = <0>; 53 clock-frequency = <48000000>; 54 }; 55 56 cpu@1 { 57 compatible = "arm,cortex-a7"; 58 device_type = "cpu"; 59 reg = <1>; 60 clock-frequency = <48000000>; 61 }; 62 63 }; 64 65 timer { 66 compatible = "arm,armv7-timer"; 67 interrupt-parent = <&gic>; 68 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 69 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 70 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 71 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 72 clock-frequency = <25000000>; 73 }; 74 75 memory@80000000 { 76 device_type = "memory"; 77 reg = <0x80000000 0>; 78 }; 79 80 reserved-memory { 81 #address-cells = <1>; 82 #size-cells = <1>; 83 ranges; 84 85 gfx_memory: framebuffer { 86 size = <0x01000000>; 87 alignment = <0x01000000>; 88 compatible = "shared-dma-pool"; 89 reusable; 90 }; 91 92 video_memory: video { 93 size = <0x04000000>; 94 alignment = <0x01000000>; 95 compatible = "shared-dma-pool"; 96 no-map; 97 }; 98 }; 99 100 ahb { 101 compatible = "simple-bus"; 102 #address-cells = <1>; 103 #size-cells = <1>; 104 device_type = "soc"; 105 ranges; 106 107 gic: interrupt-controller@40461000 { 108 compatible = "arm,cortex-a7-gic"; 109 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 110 #interrupt-cells = <3>; 111 interrupt-controller; 112 interrupt-parent = <&gic>; 113 reg = <0x40461000 0x1000>, 114 <0x40462000 0x1000>, 115 <0x40464000 0x2000>, 116 <0x40466000 0x2000>; 117 }; 118 119 fmc: flash-controller@1e620000 { 120 reg = < 0x1e620000 0xc4 121 0x20000000 0x10000000 >; 122 #address-cells = <1>; 123 #size-cells = <0>; 124 compatible = "aspeed,ast2600-fmc"; 125 status = "disabled"; 126 interrupts = <19>; 127 clocks = <&scu ASPEED_CLK_AHB>; 128 flash@0 { 129 reg = < 0 >; 130 compatible = "jedec,spi-nor"; 131 status = "disabled"; 132 }; 133 flash@1 { 134 reg = < 1 >; 135 compatible = "jedec,spi-nor"; 136 status = "disabled"; 137 }; 138 flash@2 { 139 reg = < 2 >; 140 compatible = "jedec,spi-nor"; 141 status = "disabled"; 142 }; 143 }; 144 145 spi1: flash-controller@1e630000 { 146 reg = < 0x1e630000 0xc4 147 0x30000000 0x08000000 >; 148 #address-cells = <1>; 149 #size-cells = <0>; 150 compatible = "aspeed,ast2600-spi"; 151 clocks = <&scu ASPEED_CLK_AHB>; 152 status = "disabled"; 153 flash@0 { 154 reg = < 0 >; 155 compatible = "jedec,spi-nor"; 156 status = "disabled"; 157 }; 158 flash@1 { 159 reg = < 1 >; 160 compatible = "jedec,spi-nor"; 161 status = "disabled"; 162 }; 163 }; 164 165 spi2: flash-controller@1e631000 { 166 reg = < 0x1e631000 0xc4 167 0x38000000 0x08000000 >; 168 #address-cells = <1>; 169 #size-cells = <0>; 170 compatible = "aspeed,ast2600-spi"; 171 clocks = <&scu ASPEED_CLK_AHB>; 172 status = "disabled"; 173 flash@0 { 174 reg = < 0 >; 175 compatible = "jedec,spi-nor"; 176 status = "disabled"; 177 }; 178 flash@1 { 179 reg = < 1 >; 180 compatible = "jedec,spi-nor"; 181 status = "disabled"; 182 }; 183 }; 184 185 edac: sdram@1e6e0000 { 186 compatible = "aspeed,ast2600-sdram-edac"; 187 reg = <0x1e6e0000 0x174>; 188 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 189 }; 190 191 mdio: ethernet@1e650000 { 192 compatible = "aspeed,aspeed-mdio"; 193 reg = <0x1e650000 0x40>; 194 resets = <&rst ASPEED_RESET_MII>; 195 status = "disabled"; 196 }; 197 198 mac0: ethernet@1e660000 { 199 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 200 reg = <0x1e660000 0x180>, <0x1e650000 0x4>; 201 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 202 clocks = <&scu ASPEED_CLK_GATE_MAC1CLK>; 203 status = "disabled"; 204 }; 205 206 mac2: ftgmac@1e670000 { 207 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 208 reg = <0x1e670000 0x180>, <0x1e650010 0x4>; 209 #address-cells = <1>; 210 #size-cells = <0>; 211 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 212 clocks = <&scu ASPEED_CLK_GATE_MAC3CLK>; 213#if 0 214 phy-handle = <&phy0>; 215#endif 216 status = "disabled"; 217 }; 218 219 mac1: ftgmac@1e680000 { 220 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 221 reg = <0x1e680000 0x180>, <0x1e650008 0x4>; 222 #address-cells = <1>; 223 #size-cells = <0>; 224 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 225 clocks = <&scu ASPEED_CLK_GATE_MAC2CLK>; 226#if 0 227 phy-handle = <&phy0>; 228#endif 229 status = "disabled"; 230 }; 231 232 mac3: ftgmac@1e690000 { 233 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 234 reg = <0x1e690000 0x180>, <0x1e650018 0x4>; 235 #address-cells = <1>; 236 #size-cells = <0>; 237 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 238 clocks = <&scu ASPEED_CLK_GATE_MAC4CLK>; 239#if 0 240 phy-handle = <&phy0>; 241#endif 242 status = "disabled"; 243 }; 244 245 246 apb { 247 compatible = "simple-bus"; 248 #address-cells = <1>; 249 #size-cells = <1>; 250 ranges; 251 252 syscon: syscon@1e6e2000 { 253 compatible = "aspeed,g6-scu", "syscon", "simple-mfd"; 254 reg = <0x1e6e2000 0x1000>; 255 #address-cells = <1>; 256 #size-cells = <1>; 257 #clock-cells = <1>; 258 #reset-cells = <1>; 259 ranges = <0 0x1e6e2000 0x1000>; 260 261 pinctrl: pinctrl { 262 compatible = "aspeed,g6-pinctrl"; 263 aspeed,external-nodes = <&gfx &lhc>; 264 265 }; 266 267 vga_scratch: scratch { 268 compatible = "aspeed,bmc-misc"; 269 }; 270 271 scu_ic0: interrupt-controller@0 { 272 #interrupt-cells = <1>; 273 compatible = "aspeed,ast2600-scu-ic"; 274 reg = <0x560 0x10>; 275 interrupt-parent = <&gic>; 276 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 277 interrupt-controller; 278 }; 279 280 scu_ic1: interrupt-controller@1 { 281 #interrupt-cells = <1>; 282 compatible = "aspeed,ast2600-scu-ic"; 283 reg = <0x570 0x10>; 284 interrupt-parent = <&gic>; 285 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 286 interrupt-controller; 287 }; 288 289 }; 290 291 smp-memram@0 { 292 compatible = "aspeed,ast2600-smpmem", "syscon"; 293 reg = <0x1e6e2180 0x40>; 294 }; 295 296 gfx: display@1e6e6000 { 297 compatible = "aspeed,ast2500-gfx", "syscon"; 298 reg = <0x1e6e6000 0x1000>; 299 reg-io-width = <4>; 300 }; 301 302 uart1: serial@1e783000 { 303 compatible = "ns16550a"; 304 reg = <0x1e783000 0x20>; 305 reg-shift = <2>; 306 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 307 clocks = <&scu ASPEED_CLK_GATE_UART1CLK>; 308 no-loopback-test; 309 status = "disabled"; 310 }; 311 312 uart5: serial@1e784000 { 313 compatible = "ns16550a"; 314 reg = <0x1e784000 0x1000>; 315 reg-shift = <2>; 316 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 317 clocks = <&scu ASPEED_CLK_GATE_UART5CLK>; 318 no-loopback-test; 319 status = "disabled"; 320 }; 321 322 wdt1: watchdog@1e785000 { 323 compatible = "aspeed,ast2600-wdt"; 324 reg = <0x1e785000 0x40>; 325 }; 326 327 wdt2: watchdog@1e785040 { 328 compatible = "aspeed,ast2600-wdt"; 329 reg = <0x1e785040 0x40>; 330 }; 331 332 wdt3: watchdog@1e785080 { 333 compatible = "aspeed,ast2600-wdt"; 334 reg = <0x1e785080 0x40>; 335 }; 336 337 wdt4: watchdog@1e7850C0 { 338 compatible = "aspeed,ast2600-wdt"; 339 reg = <0x1e7850C0 0x40>; 340 }; 341 342 lpc: lpc@1e789000 { 343 compatible = "aspeed,ast-lpc", "simple-mfd", "syscon"; 344 reg = <0x1e789000 0x200>; 345 346 #address-cells = <1>; 347 #size-cells = <1>; 348 ranges = <0x0 0x1e789000 0x1000>; 349 350 lpc_bmc: lpc-bmc@0 { 351 compatible = "aspeed,ast2600-lpc-bmc", "simple-mfd", "syscon"; 352 reg = <0x0 0x80>; 353 reg-io-width = <4>; 354 #address-cells = <1>; 355 #size-cells = <1>; 356 ranges = <0x0 0x0 0x80>; 357 358 kcs1: kcs1@0 { 359 compatible = "aspeed,ast2600-kcs-bmc"; 360 reg = <0x0 0x80>; 361 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 362 kcs_chan = <1>; 363 kcs_addr = <0xCA0>; 364 status = "disabled"; 365 }; 366 367 kcs2: kcs2@0 { 368 compatible = "aspeed,ast2600-kcs-bmc"; 369 reg = <0x0 0x80>; 370 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 371 kcs_chan = <2>; 372 kcs_addr = <0xCA8>; 373 status = "disabled"; 374 }; 375 376 kcs3: kcs3@0 { 377 compatible = "aspeed,ast2600-kcs-bmc"; 378 reg = <0x0 0x80>; 379 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 380 kcs_chan = <3>; 381 kcs_addr = <0xCA2>; 382 }; 383 384 kcs4: kcs4@0 { 385 compatible = "aspeed,ast2600-kcs-bmc"; 386 reg = <0x0 0x120>; 387 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 388 kcs_chan = <4>; 389 kcs_addr = <0xCA4>; 390 status = "disabled"; 391 }; 392 393 }; 394 395 lpc_host: lpc-host@80 { 396 compatible = "aspeed,ast2600-lpc-host", "simple-mfd", "syscon"; 397 reg = <0x80 0x1e0>; 398 reg-io-width = <4>; 399 400 #address-cells = <1>; 401 #size-cells = <1>; 402 ranges = <0x0 0x80 0x1e0>; 403 404 lpc_ctrl: lpc-ctrl@0 { 405 compatible = "aspeed,ast2600-lpc-ctrl"; 406 reg = <0x0 0x80>; 407 status = "disabled"; 408 }; 409 410 lpc_snoop: lpc-snoop@0 { 411 compatible = "aspeed,ast2600-lpc-snoop"; 412 reg = <0x0 0x80>; 413 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 414 snoop-ports = <0x80>; 415 status = "disabled"; 416 }; 417 418 lhc: lhc@20 { 419 compatible = "aspeed,ast2600-lhc"; 420 reg = <0x20 0x24 0x48 0x8>; 421 }; 422 423 lpc_reset: reset-controller@18 { 424 compatible = "aspeed,ast2600-lpc-reset"; 425 reg = <0x18 0x4>; 426 #reset-cells = <1>; 427 status = "disabled"; 428 }; 429 430 ibt: ibt@c0 { 431 compatible = "aspeed,ast2600-ibt-bmc"; 432 reg = <0xc0 0x18>; 433 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 434 status = "disabled"; 435 }; 436 437 sio_regs: regs { 438 compatible = "aspeed,bmc-misc"; 439 }; 440 441 mbox: mbox@180 { 442 compatible = "aspeed,ast2600-mbox"; 443 reg = <0x180 0x5c>; 444 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 445 #mbox-cells = <1>; 446 status = "disabled"; 447 }; 448 }; 449 }; 450 451 uart2: serial@1e78d000 { 452 compatible = "ns16550a"; 453 reg = <0x1e78d000 0x20>; 454 reg-shift = <2>; 455 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 456 clocks = <&scu ASPEED_CLK_GATE_UART2CLK>; 457 no-loopback-test; 458 status = "disabled"; 459 }; 460 461 uart3: serial@1e78e000 { 462 compatible = "ns16550a"; 463 reg = <0x1e78e000 0x20>; 464 reg-shift = <2>; 465 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 466 clocks = <&scu ASPEED_CLK_GATE_UART3CLK>; 467 no-loopback-test; 468 status = "disabled"; 469 }; 470 471 uart4: serial@1e78f000 { 472 compatible = "ns16550a"; 473 reg = <0x1e78f000 0x20>; 474 reg-shift = <2>; 475 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 476 clocks = <&scu ASPEED_CLK_GATE_UART4CLK>; 477 no-loopback-test; 478 status = "disabled"; 479 }; 480 481 i2c: bus@1e78a000 { 482 compatible = "simple-bus"; 483 #address-cells = <1>; 484 #size-cells = <1>; 485 ranges = <0 0x1e78a000 0x1000>; 486 }; 487 488 uart6: serial@1e790000 { 489 compatible = "ns16550a"; 490 reg = <0x1e790000 0x20>; 491 reg-shift = <2>; 492 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 493 clocks = <&scu ASPEED_CLK_GATE_UART6CLK>; 494 no-loopback-test; 495 status = "disabled"; 496 }; 497 498 uart7: serial@1e790100 { 499 compatible = "ns16550a"; 500 reg = <0x1e790100 0x20>; 501 reg-shift = <2>; 502 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 503 clocks = <&scu ASPEED_CLK_GATE_UART7CLK>; 504 no-loopback-test; 505 status = "disabled"; 506 }; 507 508 uart8: serial@1e790200 { 509 compatible = "ns16550a"; 510 reg = <0x1e790200 0x20>; 511 reg-shift = <2>; 512 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 513 clocks = <&scu ASPEED_CLK_GATE_UART8CLK>; 514 no-loopback-test; 515 status = "disabled"; 516 }; 517 518 uart9: serial@1e790300 { 519 compatible = "ns16550a"; 520 reg = <0x1e790300 0x20>; 521 reg-shift = <2>; 522 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 523 clocks = <&scu ASPEED_CLK_GATE_UART9CLK>; 524 no-loopback-test; 525 status = "disabled"; 526 }; 527 528 uart10: serial@1e790400 { 529 compatible = "ns16550a"; 530 reg = <0x1e790400 0x20>; 531 reg-shift = <2>; 532 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 533 clocks = <&scu ASPEED_CLK_GATE_UART10CLK>; 534 no-loopback-test; 535 status = "disabled"; 536 }; 537 538 uart11: serial@1e790500 { 539 compatible = "ns16550a"; 540 reg = <0x1e790400 0x20>; 541 reg-shift = <2>; 542 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 543 clocks = <&scu ASPEED_CLK_GATE_UART11CLK>; 544 no-loopback-test; 545 status = "disabled"; 546 }; 547 548 uart12: serial@1e790600 { 549 compatible = "ns16550a"; 550 reg = <0x1e790600 0x20>; 551 reg-shift = <2>; 552 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 553 clocks = <&scu ASPEED_CLK_GATE_UART12CLK>; 554 no-loopback-test; 555 status = "disabled"; 556 }; 557 558 uart13: serial@1e790700 { 559 compatible = "ns16550a"; 560 reg = <0x1e790700 0x20>; 561 reg-shift = <2>; 562 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 563 clocks = <&scu ASPEED_CLK_GATE_UART13CLK>; 564 no-loopback-test; 565 status = "disabled"; 566 }; 567 568 569 570 }; 571 572 }; 573 574}; 575 576&i2c { 577 i2cglobal: i2cg@00 { 578 compatible = "aspeed,ast2600-i2c-global", "syscon", "simple-mfd"; 579 reg = <0x0 0x40>; 580 581#if 0 582 new-mode; 583#endif 584 }; 585 586 i2c0: i2c@80 { 587 #address-cells = <1>; 588 #size-cells = <0>; 589 #interrupt-cells = <1>; 590 591 reg = <0x80 0x80 0xC00 0x20>; 592 compatible = "aspeed,ast2600-i2c-bus"; 593 bus-frequency = <100000>; 594 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 595 clocks = <&scu ASPEED_CLK_APB>; 596 }; 597 598 i2c1: i2c@100 { 599 #address-cells = <1>; 600 #size-cells = <0>; 601 #interrupt-cells = <1>; 602 603 reg = <0x100 0x80 0xC20 0x20>; 604 compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 605 bus-frequency = <100000>; 606 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 607 clocks = <&scu ASPEED_CLK_APB>; 608 }; 609 610 i2c2: i2c@180 { 611 #address-cells = <1>; 612 #size-cells = <0>; 613 #interrupt-cells = <1>; 614 615 reg = <0x180 0x80 0xC40 0x20>; 616 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 617 bus-frequency = <100000>; 618 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 619 clocks = <&scu ASPEED_CLK_APB>; 620 }; 621 622 i2c3: i2c@200 { 623 #address-cells = <1>; 624 #size-cells = <0>; 625 #interrupt-cells = <1>; 626 627 reg = <0x200 0x40 0xC60 0x20>; 628 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 629 bus-frequency = <100000>; 630 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 631 clocks = <&scu ASPEED_CLK_APB>; 632 }; 633 634 i2c4: i2c@280 { 635 #address-cells = <1>; 636 #size-cells = <0>; 637 #interrupt-cells = <1>; 638 639 reg = <0x280 0x80 0xC80 0x20>; 640 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 641 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 642 bus-frequency = <100000>; 643 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 644 clocks = <&scu ASPEED_CLK_APB>; 645 }; 646 647 i2c5: i2c@300 { 648 #address-cells = <1>; 649 #size-cells = <0>; 650 #interrupt-cells = <1>; 651 652 reg = <0x300 0x40 0xCA0 0x20>; 653 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 654 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 655 bus-frequency = <100000>; 656 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 657 clocks = <&scu ASPEED_CLK_APB>; 658 }; 659 660 i2c6: i2c@380 { 661 #address-cells = <1>; 662 #size-cells = <0>; 663 #interrupt-cells = <1>; 664 665 reg = <0x380 0x80 0xCC0 0x20>; 666 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 667 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 668 bus-frequency = <100000>; 669 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 670 clocks = <&scu ASPEED_CLK_APB>; 671 }; 672 673 i2c7: i2c@400 { 674 #address-cells = <1>; 675 #size-cells = <0>; 676 #interrupt-cells = <1>; 677 678 reg = <0x400 0x80 0xCE0 0x20>; 679 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 680 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 681 bus-frequency = <100000>; 682 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 683 clocks = <&scu ASPEED_CLK_APB>; 684 }; 685 686 i2c8: i2c@480 { 687 #address-cells = <1>; 688 #size-cells = <0>; 689 #interrupt-cells = <1>; 690 691 reg = <0x480 0x80 0xD00 0x20>; 692 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 693 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 694 bus-frequency = <100000>; 695 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 696 clocks = <&scu ASPEED_CLK_APB>; 697 }; 698 699 i2c9: i2c@500 { 700 #address-cells = <1>; 701 #size-cells = <0>; 702 #interrupt-cells = <1>; 703 704 reg = <0x500 0x80 0xD20 0x20>; 705 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 706 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 707 bus-frequency = <100000>; 708 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 709 clocks = <&scu ASPEED_CLK_APB>; 710 status = "disabled"; 711 }; 712 713 i2c10: i2c@580 { 714 #address-cells = <1>; 715 #size-cells = <0>; 716 #interrupt-cells = <1>; 717 718 reg = <0x580 0x80 0xD40 0x20>; 719 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 720 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 721 bus-frequency = <100000>; 722 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 723 clocks = <&scu ASPEED_CLK_APB>; 724 status = "disabled"; 725 }; 726 727 i2c11: i2c@600 { 728 #address-cells = <1>; 729 #size-cells = <0>; 730 #interrupt-cells = <1>; 731 732 reg = <0x600 0x80 0xD60 0x20>; 733 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 734 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 735 bus-frequency = <100000>; 736 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 737 clocks = <&scu ASPEED_CLK_APB>; 738 status = "disabled"; 739 }; 740 741 i2c12: i2c@680 { 742 #address-cells = <1>; 743 #size-cells = <0>; 744 #interrupt-cells = <1>; 745 746 reg = <0x680 0x80 0xD80 0x20>; 747 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 748 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 749 bus-frequency = <100000>; 750 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 751 clocks = <&scu ASPEED_CLK_APB>; 752 status = "disabled"; 753 }; 754 755 i2c13: i2c@700 { 756 #address-cells = <1>; 757 #size-cells = <0>; 758 #interrupt-cells = <1>; 759 760 reg = <0x700 0x80 0xDA0 0x20>; 761 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 762 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 763 bus-frequency = <100000>; 764 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 765 clocks = <&scu ASPEED_CLK_APB>; 766 status = "disabled"; 767 }; 768 769 i2c14: i2c@780 { 770 #address-cells = <1>; 771 #size-cells = <0>; 772 #interrupt-cells = <1>; 773 774 reg = <0x780 0x80 0xDC0 0x20>; 775 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 776 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 777 bus-frequency = <100000>; 778 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 779 clocks = <&scu ASPEED_CLK_APB>; 780 status = "disabled"; 781 }; 782 783 i2c15: i2c@800 { 784 #address-cells = <1>; 785 #size-cells = <0>; 786 #interrupt-cells = <1>; 787 788 reg = <0x800 0x80 0xDE0 0x20>; 789 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 790 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 791 bus-frequency = <100000>; 792 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 793 clocks = <&scu ASPEED_CLK_APB>; 794 status = "disabled"; 795 }; 796 797}; 798 799&pinctrl { 800 pinctrl_acpi_default: acpi_default { 801 function = "ACPI"; 802 groups = "ACPI"; 803 }; 804 805 pinctrl_adc0_default: adc0_default { 806 function = "ADC0"; 807 groups = "ADC0"; 808 }; 809 810 pinctrl_adc1_default: adc1_default { 811 function = "ADC1"; 812 groups = "ADC1"; 813 }; 814 815 pinctrl_adc10_default: adc10_default { 816 function = "ADC10"; 817 groups = "ADC10"; 818 }; 819 820 pinctrl_adc11_default: adc11_default { 821 function = "ADC11"; 822 groups = "ADC11"; 823 }; 824 825 pinctrl_adc12_default: adc12_default { 826 function = "ADC12"; 827 groups = "ADC12"; 828 }; 829 830 pinctrl_adc13_default: adc13_default { 831 function = "ADC13"; 832 groups = "ADC13"; 833 }; 834 835 pinctrl_adc14_default: adc14_default { 836 function = "ADC14"; 837 groups = "ADC14"; 838 }; 839 840 pinctrl_adc15_default: adc15_default { 841 function = "ADC15"; 842 groups = "ADC15"; 843 }; 844 845 pinctrl_adc2_default: adc2_default { 846 function = "ADC2"; 847 groups = "ADC2"; 848 }; 849 850 pinctrl_adc3_default: adc3_default { 851 function = "ADC3"; 852 groups = "ADC3"; 853 }; 854 855 pinctrl_adc4_default: adc4_default { 856 function = "ADC4"; 857 groups = "ADC4"; 858 }; 859 860 pinctrl_adc5_default: adc5_default { 861 function = "ADC5"; 862 groups = "ADC5"; 863 }; 864 865 pinctrl_adc6_default: adc6_default { 866 function = "ADC6"; 867 groups = "ADC6"; 868 }; 869 870 pinctrl_adc7_default: adc7_default { 871 function = "ADC7"; 872 groups = "ADC7"; 873 }; 874 875 pinctrl_adc8_default: adc8_default { 876 function = "ADC8"; 877 groups = "ADC8"; 878 }; 879 880 pinctrl_adc9_default: adc9_default { 881 function = "ADC9"; 882 groups = "ADC9"; 883 }; 884 885 pinctrl_bmcint_default: bmcint_default { 886 function = "BMCINT"; 887 groups = "BMCINT"; 888 }; 889 890 pinctrl_ddcclk_default: ddcclk_default { 891 function = "DDCCLK"; 892 groups = "DDCCLK"; 893 }; 894 895 pinctrl_ddcdat_default: ddcdat_default { 896 function = "DDCDAT"; 897 groups = "DDCDAT"; 898 }; 899 900 pinctrl_espi_default: espi_default { 901 function = "ESPI"; 902 groups = "ESPI"; 903 }; 904 905 pinctrl_fwspics1_default: fwspics1_default { 906 function = "FWSPICS1"; 907 groups = "FWSPICS1"; 908 }; 909 910 pinctrl_fwspics2_default: fwspics2_default { 911 function = "FWSPICS2"; 912 groups = "FWSPICS2"; 913 }; 914 915 pinctrl_gpid0_default: gpid0_default { 916 function = "GPID0"; 917 groups = "GPID0"; 918 }; 919 920 pinctrl_gpid2_default: gpid2_default { 921 function = "GPID2"; 922 groups = "GPID2"; 923 }; 924 925 pinctrl_gpid4_default: gpid4_default { 926 function = "GPID4"; 927 groups = "GPID4"; 928 }; 929 930 pinctrl_gpid6_default: gpid6_default { 931 function = "GPID6"; 932 groups = "GPID6"; 933 }; 934 935 pinctrl_gpie0_default: gpie0_default { 936 function = "GPIE0"; 937 groups = "GPIE0"; 938 }; 939 940 pinctrl_gpie2_default: gpie2_default { 941 function = "GPIE2"; 942 groups = "GPIE2"; 943 }; 944 945 pinctrl_gpie4_default: gpie4_default { 946 function = "GPIE4"; 947 groups = "GPIE4"; 948 }; 949 950 pinctrl_gpie6_default: gpie6_default { 951 function = "GPIE6"; 952 groups = "GPIE6"; 953 }; 954 955 pinctrl_i2c10_default: i2c10_default { 956 function = "I2C10"; 957 groups = "I2C10"; 958 }; 959 960 pinctrl_i2c11_default: i2c11_default { 961 function = "I2C11"; 962 groups = "I2C11"; 963 }; 964 965 pinctrl_i2c12_default: i2c12_default { 966 function = "I2C12"; 967 groups = "I2C12"; 968 }; 969 970 pinctrl_i2c13_default: i2c13_default { 971 function = "I2C13"; 972 groups = "I2C13"; 973 }; 974 975 pinctrl_i2c14_default: i2c14_default { 976 function = "I2C14"; 977 groups = "I2C14"; 978 }; 979 980 pinctrl_i2c3_default: i2c3_default { 981 function = "I2C3"; 982 groups = "I2C3"; 983 }; 984 985 pinctrl_i2c4_default: i2c4_default { 986 function = "I2C4"; 987 groups = "I2C4"; 988 }; 989 990 pinctrl_i2c5_default: i2c5_default { 991 function = "I2C5"; 992 groups = "I2C5"; 993 }; 994 995 pinctrl_i2c6_default: i2c6_default { 996 function = "I2C6"; 997 groups = "I2C6"; 998 }; 999 1000 pinctrl_i2c7_default: i2c7_default { 1001 function = "I2C7"; 1002 groups = "I2C7"; 1003 }; 1004 1005 pinctrl_i2c8_default: i2c8_default { 1006 function = "I2C8"; 1007 groups = "I2C8"; 1008 }; 1009 1010 pinctrl_i2c9_default: i2c9_default { 1011 function = "I2C9"; 1012 groups = "I2C9"; 1013 }; 1014 1015 pinctrl_lad0_default: lad0_default { 1016 function = "LAD0"; 1017 groups = "LAD0"; 1018 }; 1019 1020 pinctrl_lad1_default: lad1_default { 1021 function = "LAD1"; 1022 groups = "LAD1"; 1023 }; 1024 1025 pinctrl_lad2_default: lad2_default { 1026 function = "LAD2"; 1027 groups = "LAD2"; 1028 }; 1029 1030 pinctrl_lad3_default: lad3_default { 1031 function = "LAD3"; 1032 groups = "LAD3"; 1033 }; 1034 1035 pinctrl_lclk_default: lclk_default { 1036 function = "LCLK"; 1037 groups = "LCLK"; 1038 }; 1039 1040 pinctrl_lframe_default: lframe_default { 1041 function = "LFRAME"; 1042 groups = "LFRAME"; 1043 }; 1044 1045 pinctrl_lpchc_default: lpchc_default { 1046 function = "LPCHC"; 1047 groups = "LPCHC"; 1048 }; 1049 1050 pinctrl_lpcpd_default: lpcpd_default { 1051 function = "LPCPD"; 1052 groups = "LPCPD"; 1053 }; 1054 1055 pinctrl_lpcplus_default: lpcplus_default { 1056 function = "LPCPLUS"; 1057 groups = "LPCPLUS"; 1058 }; 1059 1060 pinctrl_lpcpme_default: lpcpme_default { 1061 function = "LPCPME"; 1062 groups = "LPCPME"; 1063 }; 1064 1065 pinctrl_lpcrst_default: lpcrst_default { 1066 function = "LPCRST"; 1067 groups = "LPCRST"; 1068 }; 1069 1070 pinctrl_lpcsmi_default: lpcsmi_default { 1071 function = "LPCSMI"; 1072 groups = "LPCSMI"; 1073 }; 1074 1075 pinctrl_lsirq_default: lsirq_default { 1076 function = "LSIRQ"; 1077 groups = "LSIRQ"; 1078 }; 1079 1080 pinctrl_mac1link_default: mac1link_default { 1081 function = "MAC1LINK"; 1082 groups = "MAC1LINK"; 1083 }; 1084 1085 pinctrl_mac2link_default: mac2link_default { 1086 function = "MAC2LINK"; 1087 groups = "MAC2LINK"; 1088 }; 1089 1090 pinctrl_mac3link_default: mac3link_default { 1091 function = "MAC3LINK"; 1092 groups = "MAC3LINK"; 1093 }; 1094 1095 pinctrl_mac4link_default: mac4link_default { 1096 function = "MAC4LINK"; 1097 groups = "MAC4LINK"; 1098 }; 1099 1100 pinctrl_mdio1_default: mdio1_default { 1101 function = "MDIO1"; 1102 groups = "MDIO1"; 1103 }; 1104 1105 pinctrl_mdio2_default: mdio2_default { 1106 function = "MDIO2"; 1107 groups = "MDIO2"; 1108 }; 1109 1110 pinctrl_mdio3_default: mdio3_default { 1111 function = "MDIO3"; 1112 groups = "MDIO3"; 1113 }; 1114 1115 pinctrl_mdio4_default: mdio4_default { 1116 function = "MDIO4"; 1117 groups = "MDIO4"; 1118 }; 1119 1120 pinctrl_ncts1_default: ncts1_default { 1121 function = "NCTS1"; 1122 groups = "NCTS1"; 1123 }; 1124 1125 pinctrl_ncts2_default: ncts2_default { 1126 function = "NCTS2"; 1127 groups = "NCTS2"; 1128 }; 1129 1130 pinctrl_ncts3_default: ncts3_default { 1131 function = "NCTS3"; 1132 groups = "NCTS3"; 1133 }; 1134 1135 pinctrl_ncts4_default: ncts4_default { 1136 function = "NCTS4"; 1137 groups = "NCTS4"; 1138 }; 1139 1140 pinctrl_ndcd1_default: ndcd1_default { 1141 function = "NDCD1"; 1142 groups = "NDCD1"; 1143 }; 1144 1145 pinctrl_ndcd2_default: ndcd2_default { 1146 function = "NDCD2"; 1147 groups = "NDCD2"; 1148 }; 1149 1150 pinctrl_ndcd3_default: ndcd3_default { 1151 function = "NDCD3"; 1152 groups = "NDCD3"; 1153 }; 1154 1155 pinctrl_ndcd4_default: ndcd4_default { 1156 function = "NDCD4"; 1157 groups = "NDCD4"; 1158 }; 1159 1160 pinctrl_ndsr1_default: ndsr1_default { 1161 function = "NDSR1"; 1162 groups = "NDSR1"; 1163 }; 1164 1165 pinctrl_ndsr2_default: ndsr2_default { 1166 function = "NDSR2"; 1167 groups = "NDSR2"; 1168 }; 1169 1170 pinctrl_ndsr3_default: ndsr3_default { 1171 function = "NDSR3"; 1172 groups = "NDSR3"; 1173 }; 1174 1175 pinctrl_ndsr4_default: ndsr4_default { 1176 function = "NDSR4"; 1177 groups = "NDSR4"; 1178 }; 1179 1180 pinctrl_ndtr1_default: ndtr1_default { 1181 function = "NDTR1"; 1182 groups = "NDTR1"; 1183 }; 1184 1185 pinctrl_ndtr2_default: ndtr2_default { 1186 function = "NDTR2"; 1187 groups = "NDTR2"; 1188 }; 1189 1190 pinctrl_ndtr3_default: ndtr3_default { 1191 function = "NDTR3"; 1192 groups = "NDTR3"; 1193 }; 1194 1195 pinctrl_ndtr4_default: ndtr4_default { 1196 function = "NDTR4"; 1197 groups = "NDTR4"; 1198 }; 1199 1200 pinctrl_nri1_default: nri1_default { 1201 function = "NRI1"; 1202 groups = "NRI1"; 1203 }; 1204 1205 pinctrl_nri2_default: nri2_default { 1206 function = "NRI2"; 1207 groups = "NRI2"; 1208 }; 1209 1210 pinctrl_nri3_default: nri3_default { 1211 function = "NRI3"; 1212 groups = "NRI3"; 1213 }; 1214 1215 pinctrl_nri4_default: nri4_default { 1216 function = "NRI4"; 1217 groups = "NRI4"; 1218 }; 1219 1220 pinctrl_nrts1_default: nrts1_default { 1221 function = "NRTS1"; 1222 groups = "NRTS1"; 1223 }; 1224 1225 pinctrl_nrts2_default: nrts2_default { 1226 function = "NRTS2"; 1227 groups = "NRTS2"; 1228 }; 1229 1230 pinctrl_nrts3_default: nrts3_default { 1231 function = "NRTS3"; 1232 groups = "NRTS3"; 1233 }; 1234 1235 pinctrl_nrts4_default: nrts4_default { 1236 function = "NRTS4"; 1237 groups = "NRTS4"; 1238 }; 1239 1240 pinctrl_oscclk_default: oscclk_default { 1241 function = "OSCCLK"; 1242 groups = "OSCCLK"; 1243 }; 1244 1245 pinctrl_pewake_default: pewake_default { 1246 function = "PEWAKE"; 1247 groups = "PEWAKE"; 1248 }; 1249 1250 pinctrl_pnor_default: pnor_default { 1251 function = "PNOR"; 1252 groups = "PNOR"; 1253 }; 1254 1255 pinctrl_pwm0_default: pwm0_default { 1256 function = "PWM0"; 1257 groups = "PWM0"; 1258 }; 1259 1260 pinctrl_pwm1_default: pwm1_default { 1261 function = "PWM1"; 1262 groups = "PWM1"; 1263 }; 1264 1265 pinctrl_pwm2_default: pwm2_default { 1266 function = "PWM2"; 1267 groups = "PWM2"; 1268 }; 1269 1270 pinctrl_pwm3_default: pwm3_default { 1271 function = "PWM3"; 1272 groups = "PWM3"; 1273 }; 1274 1275 pinctrl_pwm4_default: pwm4_default { 1276 function = "PWM4"; 1277 groups = "PWM4"; 1278 }; 1279 1280 pinctrl_pwm5_default: pwm5_default { 1281 function = "PWM5"; 1282 groups = "PWM5"; 1283 }; 1284 1285 pinctrl_pwm6_default: pwm6_default { 1286 function = "PWM6"; 1287 groups = "PWM6"; 1288 }; 1289 1290 pinctrl_pwm7_default: pwm7_default { 1291 function = "PWM7"; 1292 groups = "PWM7"; 1293 }; 1294 1295 pinctrl_rgmii1_default: rgmii1_default { 1296 function = "RGMII1"; 1297 groups = "RGMII1"; 1298 }; 1299 1300 pinctrl_rgmii2_default: rgmii2_default { 1301 function = "RGMII2"; 1302 groups = "RGMII2"; 1303 }; 1304 1305 pinctrl_rmii1_default: rmii1_default { 1306 function = "RMII1"; 1307 groups = "RMII1"; 1308 }; 1309 1310 pinctrl_rmii2_default: rmii2_default { 1311 function = "RMII2"; 1312 groups = "RMII2"; 1313 }; 1314 1315 pinctrl_rxd1_default: rxd1_default { 1316 function = "RXD1"; 1317 groups = "RXD1"; 1318 }; 1319 1320 pinctrl_rxd2_default: rxd2_default { 1321 function = "RXD2"; 1322 groups = "RXD2"; 1323 }; 1324 1325 pinctrl_rxd3_default: rxd3_default { 1326 function = "RXD3"; 1327 groups = "RXD3"; 1328 }; 1329 1330 pinctrl_rxd4_default: rxd4_default { 1331 function = "RXD4"; 1332 groups = "RXD4"; 1333 }; 1334 1335 pinctrl_salt1_default: salt1_default { 1336 function = "SALT1"; 1337 groups = "SALT1"; 1338 }; 1339 1340 pinctrl_salt10_default: salt10_default { 1341 function = "SALT10"; 1342 groups = "SALT10"; 1343 }; 1344 1345 pinctrl_salt11_default: salt11_default { 1346 function = "SALT11"; 1347 groups = "SALT11"; 1348 }; 1349 1350 pinctrl_salt12_default: salt12_default { 1351 function = "SALT12"; 1352 groups = "SALT12"; 1353 }; 1354 1355 pinctrl_salt13_default: salt13_default { 1356 function = "SALT13"; 1357 groups = "SALT13"; 1358 }; 1359 1360 pinctrl_salt14_default: salt14_default { 1361 function = "SALT14"; 1362 groups = "SALT14"; 1363 }; 1364 1365 pinctrl_salt2_default: salt2_default { 1366 function = "SALT2"; 1367 groups = "SALT2"; 1368 }; 1369 1370 pinctrl_salt3_default: salt3_default { 1371 function = "SALT3"; 1372 groups = "SALT3"; 1373 }; 1374 1375 pinctrl_salt4_default: salt4_default { 1376 function = "SALT4"; 1377 groups = "SALT4"; 1378 }; 1379 1380 pinctrl_salt5_default: salt5_default { 1381 function = "SALT5"; 1382 groups = "SALT5"; 1383 }; 1384 1385 pinctrl_salt6_default: salt6_default { 1386 function = "SALT6"; 1387 groups = "SALT6"; 1388 }; 1389 1390 pinctrl_salt7_default: salt7_default { 1391 function = "SALT7"; 1392 groups = "SALT7"; 1393 }; 1394 1395 pinctrl_salt8_default: salt8_default { 1396 function = "SALT8"; 1397 groups = "SALT8"; 1398 }; 1399 1400 pinctrl_salt9_default: salt9_default { 1401 function = "SALT9"; 1402 groups = "SALT9"; 1403 }; 1404 1405 pinctrl_scl1_default: scl1_default { 1406 function = "SCL1"; 1407 groups = "SCL1"; 1408 }; 1409 1410 pinctrl_scl2_default: scl2_default { 1411 function = "SCL2"; 1412 groups = "SCL2"; 1413 }; 1414 1415 pinctrl_sd1_default: sd1_default { 1416 function = "SD1"; 1417 groups = "SD1"; 1418 }; 1419 1420 pinctrl_sd2_default: sd2_default { 1421 function = "SD2"; 1422 groups = "SD2"; 1423 }; 1424 1425 pinctrl_sda1_default: sda1_default { 1426 function = "SDA1"; 1427 groups = "SDA1"; 1428 }; 1429 1430 pinctrl_sda2_default: sda2_default { 1431 function = "SDA2"; 1432 groups = "SDA2"; 1433 }; 1434 1435 pinctrl_sgps1_default: sgps1_default { 1436 function = "SGPS1"; 1437 groups = "SGPS1"; 1438 }; 1439 1440 pinctrl_sgps2_default: sgps2_default { 1441 function = "SGPS2"; 1442 groups = "SGPS2"; 1443 }; 1444 1445 pinctrl_sioonctrl_default: sioonctrl_default { 1446 function = "SIOONCTRL"; 1447 groups = "SIOONCTRL"; 1448 }; 1449 1450 pinctrl_siopbi_default: siopbi_default { 1451 function = "SIOPBI"; 1452 groups = "SIOPBI"; 1453 }; 1454 1455 pinctrl_siopbo_default: siopbo_default { 1456 function = "SIOPBO"; 1457 groups = "SIOPBO"; 1458 }; 1459 1460 pinctrl_siopwreq_default: siopwreq_default { 1461 function = "SIOPWREQ"; 1462 groups = "SIOPWREQ"; 1463 }; 1464 1465 pinctrl_siopwrgd_default: siopwrgd_default { 1466 function = "SIOPWRGD"; 1467 groups = "SIOPWRGD"; 1468 }; 1469 1470 pinctrl_sios3_default: sios3_default { 1471 function = "SIOS3"; 1472 groups = "SIOS3"; 1473 }; 1474 1475 pinctrl_sios5_default: sios5_default { 1476 function = "SIOS5"; 1477 groups = "SIOS5"; 1478 }; 1479 1480 pinctrl_siosci_default: siosci_default { 1481 function = "SIOSCI"; 1482 groups = "SIOSCI"; 1483 }; 1484 1485 pinctrl_spi1_default: spi1_default { 1486 function = "SPI1"; 1487 groups = "SPI1"; 1488 }; 1489 1490 pinctrl_spi1cs1_default: spi1cs1_default { 1491 function = "SPI1CS1"; 1492 groups = "SPI1CS1"; 1493 }; 1494 1495 pinctrl_spi1debug_default: spi1debug_default { 1496 function = "SPI1DEBUG"; 1497 groups = "SPI1DEBUG"; 1498 }; 1499 1500 pinctrl_spi1passthru_default: spi1passthru_default { 1501 function = "SPI1PASSTHRU"; 1502 groups = "SPI1PASSTHRU"; 1503 }; 1504 1505 pinctrl_spi2ck_default: spi2ck_default { 1506 function = "SPI2CK"; 1507 groups = "SPI2CK"; 1508 }; 1509 1510 pinctrl_spi2cs0_default: spi2cs0_default { 1511 function = "SPI2CS0"; 1512 groups = "SPI2CS0"; 1513 }; 1514 1515 pinctrl_spi2cs1_default: spi2cs1_default { 1516 function = "SPI2CS1"; 1517 groups = "SPI2CS1"; 1518 }; 1519 1520 pinctrl_spi2miso_default: spi2miso_default { 1521 function = "SPI2MISO"; 1522 groups = "SPI2MISO"; 1523 }; 1524 1525 pinctrl_spi2mosi_default: spi2mosi_default { 1526 function = "SPI2MOSI"; 1527 groups = "SPI2MOSI"; 1528 }; 1529 1530 pinctrl_timer3_default: timer3_default { 1531 function = "TIMER3"; 1532 groups = "TIMER3"; 1533 }; 1534 1535 pinctrl_timer4_default: timer4_default { 1536 function = "TIMER4"; 1537 groups = "TIMER4"; 1538 }; 1539 1540 pinctrl_timer5_default: timer5_default { 1541 function = "TIMER5"; 1542 groups = "TIMER5"; 1543 }; 1544 1545 pinctrl_timer6_default: timer6_default { 1546 function = "TIMER6"; 1547 groups = "TIMER6"; 1548 }; 1549 1550 pinctrl_timer7_default: timer7_default { 1551 function = "TIMER7"; 1552 groups = "TIMER7"; 1553 }; 1554 1555 pinctrl_timer8_default: timer8_default { 1556 function = "TIMER8"; 1557 groups = "TIMER8"; 1558 }; 1559 1560 pinctrl_txd1_default: txd1_default { 1561 function = "TXD1"; 1562 groups = "TXD1"; 1563 }; 1564 1565 pinctrl_txd2_default: txd2_default { 1566 function = "TXD2"; 1567 groups = "TXD2"; 1568 }; 1569 1570 pinctrl_txd3_default: txd3_default { 1571 function = "TXD3"; 1572 groups = "TXD3"; 1573 }; 1574 1575 pinctrl_txd4_default: txd4_default { 1576 function = "TXD4"; 1577 groups = "TXD4"; 1578 }; 1579 1580 pinctrl_uart6_default: uart6_default { 1581 function = "UART6"; 1582 groups = "UART6"; 1583 }; 1584 1585 pinctrl_usbcki_default: usbcki_default { 1586 function = "USBCKI"; 1587 groups = "USBCKI"; 1588 }; 1589 1590 pinctrl_usb2ah_default: usb2ah_default { 1591 function = "USB2AH"; 1592 groups = "USB2AH"; 1593 }; 1594 1595 pinctrl_usb11bhid_default: usb11bhid_default { 1596 function = "USB11BHID"; 1597 groups = "USB11BHID"; 1598 }; 1599 1600 pinctrl_usb2bh_default: usb2bh_default { 1601 function = "USB2BH"; 1602 groups = "USB2BH"; 1603 }; 1604 1605 pinctrl_vgabiosrom_default: vgabiosrom_default { 1606 function = "VGABIOSROM"; 1607 groups = "VGABIOSROM"; 1608 }; 1609 1610 pinctrl_vgahs_default: vgahs_default { 1611 function = "VGAHS"; 1612 groups = "VGAHS"; 1613 }; 1614 1615 pinctrl_vgavs_default: vgavs_default { 1616 function = "VGAVS"; 1617 groups = "VGAVS"; 1618 }; 1619 1620 pinctrl_vpi24_default: vpi24_default { 1621 function = "VPI24"; 1622 groups = "VPI24"; 1623 }; 1624 1625 pinctrl_vpo_default: vpo_default { 1626 function = "VPO"; 1627 groups = "VPO"; 1628 }; 1629 1630 pinctrl_wdtrst1_default: wdtrst1_default { 1631 function = "WDTRST1"; 1632 groups = "WDTRST1"; 1633 }; 1634 1635 pinctrl_wdtrst2_default: wdtrst2_default { 1636 function = "WDTRST2"; 1637 groups = "WDTRST2"; 1638 }; 1639}; 1640