xref: /openbmc/u-boot/arch/arm/dts/ast2600-u-boot.dtsi (revision d6e349c7)

#include <dt-bindings/clock/ast2600-clock.h>
#include <dt-bindings/reset/ast2500-reset.h>

#include "ast2600.dtsi"

/ {
	scu: clock-controller@1e6e2000 {
		compatible = "aspeed,ast2600-scu";
		reg = <0x1e6e2000 0x1000>;
		u-boot,dm-pre-reloc;
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	rst: reset-controller {
		u-boot,dm-pre-reloc;
		compatible = "aspeed,ast2600-reset";
		aspeed,wdt = <&wdt1>;
		#reset-cells = <1>;
	};

#if 0
	sdrammc: sdrammc@1e6e0000 {
		u-boot,dm-pre-reloc;
		compatible = "aspeed,ast2500-sdrammc";
		reg = <0x1e6e0000 0x174
			0x1e6e0200 0x1d4 >;
		#reset-cells = <1>;
		clocks = <&scu PLL_MPLL>;
		resets = <&rst AST_RESET_SDRAM>;
	};
#endif
	ahb {
		u-boot,dm-pre-reloc;

		apb {
			u-boot,dm-pre-reloc;
		};

	};
};

&uart1 {
	clock-frequency = <1846154>;
};

&uart2 {
	clock-frequency = <1846154>;
};

&uart3 {
	clock-frequency = <1846154>;
};

&uart4 {
	clock-frequency = <1846154>;
};

&uart5 {
#if 0
	clock-frequency = <1846154>;
#endif
	clocks = <&scu ASPEED_CLK_UART5>;
};

&mac0 {
	clocks = <&scu PCLK_MAC1>, <&scu PLL_D2PLL>;
};

&mac1 {
	clocks = <&scu PCLK_MAC2>, <&scu PLL_D2PLL>;
};

&fmc {
	clocks = <&scu BCLK_HCLK>;
};

&spi1 {
	clocks = <&scu BCLK_HCLK>;
};

&spi2 {
	clocks = <&scu BCLK_HCLK>;
};