1d6e349c7Sryan_chen#include <dt-bindings/clock/ast2600-clock.h> 2b9553986Sryan_chen#include <dt-bindings/reset/ast2500-reset.h> 3b9553986Sryan_chen 4b9553986Sryan_chen#include "ast2600.dtsi" 5b9553986Sryan_chen 6b9553986Sryan_chen/ { 7b9553986Sryan_chen scu: clock-controller@1e6e2000 { 8b9553986Sryan_chen compatible = "aspeed,ast2600-scu"; 9b9553986Sryan_chen reg = <0x1e6e2000 0x1000>; 10b9553986Sryan_chen u-boot,dm-pre-reloc; 11b9553986Sryan_chen #clock-cells = <1>; 12b9553986Sryan_chen #reset-cells = <1>; 13b9553986Sryan_chen }; 14b9553986Sryan_chen 15b9553986Sryan_chen rst: reset-controller { 16b9553986Sryan_chen u-boot,dm-pre-reloc; 17b9553986Sryan_chen compatible = "aspeed,ast2600-reset"; 18b9553986Sryan_chen aspeed,wdt = <&wdt1>; 19b9553986Sryan_chen #reset-cells = <1>; 20b9553986Sryan_chen }; 21b9553986Sryan_chen 22b9553986Sryan_chen#if 0 23b9553986Sryan_chen sdrammc: sdrammc@1e6e0000 { 24b9553986Sryan_chen u-boot,dm-pre-reloc; 25b9553986Sryan_chen compatible = "aspeed,ast2500-sdrammc"; 26b9553986Sryan_chen reg = <0x1e6e0000 0x174 27b9553986Sryan_chen 0x1e6e0200 0x1d4 >; 28b9553986Sryan_chen #reset-cells = <1>; 29b9553986Sryan_chen clocks = <&scu PLL_MPLL>; 30b9553986Sryan_chen resets = <&rst AST_RESET_SDRAM>; 31b9553986Sryan_chen }; 32b9553986Sryan_chen#endif 33b9553986Sryan_chen ahb { 34b9553986Sryan_chen u-boot,dm-pre-reloc; 35b9553986Sryan_chen 36b9553986Sryan_chen apb { 37b9553986Sryan_chen u-boot,dm-pre-reloc; 38b9553986Sryan_chen }; 39b9553986Sryan_chen 40b9553986Sryan_chen }; 41b9553986Sryan_chen}; 42b9553986Sryan_chen 43b9553986Sryan_chen&uart1 { 44b9553986Sryan_chen clock-frequency = <1846154>; 45b9553986Sryan_chen}; 46b9553986Sryan_chen 47b9553986Sryan_chen&uart2 { 48b9553986Sryan_chen clock-frequency = <1846154>; 49b9553986Sryan_chen}; 50b9553986Sryan_chen 51b9553986Sryan_chen&uart3 { 52b9553986Sryan_chen clock-frequency = <1846154>; 53b9553986Sryan_chen}; 54b9553986Sryan_chen 55b9553986Sryan_chen&uart4 { 56b9553986Sryan_chen clock-frequency = <1846154>; 57b9553986Sryan_chen}; 58b9553986Sryan_chen 59b9553986Sryan_chen&uart5 { 60d6e349c7Sryan_chen#if 0 61b9553986Sryan_chen clock-frequency = <1846154>; 62d6e349c7Sryan_chen#endif 63*d1e64dd1Sryan_chen clocks = <&scu ASPEED_CLK_GATE_UART5CLK>; 64d6e349c7Sryan_chen}; 65d6e349c7Sryan_chen 66d6e349c7Sryan_chen&mac0 { 67d6e349c7Sryan_chen clocks = <&scu PCLK_MAC1>, <&scu PLL_D2PLL>; 68d6e349c7Sryan_chen}; 69d6e349c7Sryan_chen 70d6e349c7Sryan_chen&mac1 { 71d6e349c7Sryan_chen clocks = <&scu PCLK_MAC2>, <&scu PLL_D2PLL>; 72d6e349c7Sryan_chen}; 73d6e349c7Sryan_chen 74d6e349c7Sryan_chen&fmc { 75*d1e64dd1Sryan_chen clocks = <&scu ASPEED_CLK_AHB>; 76d6e349c7Sryan_chen}; 77d6e349c7Sryan_chen 78d6e349c7Sryan_chen&spi1 { 79*d1e64dd1Sryan_chen clocks = <&scu ASPEED_CLK_AHB>; 80d6e349c7Sryan_chen}; 81d6e349c7Sryan_chen 82d6e349c7Sryan_chen&spi2 { 83*d1e64dd1Sryan_chen clocks = <&scu ASPEED_CLK_AHB>; 84b9553986Sryan_chen}; 85