1/dts-v1/; 2 3#include "ast2600-u-boot.dtsi" 4 5/ { 6 memory { 7 device_type = "memory"; 8 reg = <0x80000000 0x40000000>; 9 }; 10 11 chosen { 12 stdout-path = &uart5; 13 }; 14 15 aliases { 16 mmc0 = &emmc_slot0; 17 mmc1 = &sdhci_slot0; 18 mmc2 = &sdhci_slot1; 19 spi0 = &fmc; 20 spi1 = &spi1; 21 spi2 = &spi2; 22 ethernet0 = &mac0; 23 ethernet1 = &mac1; 24 ethernet2 = &mac2; 25 ethernet3 = &mac3; 26 }; 27 28 cpus { 29 cpu@0 { 30 clock-frequency = <800000000>; 31 }; 32 cpu@1 { 33 clock-frequency = <800000000>; 34 }; 35 }; 36}; 37 38&uart5 { 39 u-boot,dm-pre-reloc; 40 status = "okay"; 41}; 42 43&sdrammc { 44 clock-frequency = <400000000>; 45}; 46 47&wdt1 { 48 u-boot,dm-pre-reloc; 49 status = "okay"; 50}; 51 52&wdt2 { 53 u-boot,dm-pre-reloc; 54 status = "okay"; 55}; 56 57&wdt3 { 58 u-boot,dm-pre-reloc; 59 status = "okay"; 60}; 61 62&mdio { 63 status = "okay"; 64 pinctrl-names = "default"; 65 pinctrl-0 = < &pinctrl_mdio1_default &pinctrl_mdio2_default 66 &pinctrl_mdio3_default &pinctrl_mdio4_default>; 67 #address-cells = <1>; 68 #size-cells = <0>; 69 ethphy1: ethernet-phy@1 { 70 reg = <0>; 71 }; 72 73 ethphy2: ethernet-phy@2 { 74 reg = <0>; 75 }; 76 77 ethphy3: ethernet-phy@3 { 78 reg = <0>; 79 }; 80 81 ethphy4: ethernet-phy@4 { 82 reg = <0>; 83 }; 84}; 85 86&mac0 { 87 status = "okay"; 88 phy-mode = "rgmii"; 89 phy-handle = <ðphy1>; 90 pinctrl-names = "default"; 91 pinctrl-0 = <&pinctrl_rgmii1_default>; 92}; 93 94&mac1 { 95 status = "okay"; 96 phy-mode = "rgmii"; 97 phy-handle = <ðphy2>; 98 pinctrl-names = "default"; 99 pinctrl-0 = <&pinctrl_rgmii2_default>; 100}; 101 102&mac2 { 103 status = "okay"; 104 phy-mode = "rgmii"; 105 phy-handle = <ðphy3>; 106 pinctrl-names = "default"; 107 pinctrl-0 = <&pinctrl_rgmii3_default>; 108}; 109 110&mac3 { 111 status = "okay"; 112 phy-mode = "rgmii"; 113 phy-handle = <ðphy4>; 114 pinctrl-names = "default"; 115 pinctrl-0 = <&pinctrl_rgmii4_default>; 116}; 117 118&fmc { 119 status = "okay"; 120 121 pinctrl-names = "default"; 122 pinctrl-0 = <&pinctrl_fmcquad_default>; 123 124 flash@0 { 125 compatible = "spi-flash", "sst,w25q256"; 126 status = "okay"; 127 spi-max-frequency = <50000000>; 128 spi-tx-bus-width = <4>; 129 spi-rx-bus-width = <4>; 130 }; 131 132 flash@1 { 133 compatible = "spi-flash", "sst,w25q256"; 134 status = "okay"; 135 spi-max-frequency = <50000000>; 136 spi-tx-bus-width = <4>; 137 spi-rx-bus-width = <4>; 138 }; 139 140 flash@2 { 141 compatible = "spi-flash", "sst,w25q256"; 142 status = "okay"; 143 spi-max-frequency = <50000000>; 144 spi-tx-bus-width = <4>; 145 spi-rx-bus-width = <4>; 146 }; 147}; 148 149&spi1 { 150 status = "okay"; 151 152 pinctrl-names = "default"; 153 pinctrl-0 = <&pinctrl_spi1_default &pinctrl_spi1abr_default 154 &pinctrl_spi1cs1_default &pinctrl_spi1wp_default 155 &pinctrl_spi1wp_default &pinctrl_spi1quad_default>; 156 157 flash@0 { 158 compatible = "spi-flash", "sst,w25q256"; 159 status = "okay"; 160 spi-max-frequency = <50000000>; 161 spi-tx-bus-width = <4>; 162 spi-rx-bus-width = <4>; 163 }; 164 165 flash@1 { 166 compatible = "spi-flash", "sst,w25q256"; 167 status = "okay"; 168 spi-max-frequency = <50000000>; 169 spi-tx-bus-width = <4>; 170 spi-rx-bus-width = <4>; 171 }; 172}; 173 174&spi2 { 175 status = "okay"; 176 177 pinctrl-names = "default"; 178 pinctrl-0 = <&pinctrl_spi2_default &pinctrl_spi2cs1_default 179 &pinctrl_spi2cs2_default &pinctrl_spi2quad_default>; 180 181 flash@0 { 182 compatible = "spi-flash", "sst,w25q256"; 183 status = "okay"; 184 spi-max-frequency = <50000000>; 185 spi-tx-bus-width = <4>; 186 spi-rx-bus-width = <4>; 187 }; 188 189 flash@1 { 190 compatible = "spi-flash", "sst,w25q256"; 191 status = "okay"; 192 spi-max-frequency = <50000000>; 193 spi-tx-bus-width = <4>; 194 spi-rx-bus-width = <4>; 195 }; 196 197 flash@2 { 198 compatible = "spi-flash", "sst,w25q256"; 199 status = "okay"; 200 spi-max-frequency = <50000000>; 201 spi-tx-bus-width = <4>; 202 spi-rx-bus-width = <4>; 203 }; 204}; 205 206&emmc { 207 timing-phase = <0x700ff>; 208}; 209 210&emmc_slot0 { 211 status = "okay"; 212 bus-width = <4>; 213 pinctrl-names = "default"; 214 pinctrl-0 = <&pinctrl_emmc_default>; 215 sdhci-drive-type = <1>; 216}; 217 218&sdhci { 219 timing-phase = <0xc6ffff>; 220}; 221 222&sdhci_slot0 { 223 status = "okay"; 224 bus-width = <4>; 225 pwr-gpios = <&gpio0 ASPEED_GPIO(V, 0) GPIO_ACTIVE_HIGH>; 226 pwr-sw-gpios = <&gpio0 ASPEED_GPIO(V, 1) GPIO_ACTIVE_HIGH>; 227 pinctrl-names = "default"; 228 pinctrl-0 = <&pinctrl_sd1_default>; 229 sdhci-drive-type = <1>; 230}; 231 232&sdhci_slot1 { 233 status = "okay"; 234 bus-width = <4>; 235 pwr-gpios = <&gpio0 ASPEED_GPIO(V, 2) GPIO_ACTIVE_HIGH>; 236 pwr-sw-gpios = <&gpio0 ASPEED_GPIO(V, 3) GPIO_ACTIVE_HIGH>; 237 pinctrl-names = "default"; 238 pinctrl-0 = <&pinctrl_sd2_default>; 239 sdhci-drive-type = <1>; 240}; 241 242&i2c4 { 243 status = "okay"; 244 245 pinctrl-names = "default"; 246 pinctrl-0 = <&pinctrl_i2c5_default>; 247}; 248 249&i2c5 { 250 status = "okay"; 251 252 pinctrl-names = "default"; 253 pinctrl-0 = <&pinctrl_i2c6_default>; 254}; 255 256&i2c6 { 257 status = "okay"; 258 259 pinctrl-names = "default"; 260 pinctrl-0 = <&pinctrl_i2c7_default>; 261}; 262 263&i2c7 { 264 status = "okay"; 265 266 pinctrl-names = "default"; 267 pinctrl-0 = <&pinctrl_i2c8_default>; 268}; 269 270&i2c8 { 271 status = "okay"; 272 273 pinctrl-names = "default"; 274 pinctrl-0 = <&pinctrl_i2c9_default>; 275}; 276 277&pcie_bridge1 { 278 status = "okay"; 279}; 280 281&h2x { 282 status = "okay"; 283}; 284 285#if 0 286&fsim0 { 287 status = "okay"; 288}; 289 290&fsim1 { 291 status = "okay"; 292}; 293#endif 294 295&ehci1 { 296 status = "okay"; 297}; 298