1/dts-v1/; 2 3#include "ast2600-u-boot.dtsi" 4 5/ { 6 memory { 7 device_type = "memory"; 8 reg = <0x80000000 0x40000000>; 9 }; 10 11 chosen { 12 stdout-path = &uart5; 13 }; 14 15 aliases { 16 mmc0 = &emmc_slot0; 17 mmc1 = &sdhci_slot0; 18 mmc2 = &sdhci_slot1; 19 spi0 = &fmc; 20 spi1 = &spi1; 21 spi2 = &spi2; 22 ethernet0 = &mac0; 23 ethernet1 = &mac1; 24 ethernet2 = &mac2; 25 ethernet3 = &mac3; 26 }; 27 28 cpus { 29 cpu@0 { 30 clock-frequency = <800000000>; 31 }; 32 cpu@1 { 33 clock-frequency = <800000000>; 34 }; 35 }; 36}; 37 38&uart5 { 39 u-boot,dm-pre-reloc; 40 status = "okay"; 41}; 42 43&sdrammc { 44 clock-frequency = <400000000>; 45}; 46 47&wdt1 { 48 u-boot,dm-pre-reloc; 49 status = "okay"; 50}; 51 52&wdt2 { 53 u-boot,dm-pre-reloc; 54 status = "okay"; 55}; 56 57&wdt3 { 58 u-boot,dm-pre-reloc; 59 status = "okay"; 60}; 61 62&mdio { 63 status = "okay"; 64 pinctrl-names = "default"; 65 pinctrl-0 = < &pinctrl_mdio1_default &pinctrl_mdio2_default 66 &pinctrl_mdio3_default &pinctrl_mdio4_default>; 67 #address-cells = <1>; 68 #size-cells = <0>; 69 ethphy1: ethernet-phy@1 { 70 reg = <0>; 71 }; 72 73 ethphy2: ethernet-phy@2 { 74 reg = <0>; 75 }; 76 77 ethphy3: ethernet-phy@3 { 78 reg = <0>; 79 }; 80 81 ethphy4: ethernet-phy@4 { 82 reg = <0>; 83 }; 84}; 85 86&mac0 { 87 status = "okay"; 88 phy-mode = "rgmii"; 89 phy-handle = <ðphy1>; 90 pinctrl-names = "default"; 91 pinctrl-0 = <&pinctrl_rgmii1_default>; 92}; 93 94&mac1 { 95 status = "okay"; 96 phy-mode = "rgmii"; 97 phy-handle = <ðphy2>; 98 pinctrl-names = "default"; 99 pinctrl-0 = <&pinctrl_rgmii2_default>; 100}; 101 102&mac2 { 103 status = "okay"; 104 phy-mode = "rgmii"; 105 phy-handle = <ðphy3>; 106 pinctrl-names = "default"; 107 pinctrl-0 = <&pinctrl_rgmii3_default>; 108}; 109 110&mac3 { 111 status = "okay"; 112 phy-mode = "rgmii"; 113 phy-handle = <ðphy4>; 114 pinctrl-names = "default"; 115 pinctrl-0 = <&pinctrl_rgmii4_default>; 116}; 117 118&fmc { 119 status = "okay"; 120 121 pinctrl-names = "default"; 122 pinctrl-0 = <&pinctrl_fmcquad_default>; 123 124 flash@0 { 125 status = "okay"; 126 spi-max-frequency = <50000000>; 127 spi-tx-bus-width = <4>; 128 spi-rx-bus-width = <4>; 129 }; 130 131 flash@1 { 132 status = "okay"; 133 spi-max-frequency = <50000000>; 134 spi-tx-bus-width = <4>; 135 spi-rx-bus-width = <4>; 136 }; 137 138 flash@2 { 139 status = "okay"; 140 spi-max-frequency = <50000000>; 141 spi-tx-bus-width = <4>; 142 spi-rx-bus-width = <4>; 143 }; 144}; 145 146&spi1 { 147 status = "okay"; 148 149 pinctrl-names = "default"; 150 pinctrl-0 = <&pinctrl_spi1_default &pinctrl_spi1abr_default 151 &pinctrl_spi1cs1_default &pinctrl_spi1wp_default 152 &pinctrl_spi1wp_default &pinctrl_spi1quad_default>; 153 154 flash@0 { 155 status = "okay"; 156 spi-max-frequency = <50000000>; 157 spi-tx-bus-width = <4>; 158 spi-rx-bus-width = <4>; 159 }; 160 161 flash@1 { 162 status = "okay"; 163 spi-max-frequency = <50000000>; 164 spi-tx-bus-width = <4>; 165 spi-rx-bus-width = <4>; 166 }; 167}; 168 169&spi2 { 170 status = "okay"; 171 172 pinctrl-names = "default"; 173 pinctrl-0 = <&pinctrl_spi2_default &pinctrl_spi2cs1_default 174 &pinctrl_spi2cs2_default &pinctrl_spi2quad_default>; 175 176 flash@0 { 177 status = "okay"; 178 spi-max-frequency = <50000000>; 179 spi-tx-bus-width = <4>; 180 spi-rx-bus-width = <4>; 181 }; 182 183 flash@1 { 184 status = "okay"; 185 spi-max-frequency = <50000000>; 186 spi-tx-bus-width = <4>; 187 spi-rx-bus-width = <4>; 188 }; 189 190 flash@2 { 191 status = "okay"; 192 spi-max-frequency = <50000000>; 193 spi-tx-bus-width = <4>; 194 spi-rx-bus-width = <4>; 195 }; 196}; 197 198&emmc { 199 timing-phase = <0x700ff>; 200}; 201 202&emmc_slot0 { 203 status = "okay"; 204 bus-width = <4>; 205 pinctrl-names = "default"; 206 pinctrl-0 = <&pinctrl_emmc_default>; 207 sdhci-drive-type = <1>; 208}; 209 210&sdhci { 211 timing-phase = <0xc6ffff>; 212}; 213 214&sdhci_slot0 { 215 status = "okay"; 216 bus-width = <4>; 217 pwr-gpios = <&gpio0 ASPEED_GPIO(V, 0) GPIO_ACTIVE_HIGH>; 218 pwr-sw-gpios = <&gpio0 ASPEED_GPIO(V, 1) GPIO_ACTIVE_HIGH>; 219 pinctrl-names = "default"; 220 pinctrl-0 = <&pinctrl_sd1_default>; 221 sdhci-drive-type = <1>; 222}; 223 224&sdhci_slot1 { 225 status = "okay"; 226 bus-width = <4>; 227 pwr-gpios = <&gpio0 ASPEED_GPIO(V, 2) GPIO_ACTIVE_HIGH>; 228 pwr-sw-gpios = <&gpio0 ASPEED_GPIO(V, 3) GPIO_ACTIVE_HIGH>; 229 pinctrl-names = "default"; 230 pinctrl-0 = <&pinctrl_sd2_default>; 231 sdhci-drive-type = <1>; 232}; 233 234&i2c4 { 235 status = "okay"; 236 237 pinctrl-names = "default"; 238 pinctrl-0 = <&pinctrl_i2c5_default>; 239}; 240 241&i2c5 { 242 status = "okay"; 243 244 pinctrl-names = "default"; 245 pinctrl-0 = <&pinctrl_i2c6_default>; 246}; 247 248&i2c6 { 249 status = "okay"; 250 251 pinctrl-names = "default"; 252 pinctrl-0 = <&pinctrl_i2c7_default>; 253}; 254 255&i2c7 { 256 status = "okay"; 257 258 pinctrl-names = "default"; 259 pinctrl-0 = <&pinctrl_i2c8_default>; 260}; 261 262&i2c8 { 263 status = "okay"; 264 265 pinctrl-names = "default"; 266 pinctrl-0 = <&pinctrl_i2c9_default>; 267}; 268 269 270#if 0 271&fsim0 { 272 status = "okay"; 273}; 274 275&fsim1 { 276 status = "okay"; 277}; 278#endif 279 280&ehci1 { 281 status = "okay"; 282}; 283