xref: /openbmc/u-boot/arch/arm/dts/ast2600-slt.dts (revision c7c4c2d9)

/dts-v1/;

#include "ast2600-u-boot.dtsi"

/ {
	memory {
		device_type = "memory";
		reg = <0x80000000 0x40000000>;
	};

	chosen {
		stdout-path = &uart5;
	};

	aliases {
		mmc0 = &emmc_slot0;
		mmc1 = &sdhci_slot0;
		mmc2 = &sdhci_slot1;
		spi0 = &fmc;
		spi1 = &spi1;
		spi2 = &spi2;
		ethernet0 = &mac0;
		ethernet1 = &mac1;
		ethernet2 = &mac2;
		ethernet3 = &mac3;
	};

	cpus {
		cpu@0 {
			clock-frequency = <800000000>;
		};
		cpu@1 {
			clock-frequency = <800000000>;
		};
	};
};

&uart5 {
	u-boot,dm-pre-reloc;
	status = "okay";
};

&sdrammc {
	clock-frequency = <400000000>;
};

&wdt1 {
	u-boot,dm-pre-reloc;
	status = "okay";
};

&wdt2 {
	u-boot,dm-pre-reloc;
	status = "okay";
};

&wdt3 {
	u-boot,dm-pre-reloc;
	status = "okay";
};

&mdio {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <	&pinctrl_mdio1_default &pinctrl_mdio2_default
			&pinctrl_mdio3_default &pinctrl_mdio4_default>;
	#address-cells = <1>;
	#size-cells = <0>;
	ethphy1: ethernet-phy@1 {
		reg = <0>;
	};

	ethphy2: ethernet-phy@2 {
		reg = <0>;
	};

	ethphy3: ethernet-phy@3 {
		reg = <0>;
	};

	ethphy4: ethernet-phy@4 {
		reg = <0>;
	};
};

&mac0 {
	status = "okay";
	phy-mode = "rgmii";
	phy-handle = <&ethphy1>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_rgmii1_default>;
};

&mac1 {
	status = "okay";
	phy-mode = "rgmii";
	phy-handle = <&ethphy2>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_rgmii2_default>;
};

&mac2 {
	status = "okay";
	phy-mode = "rgmii";
	phy-handle = <&ethphy3>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_rgmii3_default>;
};

&mac3 {
	status = "okay";
	phy-mode = "rgmii";
	phy-handle = <&ethphy4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_rgmii4_default>;
};

&fmc {
	status = "okay";

	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fmcquad_default>;

	flash@0 {
		compatible = "spi-flash", "sst,w25q256";
		status = "okay";
		spi-max-frequency = <50000000>;
		spi-tx-bus-width = <4>;
		spi-rx-bus-width = <4>;
	};

	flash@1 {
		compatible = "spi-flash", "sst,w25q256";
		status = "okay";
		spi-max-frequency = <50000000>;
		spi-tx-bus-width = <4>;
		spi-rx-bus-width = <4>;
	};

	flash@2 {
		compatible = "spi-flash", "sst,w25q256";
		status = "okay";
		spi-max-frequency = <50000000>;
		spi-tx-bus-width = <4>;
		spi-rx-bus-width = <4>;
	};
};

&spi1 {
	status = "okay";

	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_spi1_default &pinctrl_spi1abr_default
			&pinctrl_spi1cs1_default &pinctrl_spi1wp_default
			&pinctrl_spi1wp_default &pinctrl_spi1quad_default>;

	flash@0 {
		compatible = "spi-flash", "sst,w25q256";
		status = "okay";
		spi-max-frequency = <50000000>;
		spi-tx-bus-width = <4>;
		spi-rx-bus-width = <4>;
	};

	flash@1 {
		compatible = "spi-flash", "sst,w25q256";
		status = "okay";
		spi-max-frequency = <50000000>;
		spi-tx-bus-width = <4>;
		spi-rx-bus-width = <4>;
	};
};

&spi2 {
	status = "okay";

	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_spi2_default &pinctrl_spi2cs1_default
			&pinctrl_spi2cs2_default &pinctrl_spi2quad_default>;

	flash@0 {
		compatible = "spi-flash", "sst,w25q256";
		status = "okay";
		spi-max-frequency = <50000000>;
		spi-tx-bus-width = <4>;
		spi-rx-bus-width = <4>;
	};

	flash@1 {
		compatible = "spi-flash", "sst,w25q256";
		status = "okay";
		spi-max-frequency = <50000000>;
		spi-tx-bus-width = <4>;
		spi-rx-bus-width = <4>;
	};

	flash@2 {
		compatible = "spi-flash", "sst,w25q256";
		status = "okay";
		spi-max-frequency = <50000000>;
		spi-tx-bus-width = <4>;
		spi-rx-bus-width = <4>;
	};
};

&emmc {
	timing-phase = <0x700ff>;
};

&emmc_slot0 {
	status = "okay";
	bus-width = <4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_emmc_default>;
	sdhci-drive-type = <1>;
};

&sdhci {
	timing-phase = <0xc6ffff>;
};

&sdhci_slot0 {
	status = "okay";
	bus-width = <4>;
	pwr-gpios = <&gpio0 ASPEED_GPIO(V, 0) GPIO_ACTIVE_HIGH>;
	pwr-sw-gpios = <&gpio0 ASPEED_GPIO(V, 1) GPIO_ACTIVE_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sd1_default>;
	sdhci-drive-type = <1>;
};

&sdhci_slot1 {
	status = "okay";
	bus-width = <4>;
	pwr-gpios = <&gpio0 ASPEED_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
	pwr-sw-gpios = <&gpio0 ASPEED_GPIO(V, 3) GPIO_ACTIVE_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sd2_default>;
	sdhci-drive-type = <1>;
};

&i2c4 {
	status = "okay";

	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c5_default>;
};

&i2c5 {
	status = "okay";

	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c6_default>;
};

&i2c6 {
	status = "okay";

	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c7_default>;
};

&i2c7 {
	status = "okay";

	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c8_default>;
};

&i2c8 {
	status = "okay";

	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c9_default>;
};

&pcie_bridge1 {
	status = "okay";
};

&h2x {
	status = "okay";
};

#if 0
&fsim0 {
	status = "okay";
};

&fsim1 {
	status = "okay";
};
#endif

&ehci1 {
	status = "okay";
};