1// SPDX-License-Identifier: GPL-2.0-or-later 2// Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 3/dts-v1/; 4 5#include "ast2600-u-boot.dtsi" 6 7/ { 8 model = "Qualcomm DC-SCM V1 BMC"; 9 compatible = "qcom,dc-scm-v1-bmc", "aspeed,ast2600"; 10 11 memory { 12 device_type = "memory"; 13 reg = <0x80000000 0x40000000>; 14 }; 15 16 chosen { 17 stdout-path = &uart5; 18 }; 19 20 aliases { 21 spi0 = &fmc; 22 spi1 = &spi1; 23 spi2 = &spi2; 24 }; 25 26 cpus { 27 cpu@0 { 28 clock-frequency = <800000000>; 29 }; 30 cpu@1 { 31 clock-frequency = <800000000>; 32 }; 33 }; 34}; 35 36&uart5 { 37 u-boot,dm-pre-reloc; 38 status = "okay"; 39}; 40 41&sdrammc { 42 clock-frequency = <400000000>; 43}; 44 45&wdt1 { 46 status = "okay"; 47}; 48 49&wdt2 { 50 status = "okay"; 51}; 52 53&wdt3 { 54 status = "okay"; 55}; 56 57&mdio { 58 status = "okay"; 59 pinctrl-names = "default"; 60 pinctrl-0 = <&pinctrl_mdio4_default>; 61 #address-cells = <1>; 62 #size-cells = <0>; 63 64 ethphy3: ethernet-phy@1 { 65 reg = <1>; 66 }; 67}; 68 69&mac2 { 70 status = "okay"; 71 reg = <0x1e670000 0x180>, <0x1e650018 0x4>; 72 phy-mode = "rgmii"; 73 phy-handle = <ðphy3>; 74 pinctrl-names = "default"; 75 pinctrl-0 = <&pinctrl_rgmii3_default>; 76}; 77 78&fmc { 79 status = "okay"; 80 81 pinctrl-names = "default"; 82 pinctrl-0 = <&pinctrl_fmcquad_default>; 83 84 flash@0 { 85 status = "okay"; 86 spi-max-frequency = <133000000>; 87 spi-tx-bus-width = <4>; 88 spi-rx-bus-width = <4>; 89 }; 90 91 flash@1 { 92 status = "okay"; 93 spi-max-frequency = <133000000>; 94 spi-tx-bus-width = <4>; 95 spi-rx-bus-width = <4>; 96 }; 97}; 98 99&spi1 { 100 status = "okay"; 101 102 pinctrl-names = "default"; 103 pinctrl-0 = <&pinctrl_spi1_default &pinctrl_spi1abr_default 104 &pinctrl_spi1cs1_default &pinctrl_spi1wp_default 105 &pinctrl_spi1wp_default &pinctrl_spi1quad_default>; 106 107 flash@0 { 108 status = "okay"; 109 spi-max-frequency = <133000000>; 110 spi-tx-bus-width = <4>; 111 spi-rx-bus-width = <4>; 112 }; 113}; 114 115&i2c4 { 116 status = "okay"; 117}; 118 119&i2c5 { 120 status = "okay"; 121}; 122 123&i2c6 { 124 status = "okay"; 125}; 126 127&i2c7 { 128 status = "okay"; 129}; 130 131&i2c8 { 132 status = "okay"; 133}; 134 135&i2c9 { 136 status = "okay"; 137}; 138 139&i2c10 { 140 status = "okay"; 141}; 142 143&i2c12 { 144 status = "okay"; 145}; 146 147&i2c13 { 148 status = "okay"; 149}; 150 151&i2c14 { 152 status = "okay"; 153}; 154 155&i2c15 { 156 status = "okay"; 157}; 158 159&scu { 160 mac0-clk-delay = <0x1d 0x1c 161 0x10 0x17 162 0x10 0x17>; 163 mac1-clk-delay = <0x1d 0x10 164 0x10 0x10 165 0x10 0x10>; 166 mac2-clk-delay = <0x0a 0x04 167 0x08 0x04 168 0x08 0x04>; 169 mac3-clk-delay = <0x0a 0x04 170 0x08 0x04 171 0x08 0x04>; 172}; 173 174&hace { 175 u-boot,dm-pre-reloc; 176 status = "okay"; 177}; 178