1// SPDX-License-Identifier: GPL-2.0-or-later 2/dts-v1/; 3 4#include "ast2600-u-boot.dtsi" 5 6/ { 7 model = "AST2600 EVB"; 8 compatible = "aspeed,ast2600-evb", "aspeed,ast2600"; 9 10 memory { 11 device_type = "memory"; 12 reg = <0x80000000 0x40000000>; 13 }; 14 15 chosen { 16 stdout-path = &uart5; 17 }; 18 19 aliases { 20 mmc0 = &emmc_slot0; 21 mmc1 = &sdhci_slot0; 22 mmc2 = &sdhci_slot1; 23 spi0 = &fmc; 24 spi1 = &spi1; 25 spi2 = &spi2; 26 ethernet0 = &mac0; 27 ethernet1 = &mac1; 28 ethernet2 = &mac2; 29 ethernet3 = &mac3; 30 }; 31 32 cpus { 33 cpu@0 { 34 clock-frequency = <800000000>; 35 }; 36 cpu@1 { 37 clock-frequency = <800000000>; 38 }; 39 }; 40}; 41 42&uart5 { 43 u-boot,dm-pre-reloc; 44 status = "okay"; 45}; 46 47&sdrammc { 48 clock-frequency = <400000000>; 49}; 50 51&wdt1 { 52 status = "okay"; 53}; 54 55&wdt2 { 56 status = "okay"; 57}; 58 59&wdt3 { 60 status = "okay"; 61}; 62 63&mdio { 64 status = "okay"; 65 pinctrl-names = "default"; 66 pinctrl-0 = < &pinctrl_mdio1_default &pinctrl_mdio2_default 67 &pinctrl_mdio3_default &pinctrl_mdio4_default>; 68 #address-cells = <1>; 69 #size-cells = <0>; 70 ethphy0: ethernet-phy@0 { 71 reg = <0>; 72 }; 73 74 ethphy1: ethernet-phy@1 { 75 reg = <0>; 76 }; 77 78 ethphy2: ethernet-phy@2 { 79 reg = <0>; 80 }; 81 82 ethphy3: ethernet-phy@3 { 83 reg = <0>; 84 }; 85}; 86 87&mac0 { 88 status = "okay"; 89 phy-mode = "rgmii-rxid"; 90 phy-handle = <ðphy0>; 91 pinctrl-names = "default"; 92 pinctrl-0 = <&pinctrl_rgmii1_default>; 93}; 94 95&mac1 { 96 status = "okay"; 97 phy-mode = "rgmii-rxid"; 98 phy-handle = <ðphy1>; 99 pinctrl-names = "default"; 100 pinctrl-0 = <&pinctrl_rgmii2_default>; 101}; 102 103&mac2 { 104 status = "okay"; 105 phy-mode = "rgmii"; 106 phy-handle = <ðphy2>; 107 pinctrl-names = "default"; 108 pinctrl-0 = <&pinctrl_rgmii3_default>; 109}; 110 111&mac3 { 112 status = "okay"; 113 phy-mode = "rgmii"; 114 phy-handle = <ðphy3>; 115 pinctrl-names = "default"; 116 pinctrl-0 = <&pinctrl_rgmii4_default>; 117}; 118 119&fmc { 120 status = "okay"; 121 122 pinctrl-names = "default"; 123 pinctrl-0 = <&pinctrl_fmcquad_default>; 124 timing-calibration-disabled; 125 126 flash@0 { 127 compatible = "spi-flash", "sst,w25q256"; 128 status = "okay"; 129 spi-max-frequency = <25000000>; 130 spi-tx-bus-width = <1>; 131 spi-rx-bus-width = <1>; 132 }; 133 134 flash@1 { 135 compatible = "spi-flash", "sst,w25q256"; 136 status = "okay"; 137 spi-max-frequency = <25000000>; 138 spi-tx-bus-width = <1>; 139 spi-rx-bus-width = <1>; 140 }; 141 142 flash@2 { 143 compatible = "spi-flash", "sst,w25q256"; 144 status = "okay"; 145 spi-max-frequency = <25000000>; 146 spi-tx-bus-width = <1>; 147 spi-rx-bus-width = <1>; 148 }; 149}; 150 151&spi1 { 152 status = "okay"; 153 154 pinctrl-names = "default"; 155 pinctrl-0 = <&pinctrl_spi1_default &pinctrl_spi1abr_default 156 &pinctrl_spi1cs1_default &pinctrl_spi1wp_default 157 &pinctrl_spi1wp_default &pinctrl_spi1quad_default>; 158 timing-calibration-disabled; 159 160 flash@0 { 161 compatible = "spi-flash", "sst,w25q256"; 162 status = "okay"; 163 spi-max-frequency = <25000000>; 164 spi-tx-bus-width = <1>; 165 spi-rx-bus-width = <1>; 166 }; 167 168 flash@1 { 169 compatible = "spi-flash", "sst,w25q256"; 170 status = "okay"; 171 spi-max-frequency = <25000000>; 172 spi-tx-bus-width = <1>; 173 spi-rx-bus-width = <1>; 174 }; 175}; 176 177&spi2 { 178 status = "okay"; 179 180 pinctrl-names = "default"; 181 pinctrl-0 = <&pinctrl_spi2_default &pinctrl_spi2cs1_default 182 &pinctrl_spi2cs2_default &pinctrl_spi2quad_default>; 183 timing-calibration-disabled; 184 185 flash@0 { 186 compatible = "spi-flash", "sst,w25q256"; 187 status = "okay"; 188 spi-max-frequency = <25000000>; 189 spi-tx-bus-width = <1>; 190 spi-rx-bus-width = <1>; 191 }; 192 193 flash@1 { 194 compatible = "spi-flash", "sst,w25q256"; 195 status = "okay"; 196 spi-max-frequency = <25000000>; 197 spi-tx-bus-width = <1>; 198 spi-rx-bus-width = <1>; 199 }; 200 201 flash@2 { 202 compatible = "spi-flash", "sst,w25q256"; 203 status = "okay"; 204 spi-max-frequency = <25000000>; 205 spi-tx-bus-width = <1>; 206 spi-rx-bus-width = <1>; 207 }; 208}; 209 210&emmc { 211 u-boot,dm-pre-reloc; 212 timing-phase = <0x000f0097>; 213}; 214 215&emmc_slot0 { 216 u-boot,dm-pre-reloc; 217 status = "okay"; 218 bus-width = <4>; 219 pinctrl-names = "default"; 220 pinctrl-0 = <&pinctrl_emmc_default>; 221 sdhci-drive-type = <1>; 222}; 223 224&sdhci { 225 timing-phase = <0x00c6375f>; 226}; 227 228&sdhci_slot0 { 229 status = "okay"; 230 bus-width = <4>; 231 pwr-gpios = <&gpio0 ASPEED_GPIO(V, 0) GPIO_ACTIVE_HIGH>; 232 pwr-sw-gpios = <&gpio0 ASPEED_GPIO(V, 1) GPIO_ACTIVE_HIGH>; 233 pinctrl-names = "default"; 234 pinctrl-0 = <&pinctrl_sd1_default>; 235 sdhci-drive-type = <1>; 236}; 237 238&sdhci_slot1 { 239 status = "okay"; 240 bus-width = <4>; 241 pwr-gpios = <&gpio0 ASPEED_GPIO(V, 2) GPIO_ACTIVE_HIGH>; 242 pwr-sw-gpios = <&gpio0 ASPEED_GPIO(V, 3) GPIO_ACTIVE_HIGH>; 243 pinctrl-names = "default"; 244 pinctrl-0 = <&pinctrl_sd2_default>; 245 sdhci-drive-type = <1>; 246}; 247 248&i2c4 { 249 status = "okay"; 250 251 pinctrl-names = "default"; 252 pinctrl-0 = <&pinctrl_i2c5_default>; 253}; 254 255&i2c5 { 256 status = "okay"; 257 258 pinctrl-names = "default"; 259 pinctrl-0 = <&pinctrl_i2c6_default>; 260}; 261 262&i2c6 { 263 status = "okay"; 264 265 pinctrl-names = "default"; 266 pinctrl-0 = <&pinctrl_i2c7_default>; 267}; 268 269&i2c7 { 270 status = "okay"; 271 272 pinctrl-names = "default"; 273 pinctrl-0 = <&pinctrl_i2c8_default>; 274}; 275 276&i2c8 { 277 status = "okay"; 278 279 pinctrl-names = "default"; 280 pinctrl-0 = <&pinctrl_i2c9_default>; 281}; 282 283&pcie_bridge1 { 284 status = "okay"; 285}; 286 287&h2x { 288 status = "okay"; 289}; 290 291#if 0 292&fsim0 { 293 status = "okay"; 294}; 295 296&fsim1 { 297 status = "okay"; 298}; 299#endif 300 301#if 0 302&vhub { 303 status = "okay"; 304}; 305#endif 306 307&ehci1 { 308 status = "okay"; 309}; 310 311&display_port { 312 status = "okay"; 313}; 314 315&scu { 316 mac0-clk-delay = <0x10 0x0a 317 0x10 0x10 318 0x10 0x10>; 319 mac1-clk-delay = <0x10 0x0a 320 0x10 0x10 321 0x10 0x10>; 322 mac2-clk-delay = <0x08 0x04 323 0x08 0x04 324 0x08 0x04>; 325 mac3-clk-delay = <0x08 0x04 326 0x08 0x04 327 0x08 0x04>; 328}; 329 330&hace { 331 u-boot,dm-pre-reloc; 332 status = "okay"; 333}; 334 335&acry { 336 u-boot,dm-pre-reloc; 337 status = "okay"; 338}; 339