1// SPDX-License-Identifier: GPL-2.0-or-later 2/dts-v1/; 3 4#include "ast2600-u-boot.dtsi" 5 6/ { 7 model = "AST2600 EVB"; 8 compatible = "aspeed,ast2600-evb", "aspeed,ast2600"; 9 10 memory { 11 device_type = "memory"; 12 reg = <0x80000000 0x40000000>; 13 }; 14 15 chosen { 16 stdout-path = &uart5; 17 }; 18 19 aliases { 20 mmc0 = &emmc_slot0; 21 mmc1 = &sdhci_slot0; 22 mmc2 = &sdhci_slot1; 23 spi0 = &fmc; 24 spi1 = &spi1; 25 spi2 = &spi2; 26 ethernet0 = &mac0; 27 ethernet1 = &mac1; 28 ethernet2 = &mac2; 29 ethernet3 = &mac3; 30 }; 31 32 cpus { 33 cpu@0 { 34 clock-frequency = <800000000>; 35 }; 36 cpu@1 { 37 clock-frequency = <800000000>; 38 }; 39 }; 40}; 41 42&uart5 { 43 u-boot,dm-pre-reloc; 44 status = "okay"; 45}; 46 47&sdrammc { 48 clock-frequency = <400000000>; 49}; 50 51&wdt1 { 52 status = "okay"; 53}; 54 55&wdt2 { 56 status = "okay"; 57}; 58 59&wdt3 { 60 status = "okay"; 61}; 62 63&mdio { 64 status = "okay"; 65 pinctrl-names = "default"; 66 pinctrl-0 = < &pinctrl_mdio1_default &pinctrl_mdio2_default 67 &pinctrl_mdio3_default &pinctrl_mdio4_default>; 68 #address-cells = <1>; 69 #size-cells = <0>; 70 ethphy0: ethernet-phy@0 { 71 reg = <0>; 72 }; 73 74 ethphy1: ethernet-phy@1 { 75 reg = <0>; 76 }; 77 78 ethphy2: ethernet-phy@2 { 79 reg = <0>; 80 }; 81 82 ethphy3: ethernet-phy@3 { 83 reg = <0>; 84 }; 85}; 86 87&mac0 { 88 status = "okay"; 89 phy-mode = "rgmii-rxid"; 90 phy-handle = <ðphy0>; 91 pinctrl-names = "default"; 92 pinctrl-0 = <&pinctrl_rgmii1_default>; 93}; 94 95&mac1 { 96 status = "okay"; 97 phy-mode = "rgmii-rxid"; 98 phy-handle = <ðphy1>; 99 pinctrl-names = "default"; 100 pinctrl-0 = <&pinctrl_rgmii2_default>; 101}; 102 103&mac2 { 104 status = "okay"; 105 phy-mode = "rgmii"; 106 phy-handle = <ðphy2>; 107 pinctrl-names = "default"; 108 pinctrl-0 = <&pinctrl_rgmii3_default>; 109}; 110 111&mac3 { 112 status = "okay"; 113 phy-mode = "rgmii"; 114 phy-handle = <ðphy3>; 115 pinctrl-names = "default"; 116 pinctrl-0 = <&pinctrl_rgmii4_default>; 117}; 118 119&fmc { 120 status = "okay"; 121 122 pinctrl-names = "default"; 123 pinctrl-0 = <&pinctrl_fmcquad_default>; 124 timing-calibration-disabled; 125 126 flash@0 { 127 status = "okay"; 128 spi-max-frequency = <12500000>; 129 spi-tx-bus-width = <1>; 130 spi-rx-bus-width = <1>; 131 }; 132 133 flash@1 { 134 status = "okay"; 135 spi-max-frequency = <12500000>; 136 spi-tx-bus-width = <1>; 137 spi-rx-bus-width = <1>; 138 }; 139 140 flash@2 { 141 status = "disabled"; 142 spi-max-frequency = <12500000>; 143 spi-tx-bus-width = <1>; 144 spi-rx-bus-width = <1>; 145 }; 146}; 147 148&spi1 { 149 status = "okay"; 150 151 pinctrl-names = "default"; 152 pinctrl-0 = <&pinctrl_spi1_default &pinctrl_spi1abr_default 153 &pinctrl_spi1cs1_default &pinctrl_spi1wp_default 154 &pinctrl_spi1wp_default &pinctrl_spi1quad_default>; 155 timing-calibration-disabled; 156 157 flash@0 { 158 status = "okay"; 159 spi-max-frequency = <12500000>; 160 spi-tx-bus-width = <1>; 161 spi-rx-bus-width = <1>; 162 }; 163 164 flash@1 { 165 status = "okay"; 166 spi-max-frequency = <12500000>; 167 spi-tx-bus-width = <1>; 168 spi-rx-bus-width = <1>; 169 }; 170}; 171 172&spi2 { 173 status = "okay"; 174 175 pinctrl-names = "default"; 176 pinctrl-0 = <&pinctrl_spi2_default &pinctrl_spi2cs1_default 177 &pinctrl_spi2cs2_default &pinctrl_spi2quad_default>; 178 timing-calibration-disabled; 179 180 flash@0 { 181 status = "okay"; 182 spi-max-frequency = <12500000>; 183 spi-tx-bus-width = <1>; 184 spi-rx-bus-width = <1>; 185 }; 186 187 flash@1 { 188 status = "disabled"; 189 spi-max-frequency = <12500000>; 190 spi-tx-bus-width = <1>; 191 spi-rx-bus-width = <1>; 192 }; 193 194 flash@2 { 195 status = "disabled"; 196 spi-max-frequency = <12500000>; 197 spi-tx-bus-width = <1>; 198 spi-rx-bus-width = <1>; 199 }; 200}; 201 202&emmc { 203 u-boot,dm-pre-reloc; 204 timing-phase = <0x000f0097>; 205}; 206 207&emmc_slot0 { 208 u-boot,dm-pre-reloc; 209 status = "okay"; 210 bus-width = <4>; 211 pinctrl-names = "default"; 212 pinctrl-0 = <&pinctrl_emmc_default>; 213 sdhci-drive-type = <1>; 214}; 215 216&sdhci { 217 timing-phase = <0x00c6375f>; 218}; 219 220&sdhci_slot0 { 221 status = "okay"; 222 bus-width = <4>; 223 pwr-gpios = <&gpio0 ASPEED_GPIO(V, 0) GPIO_ACTIVE_HIGH>; 224 pwr-sw-gpios = <&gpio0 ASPEED_GPIO(V, 1) GPIO_ACTIVE_HIGH>; 225 pinctrl-names = "default"; 226 pinctrl-0 = <&pinctrl_sd1_default>; 227 sdhci-drive-type = <1>; 228}; 229 230&sdhci_slot1 { 231 status = "okay"; 232 bus-width = <4>; 233 pwr-gpios = <&gpio0 ASPEED_GPIO(V, 2) GPIO_ACTIVE_HIGH>; 234 pwr-sw-gpios = <&gpio0 ASPEED_GPIO(V, 3) GPIO_ACTIVE_HIGH>; 235 pinctrl-names = "default"; 236 pinctrl-0 = <&pinctrl_sd2_default>; 237 sdhci-drive-type = <1>; 238}; 239 240&i2c4 { 241 status = "okay"; 242 243 pinctrl-names = "default"; 244 pinctrl-0 = <&pinctrl_i2c5_default>; 245}; 246 247&i2c5 { 248 status = "okay"; 249 250 pinctrl-names = "default"; 251 pinctrl-0 = <&pinctrl_i2c6_default>; 252}; 253 254&i2c6 { 255 status = "okay"; 256 257 pinctrl-names = "default"; 258 pinctrl-0 = <&pinctrl_i2c7_default>; 259}; 260 261&i2c7 { 262 status = "okay"; 263 264 pinctrl-names = "default"; 265 pinctrl-0 = <&pinctrl_i2c8_default>; 266}; 267 268&i2c8 { 269 status = "okay"; 270 271 pinctrl-names = "default"; 272 pinctrl-0 = <&pinctrl_i2c9_default>; 273}; 274 275 276#if 0 277&fsim0 { 278 status = "okay"; 279}; 280 281&fsim1 { 282 status = "okay"; 283}; 284#endif 285 286#if 0 287&vhub { 288 status = "okay"; 289}; 290#endif 291 292&ehci1 { 293 status = "okay"; 294}; 295 296&display_port { 297 status = "okay"; 298}; 299 300&scu { 301 mac0-clk-delay = <0x10 0x0a 302 0x10 0x10 303 0x10 0x10>; 304 mac1-clk-delay = <0x10 0x0a 305 0x10 0x10 306 0x10 0x10>; 307 mac2-clk-delay = <0x08 0x04 308 0x08 0x04 309 0x08 0x04>; 310 mac3-clk-delay = <0x08 0x04 311 0x08 0x04 312 0x08 0x04>; 313}; 314 315&hace { 316 u-boot,dm-pre-reloc; 317 status = "okay"; 318}; 319 320&acry { 321 u-boot,dm-pre-reloc; 322 status = "okay"; 323}; 324