1/dts-v1/; 2 3#include "ast2600-u-boot.dtsi" 4 5/ { 6 model = "AST2600 EVB w/ NCSI"; 7 compatible = "aspeed,ast2600-evb", "aspeed,ast2600"; 8 9 memory { 10 device_type = "memory"; 11 reg = <0x80000000 0x40000000>; 12 }; 13 14 chosen { 15 stdout-path = &uart5; 16 }; 17 18 aliases { 19 mmc0 = &emmc_slot0; 20 mmc1 = &sdhci_slot0; 21 mmc2 = &sdhci_slot1; 22 spi0 = &fmc; 23 spi1 = &spi1; 24 spi2 = &spi2; 25 ethernet0 = &mac0; 26 ethernet1 = &mac1; 27 ethernet2 = &mac2; 28 ethernet3 = &mac3; 29 }; 30 31 cpus { 32 cpu@0 { 33 clock-frequency = <800000000>; 34 }; 35 cpu@1 { 36 clock-frequency = <800000000>; 37 }; 38 }; 39}; 40 41&uart5 { 42 u-boot,dm-pre-reloc; 43 status = "okay"; 44}; 45 46&sdrammc { 47 clock-frequency = <400000000>; 48}; 49 50&wdt1 { 51 status = "okay"; 52}; 53 54&wdt2 { 55 status = "okay"; 56}; 57 58&wdt3 { 59 status = "okay"; 60}; 61 62#if 0 63&mdio { 64 status = "okay"; 65 pinctrl-names = "default"; 66 pinctrl-0 = < &pinctrl_mdio1_default &pinctrl_mdio2_default 67 &pinctrl_mdio3_default &pinctrl_mdio4_default>; 68 #address-cells = <1>; 69 #size-cells = <0>; 70 ethphy0: ethernet-phy@0 { 71 reg = <0>; 72 }; 73 74 ethphy1: ethernet-phy@1 { 75 reg = <0>; 76 }; 77 78 ethphy2: ethernet-phy@2 { 79 reg = <0>; 80 }; 81 82 ethphy3: ethernet-phy@3 { 83 reg = <0>; 84 }; 85}; 86 87&mac0 { 88 status = "okay"; 89 phy-mode = "rgmii"; 90 phy-handle = <ðphy0>; 91 pinctrl-names = "default"; 92 pinctrl-0 = <&pinctrl_rgmii1_default>; 93}; 94 95&mac1 { 96 status = "okay"; 97 phy-mode = "rgmii"; 98 phy-handle = <ðphy1>; 99 pinctrl-names = "default"; 100 pinctrl-0 = <&pinctrl_rgmii2_default>; 101}; 102#endif 103 104&mac2 { 105 status = "okay"; 106 phy-mode = "NC-SI"; 107 use-ncsi; 108 pinctrl-names = "default"; 109 pinctrl-0 = <&pinctrl_rmii3_default>; 110}; 111 112&mac3 { 113 status = "okay"; 114 phy-mode = "NC-SI"; 115 use-ncsi; 116 pinctrl-names = "default"; 117 pinctrl-0 = <&pinctrl_rmii4_default>; 118}; 119 120&fmc { 121 status = "okay"; 122 123 pinctrl-names = "default"; 124 pinctrl-0 = <&pinctrl_fmcquad_default>; 125 126 flash@0 { 127 compatible = "spi-flash", "sst,w25q256"; 128 status = "okay"; 129 spi-max-frequency = <50000000>; 130 spi-tx-bus-width = <4>; 131 spi-rx-bus-width = <4>; 132 }; 133 134 flash@1 { 135 compatible = "spi-flash", "sst,w25q256"; 136 status = "okay"; 137 spi-max-frequency = <50000000>; 138 spi-tx-bus-width = <4>; 139 spi-rx-bus-width = <4>; 140 }; 141 142 flash@2 { 143 compatible = "spi-flash", "sst,w25q256"; 144 status = "okay"; 145 spi-max-frequency = <50000000>; 146 spi-tx-bus-width = <4>; 147 spi-rx-bus-width = <4>; 148 }; 149}; 150 151&spi1 { 152 status = "okay"; 153 154 pinctrl-names = "default"; 155 pinctrl-0 = <&pinctrl_spi1_default &pinctrl_spi1abr_default 156 &pinctrl_spi1cs1_default &pinctrl_spi1wp_default 157 &pinctrl_spi1wp_default &pinctrl_spi1quad_default>; 158 159 flash@0 { 160 compatible = "spi-flash", "sst,w25q256"; 161 status = "okay"; 162 spi-max-frequency = <50000000>; 163 spi-tx-bus-width = <4>; 164 spi-rx-bus-width = <4>; 165 }; 166 167 flash@1 { 168 compatible = "spi-flash", "sst,w25q256"; 169 status = "okay"; 170 spi-max-frequency = <50000000>; 171 spi-tx-bus-width = <4>; 172 spi-rx-bus-width = <4>; 173 }; 174}; 175 176&spi2 { 177 status = "okay"; 178 179 pinctrl-names = "default"; 180 pinctrl-0 = <&pinctrl_spi2_default &pinctrl_spi2cs1_default 181 &pinctrl_spi2cs2_default &pinctrl_spi2quad_default>; 182 183 flash@0 { 184 compatible = "spi-flash", "sst,w25q256"; 185 status = "okay"; 186 spi-max-frequency = <50000000>; 187 spi-tx-bus-width = <4>; 188 spi-rx-bus-width = <4>; 189 }; 190 191 flash@1 { 192 compatible = "spi-flash", "sst,w25q256"; 193 status = "okay"; 194 spi-max-frequency = <50000000>; 195 spi-tx-bus-width = <4>; 196 spi-rx-bus-width = <4>; 197 }; 198 199 flash@2 { 200 compatible = "spi-flash", "sst,w25q256"; 201 status = "okay"; 202 spi-max-frequency = <50000000>; 203 spi-tx-bus-width = <4>; 204 spi-rx-bus-width = <4>; 205 }; 206}; 207 208&emmc { 209 u-boot,dm-pre-reloc; 210 timing-phase = <0x700ff>; 211}; 212 213&emmc_slot0 { 214 u-boot,dm-pre-reloc; 215 status = "okay"; 216 bus-width = <4>; 217 pinctrl-names = "default"; 218 pinctrl-0 = <&pinctrl_emmc_default>; 219 sdhci-drive-type = <1>; 220}; 221 222&sdhci { 223 timing-phase = <0xc6ffff>; 224}; 225 226&sdhci_slot0 { 227 status = "okay"; 228 bus-width = <4>; 229 pwr-gpios = <&gpio0 ASPEED_GPIO(V, 0) GPIO_ACTIVE_HIGH>; 230 pwr-sw-gpios = <&gpio0 ASPEED_GPIO(V, 1) GPIO_ACTIVE_HIGH>; 231 pinctrl-names = "default"; 232 pinctrl-0 = <&pinctrl_sd1_default>; 233 sdhci-drive-type = <1>; 234}; 235 236&sdhci_slot1 { 237 status = "okay"; 238 bus-width = <4>; 239 pwr-gpios = <&gpio0 ASPEED_GPIO(V, 2) GPIO_ACTIVE_HIGH>; 240 pwr-sw-gpios = <&gpio0 ASPEED_GPIO(V, 3) GPIO_ACTIVE_HIGH>; 241 pinctrl-names = "default"; 242 pinctrl-0 = <&pinctrl_sd2_default>; 243 sdhci-drive-type = <1>; 244}; 245 246&i2c4 { 247 status = "okay"; 248 249 pinctrl-names = "default"; 250 pinctrl-0 = <&pinctrl_i2c5_default>; 251}; 252 253&i2c5 { 254 status = "okay"; 255 256 pinctrl-names = "default"; 257 pinctrl-0 = <&pinctrl_i2c6_default>; 258}; 259 260&i2c6 { 261 status = "okay"; 262 263 pinctrl-names = "default"; 264 pinctrl-0 = <&pinctrl_i2c7_default>; 265}; 266 267&i2c7 { 268 status = "okay"; 269 270 pinctrl-names = "default"; 271 pinctrl-0 = <&pinctrl_i2c8_default>; 272}; 273 274&i2c8 { 275 status = "okay"; 276 277 pinctrl-names = "default"; 278 pinctrl-0 = <&pinctrl_i2c9_default>; 279}; 280 281&pcie_bridge1 { 282 status = "okay"; 283}; 284 285&h2x { 286 status = "okay"; 287}; 288 289#if 0 290&fsim0 { 291 status = "okay"; 292}; 293 294&fsim1 { 295 status = "okay"; 296}; 297#endif 298 299&ehci1 { 300 status = "okay"; 301}; 302 303&display_port { 304 status = "okay"; 305}; 306 307&scu { 308 mac0-clk-delay = <0x1d 0x1c 309 0x10 0x17 310 0x10 0x17>; 311 mac1-clk-delay = <0x1d 0x10 312 0x10 0x10 313 0x10 0x10>; 314 mac2-clk-delay = <0x0a 0x04 315 0x08 0x04 316 0x08 0x04>; 317 mac3-clk-delay = <0x0a 0x04 318 0x08 0x04 319 0x08 0x04>; 320}; 321