xref: /openbmc/u-boot/arch/arm/dts/ast2600-ncsi.dts (revision 47e496054e7689a63396afdc52e136afc02c891d)
1/dts-v1/;
2
3#include "ast2600-u-boot.dtsi"
4
5/ {
6	memory {
7		device_type = "memory";
8		reg = <0x80000000 0x40000000>;
9	};
10
11	chosen {
12		stdout-path = &uart5;
13	};
14
15	aliases {
16		spi0 = &fmc;
17		spi1 = &spi1;
18		spi2 = &spi2;
19#if 0
20		ethernet0 = &mac0;
21		ethernet1 = &mac1;
22#endif
23		ethernet2 = &mac2;
24		ethernet3 = &mac3;
25	};
26
27	cpus {
28		cpu@0 {
29			clock-frequency = <800000000>;
30		};
31		cpu@1 {
32			clock-frequency = <800000000>;
33		};
34	};
35};
36
37&uart5 {
38	u-boot,dm-pre-reloc;
39	status = "okay";
40};
41
42&sdrammc {
43	clock-frequency = <400000000>;
44};
45
46&wdt1 {
47	u-boot,dm-pre-reloc;
48	status = "okay";
49};
50
51&wdt2 {
52	u-boot,dm-pre-reloc;
53	status = "okay";
54};
55
56&wdt3 {
57	u-boot,dm-pre-reloc;
58	status = "okay";
59};
60
61&mdio {
62	status = "okay";
63};
64
65#if 0
66&mac0 {
67	status = "okay";
68	phy-mode = "rgmii";
69
70	pinctrl-names = "default";
71	pinctrl-0 = <&pinctrl_mac1link_default &pinctrl_mdio1_default>;
72};
73
74&mac1 {
75	status = "okay";
76
77	phy-mode = "rgmii";
78	pinctrl-names = "default";
79	pinctrl-0 = <&pinctrl_mac2link_default &pinctrl_mdio2_default>;
80};
81#endif
82
83&mac2 {
84	status = "okay";
85
86	phy-mode = "NC-SI";
87	use-ncsi;
88	pinctrl-names = "default";
89	pinctrl-0 = <&pinctrl_mac3link_default>;
90};
91
92&mac3 {
93	status = "okay";
94
95	phy-mode = "NC-SI";
96	use-ncsi;
97	pinctrl-names = "default";
98	pinctrl-0 = <&pinctrl_mac4link_default>;
99};
100
101&fmc {
102	status = "okay";
103#if 0
104	pinctrl-names = "default";
105	pinctrl-0 = <&pinctrl_fmcquad_default>;
106#endif
107	flash@0 {
108		compatible = "spi-flash", "sst,w25q256";
109		status = "okay";
110		spi-max-frequency = <50000000>;
111		spi-tx-bus-width = <2>;
112		spi-rx-bus-width = <2>;
113	};
114
115	flash@1 {
116		compatible = "spi-flash", "sst,w25q256";
117		status = "okay";
118		spi-max-frequency = <50000000>;
119		spi-tx-bus-width = <2>;
120		spi-rx-bus-width = <2>;
121    };
122
123	flash@2 {
124        compatible = "spi-flash", "sst,w25q256";
125        status = "okay";
126        spi-max-frequency = <50000000>;
127        spi-tx-bus-width = <2>;
128        spi-rx-bus-width = <2>;
129	};
130};
131
132&spi1 {
133	status = "okay";
134
135	pinctrl-names = "default";
136	pinctrl-0 = <&pinctrl_spi1_default &pinctrl_spi1abr_default
137			&pinctrl_spi1cs1_default &pinctrl_spi1wp_default
138			&pinctrl_spi1wp_default>;
139
140	flash@0 {
141		compatible = "spi-flash", "sst,w25q256";
142		status = "okay";
143		spi-max-frequency = <50000000>;
144		spi-tx-bus-width = <2>;
145		spi-rx-bus-width = <2>;
146	};
147
148	flash@1 {
149		compatible = "spi-flash", "sst,w25q256";
150		status = "okay";
151		spi-max-frequency = <50000000>;
152		spi-tx-bus-width = <2>;
153		spi-rx-bus-width = <2>;
154	};
155};
156
157&spi2 {
158	status = "okay";
159
160	pinctrl-names = "default";
161	pinctrl-0 = <&pinctrl_spi2_default &pinctrl_spi2cs1_default
162			&pinctrl_spi2cs2_default &pinctrl_spi2quad_default>;
163
164	flash@0 {
165		compatible = "spi-flash", "sst,w25q256";
166		status = "okay";
167		spi-max-frequency = <50000000>;
168		spi-tx-bus-width = <2>;
169		spi-rx-bus-width = <2>;
170	};
171
172	flash@1 {
173		compatible = "spi-flash", "sst,w25q256";
174		status = "okay";
175		spi-max-frequency = <50000000>;
176		spi-tx-bus-width = <2>;
177		spi-rx-bus-width = <2>;
178	};
179
180	flash@2 {
181		compatible = "spi-flash", "sst,w25q256";
182		status = "okay";
183		spi-max-frequency = <50000000>;
184		spi-tx-bus-width = <2>;
185		spi-rx-bus-width = <2>;
186	};
187};
188
189&emmc_slot0 {
190	status = "okay";
191	bus-width = <4>;
192	pinctrl-names = "default";
193	pinctrl-0 = <&pinctrl_emmc_default>;
194};
195
196#if 0
197&sdhci_slot0 {
198	status = "okay";
199	bus-width = <4>;
200	pwr-gpios = <&gpio0 ASPEED_GPIO(V, 0) GPIO_ACTIVE_HIGH>;
201	pwr-sw-gpios = <&gpio0 ASPEED_GPIO(V, 1) GPIO_ACTIVE_HIGH>;
202	pinctrl-names = "default";
203	pinctrl-0 = <&pinctrl_sd1_default>;
204};
205
206&sdhci_slot1 {
207	status = "okay";
208	bus-width = <4>;
209	pwr-gpios = <&gpio0 ASPEED_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
210	pwr-sw-gpios = <&gpio0 ASPEED_GPIO(V, 3) GPIO_ACTIVE_HIGH>;
211	pinctrl-names = "default";
212	pinctrl-0 = <&pinctrl_sd2_default>;
213};
214#endif
215
216&i2c4 {
217	status = "okay";
218
219	pinctrl-names = "default";
220	pinctrl-0 = <&pinctrl_i2c5_default>;
221};
222
223&i2c5 {
224	status = "okay";
225
226	pinctrl-names = "default";
227	pinctrl-0 = <&pinctrl_i2c6_default>;
228};
229
230&i2c6 {
231	status = "okay";
232
233	pinctrl-names = "default";
234	pinctrl-0 = <&pinctrl_i2c7_default>;
235};
236
237&i2c7 {
238	status = "okay";
239
240	pinctrl-names = "default";
241	pinctrl-0 = <&pinctrl_i2c8_default>;
242};
243
244&i2c8 {
245	status = "okay";
246
247	pinctrl-names = "default";
248	pinctrl-0 = <&pinctrl_i2c9_default>;
249};
250
251#if 0
252&pcie_bridge1 {
253	status = "okay";
254};
255
256&h2x {
257	status = "okay";
258};
259#endif
260