1// SPDX-License-Identifier: GPL-2.0+ 2/dts-v1/; 3 4#include "ast2600-u-boot.dtsi" 5 6/ { 7 model = "AST2600 Intel EGS server board"; 8 compatible = "aspeed,ast2600-intel", "aspeed,ast2600"; 9 10 memory { 11 device_type = "memory"; 12 reg = <0x80000000 0x40000000>; 13 }; 14 15 chosen { 16 stdout-path = &uart5; 17 }; 18 19 aliases { 20 mmc0 = &emmc_slot0; 21 mmc1 = &sdhci_slot0; 22 mmc2 = &sdhci_slot1; 23 spi0 = &fmc; 24 spi1 = &spi1; 25 spi2 = &spi2; 26 ethernet0 = &mac0; 27 ethernet1 = &mac1; 28 ethernet2 = &mac2; 29 ethernet3 = &mac3; 30 }; 31 32 cpus { 33 cpu@0 { 34 clock-frequency = <1200000000>; 35 }; 36 cpu@1 { 37 clock-frequency = <1200000000>; 38 }; 39 }; 40}; 41 42&uart5 { 43 u-boot,dm-pre-reloc; 44 status = "okay"; 45}; 46 47&sdrammc { 48 clock-frequency = <400000000>; 49}; 50 51&wdt1 { 52 status = "okay"; 53}; 54 55&wdt2 { 56 status = "okay"; 57}; 58 59&wdt3 { 60 status = "okay"; 61}; 62 63&mdio { 64 status = "okay"; 65 pinctrl-names = "default"; 66 pinctrl-0 = < &pinctrl_mdio1_default &pinctrl_mdio2_default 67 &pinctrl_mdio3_default &pinctrl_mdio4_default>; 68 #address-cells = <1>; 69 #size-cells = <0>; 70 ethphy0: ethernet-phy@0 { 71 reg = <0>; 72 }; 73 74 ethphy1: ethernet-phy@1 { 75 reg = <0>; 76 }; 77 78 ethphy2: ethernet-phy@2 { 79 reg = <0>; 80 }; 81 82 ethphy3: ethernet-phy@3 { 83 reg = <0>; 84 }; 85}; 86 87&mac0 { 88 status = "okay"; 89 phy-mode = "rgmii"; 90 phy-handle = <ðphy0>; 91 pinctrl-names = "default"; 92 pinctrl-0 = <&pinctrl_rgmii1_default>; 93}; 94 95&mac1 { 96 status = "okay"; 97 phy-mode = "rgmii"; 98 phy-handle = <ðphy1>; 99 pinctrl-names = "default"; 100 pinctrl-0 = <&pinctrl_rgmii2_default>; 101}; 102 103&mac2 { 104 status = "okay"; 105 phy-mode = "rgmii"; 106 phy-handle = <ðphy2>; 107 pinctrl-names = "default"; 108 pinctrl-0 = <&pinctrl_rgmii3_default>; 109}; 110 111&mac3 { 112 status = "okay"; 113 phy-mode = "rgmii"; 114 phy-handle = <ðphy3>; 115 pinctrl-names = "default"; 116 pinctrl-0 = <&pinctrl_rgmii4_default>; 117}; 118 119&fmc { 120 status = "okay"; 121 122 pinctrl-names = "default"; 123 pinctrl-0 = <&pinctrl_fmcquad_default>; 124 125 flash@0 { 126 compatible = "spi-flash", "sst,w25q256"; 127 status = "okay"; 128 spi-max-frequency = <50000000>; 129 spi-tx-bus-width = <4>; 130 spi-rx-bus-width = <4>; 131 }; 132 133 flash@1 { 134 compatible = "spi-flash", "sst,w25q256"; 135 status = "okay"; 136 spi-max-frequency = <50000000>; 137 spi-tx-bus-width = <4>; 138 spi-rx-bus-width = <4>; 139 }; 140 141 flash@2 { 142 compatible = "spi-flash", "sst,w25q256"; 143 status = "okay"; 144 spi-max-frequency = <50000000>; 145 spi-tx-bus-width = <4>; 146 spi-rx-bus-width = <4>; 147 }; 148}; 149 150&spi1 { 151 status = "okay"; 152 153 pinctrl-names = "default"; 154 pinctrl-0 = <&pinctrl_spi1_default &pinctrl_spi1abr_default 155 &pinctrl_spi1cs1_default &pinctrl_spi1wp_default 156 &pinctrl_spi1wp_default &pinctrl_spi1quad_default>; 157 158 flash@0 { 159 compatible = "spi-flash", "sst,w25q256"; 160 status = "okay"; 161 spi-max-frequency = <50000000>; 162 spi-tx-bus-width = <4>; 163 spi-rx-bus-width = <4>; 164 }; 165 166 flash@1 { 167 compatible = "spi-flash", "sst,w25q256"; 168 status = "okay"; 169 spi-max-frequency = <50000000>; 170 spi-tx-bus-width = <4>; 171 spi-rx-bus-width = <4>; 172 }; 173}; 174 175&spi2 { 176 status = "okay"; 177 178 pinctrl-names = "default"; 179 pinctrl-0 = <&pinctrl_spi2_default &pinctrl_spi2cs1_default 180 &pinctrl_spi2cs2_default &pinctrl_spi2quad_default>; 181 182 flash@0 { 183 compatible = "spi-flash", "sst,w25q256"; 184 status = "okay"; 185 spi-max-frequency = <50000000>; 186 spi-tx-bus-width = <4>; 187 spi-rx-bus-width = <4>; 188 }; 189 190 flash@1 { 191 compatible = "spi-flash", "sst,w25q256"; 192 status = "okay"; 193 spi-max-frequency = <50000000>; 194 spi-tx-bus-width = <4>; 195 spi-rx-bus-width = <4>; 196 }; 197 198 flash@2 { 199 compatible = "spi-flash", "sst,w25q256"; 200 status = "okay"; 201 spi-max-frequency = <50000000>; 202 spi-tx-bus-width = <4>; 203 spi-rx-bus-width = <4>; 204 }; 205}; 206 207&emmc { 208 u-boot,dm-pre-reloc; 209 timing-phase = <0x700ff>; 210}; 211 212&emmc_slot0 { 213 u-boot,dm-pre-reloc; 214 status = "okay"; 215 bus-width = <4>; 216 pinctrl-names = "default"; 217 pinctrl-0 = <&pinctrl_emmc_default>; 218 sdhci-drive-type = <1>; 219}; 220 221&sdhci { 222 timing-phase = <0xc6ffff>; 223}; 224 225&sdhci_slot0 { 226 status = "okay"; 227 bus-width = <4>; 228 pwr-gpios = <&gpio0 ASPEED_GPIO(V, 0) GPIO_ACTIVE_HIGH>; 229 pwr-sw-gpios = <&gpio0 ASPEED_GPIO(V, 1) GPIO_ACTIVE_HIGH>; 230 pinctrl-names = "default"; 231 pinctrl-0 = <&pinctrl_sd1_default>; 232 sdhci-drive-type = <1>; 233}; 234 235&sdhci_slot1 { 236 status = "okay"; 237 bus-width = <4>; 238 pwr-gpios = <&gpio0 ASPEED_GPIO(V, 2) GPIO_ACTIVE_HIGH>; 239 pwr-sw-gpios = <&gpio0 ASPEED_GPIO(V, 3) GPIO_ACTIVE_HIGH>; 240 pinctrl-names = "default"; 241 pinctrl-0 = <&pinctrl_sd2_default>; 242 sdhci-drive-type = <1>; 243}; 244 245&i2c4 { 246 status = "okay"; 247 248 pinctrl-names = "default"; 249 pinctrl-0 = <&pinctrl_i2c5_default>; 250}; 251 252&i2c5 { 253 status = "okay"; 254 255 pinctrl-names = "default"; 256 pinctrl-0 = <&pinctrl_i2c6_default>; 257}; 258 259&i2c6 { 260 status = "okay"; 261 262 pinctrl-names = "default"; 263 pinctrl-0 = <&pinctrl_i2c7_default>; 264}; 265 266&i2c7 { 267 status = "okay"; 268 269 pinctrl-names = "default"; 270 pinctrl-0 = <&pinctrl_i2c8_default>; 271}; 272 273&i2c8 { 274 status = "okay"; 275 276 pinctrl-names = "default"; 277 pinctrl-0 = <&pinctrl_i2c9_default>; 278}; 279 280&pcie_bridge1 { 281 status = "okay"; 282}; 283 284&h2x { 285 status = "okay"; 286}; 287 288#if 0 289&fsim0 { 290 status = "okay"; 291}; 292 293&fsim1 { 294 status = "okay"; 295}; 296#endif 297 298&ehci1 { 299 status = "okay"; 300}; 301 302&display_port { 303 status = "okay"; 304}; 305 306&scu { 307 mac0-clk-delay = <0x1d 0x1c 308 0x10 0x17 309 0x10 0x17>; 310 mac1-clk-delay = <0x1d 0x10 311 0x10 0x10 312 0x10 0x10>; 313 mac2-clk-delay = <0x0a 0x04 314 0x08 0x04 315 0x08 0x04>; 316 mac3-clk-delay = <0x0a 0x04 317 0x08 0x04 318 0x08 0x04>; 319}; 320