xref: /openbmc/u-boot/arch/arm/dts/ast2600-intel.dts (revision 902902db) 
1// SPDX-License-Identifier: GPL-2.0+
2/dts-v1/;
3
4#include "ast2600-u-boot.dtsi"
5
6/ {
7	model = "AST2600 Intel EGS server board";
8	compatible = "aspeed,ast2600-intel", "aspeed,ast2600";
9
10	memory {
11		device_type = "memory";
12		reg = <0x80000000 0x40000000>;
13	};
14
15	chosen {
16		stdout-path = &uart5;
17	};
18
19	aliases {
20		mmc0 = &emmc_slot0;
21		mmc1 = &sdhci_slot0;
22		mmc2 = &sdhci_slot1;
23		spi0 = &fmc;
24		spi1 = &spi1;
25		spi2 = &spi2;
26		ethernet0 = &mac0;
27		ethernet1 = &mac1;
28		ethernet2 = &mac2;
29		ethernet3 = &mac3;
30	};
31
32	cpus {
33		cpu@0 {
34			clock-frequency = <1200000000>;
35		};
36		cpu@1 {
37			clock-frequency = <1200000000>;
38		};
39	};
40};
41
42&uart5 {
43	u-boot,dm-pre-reloc;
44	status = "okay";
45};
46
47&sdrammc {
48	clock-frequency = <400000000>;
49};
50
51&wdt1 {
52	status = "okay";
53};
54
55&wdt2 {
56	status = "okay";
57};
58
59&wdt3 {
60	status = "okay";
61};
62
63&mdio {
64	status = "okay";
65	pinctrl-names = "default";
66	pinctrl-0 = <	&pinctrl_mdio1_default &pinctrl_mdio2_default
67			&pinctrl_mdio3_default &pinctrl_mdio4_default>;
68	#address-cells = <1>;
69	#size-cells = <0>;
70	ethphy0: ethernet-phy@0 {
71		reg = <0>;
72	};
73
74	ethphy1: ethernet-phy@1 {
75		reg = <0>;
76	};
77
78	ethphy2: ethernet-phy@2 {
79		reg = <0>;
80	};
81
82	ethphy3: ethernet-phy@3 {
83		reg = <0>;
84	};
85};
86
87&mac0 {
88	status = "okay";
89	phy-mode = "rgmii";
90	phy-handle = <&ethphy0>;
91	pinctrl-names = "default";
92	pinctrl-0 = <&pinctrl_rgmii1_default>;
93};
94
95&mac1 {
96	status = "okay";
97	phy-mode = "rgmii";
98	phy-handle = <&ethphy1>;
99	pinctrl-names = "default";
100	pinctrl-0 = <&pinctrl_rgmii2_default>;
101};
102
103&mac2 {
104	status = "okay";
105	phy-mode = "rgmii";
106	phy-handle = <&ethphy2>;
107	pinctrl-names = "default";
108	pinctrl-0 = <&pinctrl_rgmii3_default>;
109};
110
111&mac3 {
112	status = "okay";
113	phy-mode = "rgmii";
114	phy-handle = <&ethphy3>;
115	pinctrl-names = "default";
116	pinctrl-0 = <&pinctrl_rgmii4_default>;
117};
118
119&fmc {
120	status = "okay";
121
122	pinctrl-names = "default";
123	pinctrl-0 = <&pinctrl_fmcquad_default>;
124
125	flash@0 {
126		status = "okay";
127		spi-max-frequency = <50000000>;
128		spi-tx-bus-width = <4>;
129		spi-rx-bus-width = <4>;
130	};
131
132	flash@1 {
133		status = "okay";
134		spi-max-frequency = <50000000>;
135		spi-tx-bus-width = <4>;
136		spi-rx-bus-width = <4>;
137	};
138
139	flash@2 {
140		status = "okay";
141		spi-max-frequency = <50000000>;
142		spi-tx-bus-width = <4>;
143		spi-rx-bus-width = <4>;
144	};
145};
146
147&spi1 {
148	status = "okay";
149
150	pinctrl-names = "default";
151	pinctrl-0 = <&pinctrl_spi1_default &pinctrl_spi1abr_default
152			&pinctrl_spi1cs1_default &pinctrl_spi1wp_default
153			&pinctrl_spi1wp_default &pinctrl_spi1quad_default>;
154
155	flash@0 {
156		status = "okay";
157		spi-max-frequency = <50000000>;
158		spi-tx-bus-width = <4>;
159		spi-rx-bus-width = <4>;
160	};
161
162	flash@1 {
163		status = "okay";
164		spi-max-frequency = <50000000>;
165		spi-tx-bus-width = <4>;
166		spi-rx-bus-width = <4>;
167	};
168};
169
170&spi2 {
171	status = "okay";
172
173	pinctrl-names = "default";
174	pinctrl-0 = <&pinctrl_spi2_default &pinctrl_spi2cs1_default
175			&pinctrl_spi2cs2_default &pinctrl_spi2quad_default>;
176
177	flash@0 {
178		status = "okay";
179		spi-max-frequency = <50000000>;
180		spi-tx-bus-width = <4>;
181		spi-rx-bus-width = <4>;
182	};
183
184	flash@1 {
185		status = "okay";
186		spi-max-frequency = <50000000>;
187		spi-tx-bus-width = <4>;
188		spi-rx-bus-width = <4>;
189	};
190
191	flash@2 {
192		status = "okay";
193		spi-max-frequency = <50000000>;
194		spi-tx-bus-width = <4>;
195		spi-rx-bus-width = <4>;
196	};
197};
198
199&emmc {
200	u-boot,dm-pre-reloc;
201	timing-phase = <0x700ff>;
202};
203
204&emmc_slot0 {
205	u-boot,dm-pre-reloc;
206	status = "okay";
207	bus-width = <4>;
208	pinctrl-names = "default";
209	pinctrl-0 = <&pinctrl_emmc_default>;
210	sdhci-drive-type = <1>;
211};
212
213&sdhci {
214	timing-phase = <0xc6ffff>;
215};
216
217&sdhci_slot0 {
218	status = "okay";
219	bus-width = <4>;
220	pwr-gpios = <&gpio0 ASPEED_GPIO(V, 0) GPIO_ACTIVE_HIGH>;
221	pwr-sw-gpios = <&gpio0 ASPEED_GPIO(V, 1) GPIO_ACTIVE_HIGH>;
222	pinctrl-names = "default";
223	pinctrl-0 = <&pinctrl_sd1_default>;
224	sdhci-drive-type = <1>;
225};
226
227&sdhci_slot1 {
228	status = "okay";
229	bus-width = <4>;
230	pwr-gpios = <&gpio0 ASPEED_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
231	pwr-sw-gpios = <&gpio0 ASPEED_GPIO(V, 3) GPIO_ACTIVE_HIGH>;
232	pinctrl-names = "default";
233	pinctrl-0 = <&pinctrl_sd2_default>;
234	sdhci-drive-type = <1>;
235};
236
237&i2c4 {
238	status = "okay";
239
240	pinctrl-names = "default";
241	pinctrl-0 = <&pinctrl_i2c5_default>;
242};
243
244&i2c5 {
245	status = "okay";
246
247	pinctrl-names = "default";
248	pinctrl-0 = <&pinctrl_i2c6_default>;
249};
250
251&i2c6 {
252	status = "okay";
253
254	pinctrl-names = "default";
255	pinctrl-0 = <&pinctrl_i2c7_default>;
256};
257
258&i2c7 {
259	status = "okay";
260
261	pinctrl-names = "default";
262	pinctrl-0 = <&pinctrl_i2c8_default>;
263};
264
265&i2c8 {
266	status = "okay";
267
268	pinctrl-names = "default";
269	pinctrl-0 = <&pinctrl_i2c9_default>;
270};
271
272#if 0
273&fsim0 {
274	status = "okay";
275};
276
277&fsim1 {
278	status = "okay";
279};
280#endif
281
282&ehci1 {
283	status = "okay";
284};
285
286&display_port {
287	status = "okay";
288};
289
290&scu {
291	mac0-clk-delay = <0x1d 0x1c
292			  0x10 0x17
293			  0x10 0x17>;
294	mac1-clk-delay = <0x1d 0x10
295			  0x10 0x10
296			  0x10 0x10>;
297	mac2-clk-delay = <0x0a 0x04
298			  0x08 0x04
299			  0x08 0x04>;
300	mac3-clk-delay = <0x0a 0x04
301			  0x08 0x04
302			  0x08 0x04>;
303};
304
305&hace {
306	u-boot,dm-pre-reloc;
307	status = "okay";
308};
309
310&acry {
311	u-boot,dm-pre-reloc;
312	status = "okay";
313};
314