1/dts-v1/; 2 3#include "ast2600-u-boot.dtsi" 4 5/ { 6 model = "AST2600 EVB"; 7 compatible = "aspeed,ast2600-evb", "aspeed,ast2600"; 8 9 memory { 10 device_type = "memory"; 11 reg = <0x80000000 0x40000000>; 12 }; 13 14 chosen { 15 stdout-path = &uart5; 16 }; 17 18 aliases { 19 mmc0 = &emmc_slot0; 20 mmc1 = &sdhci_slot0; 21 mmc2 = &sdhci_slot1; 22 spi0 = &fmc; 23 spi1 = &spi1; 24 spi2 = &spi2; 25 ethernet0 = &mac0; 26 ethernet1 = &mac1; 27 ethernet2 = &mac2; 28 ethernet3 = &mac3; 29 }; 30 31 cpus { 32 cpu@0 { 33 clock-frequency = <800000000>; 34 }; 35 cpu@1 { 36 clock-frequency = <800000000>; 37 }; 38 }; 39}; 40 41&uart5 { 42 u-boot,dm-pre-reloc; 43 status = "okay"; 44}; 45 46&sdrammc { 47 clock-frequency = <400000000>; 48}; 49 50&wdt1 { 51 status = "okay"; 52}; 53 54&wdt2 { 55 status = "okay"; 56}; 57 58&wdt3 { 59 status = "okay"; 60}; 61 62&mdio { 63 status = "okay"; 64 pinctrl-names = "default"; 65 pinctrl-0 = < &pinctrl_mdio1_default &pinctrl_mdio2_default 66 &pinctrl_mdio3_default &pinctrl_mdio4_default>; 67 #address-cells = <1>; 68 #size-cells = <0>; 69 ethphy0: ethernet-phy@0 { 70 reg = <0>; 71 }; 72 73 ethphy1: ethernet-phy@1 { 74 reg = <0>; 75 }; 76 77 ethphy2: ethernet-phy@2 { 78 reg = <0>; 79 }; 80 81 ethphy3: ethernet-phy@3 { 82 reg = <0>; 83 }; 84}; 85 86&mac0 { 87 status = "okay"; 88 phy-mode = "rgmii-rxid"; 89 phy-handle = <ðphy0>; 90 pinctrl-names = "default"; 91 pinctrl-0 = <&pinctrl_rgmii1_default>; 92}; 93 94&mac1 { 95 status = "okay"; 96 phy-mode = "rgmii-rxid"; 97 phy-handle = <ðphy1>; 98 pinctrl-names = "default"; 99 pinctrl-0 = <&pinctrl_rgmii2_default>; 100}; 101 102&mac2 { 103 status = "okay"; 104 phy-mode = "rgmii"; 105 phy-handle = <ðphy2>; 106 pinctrl-names = "default"; 107 pinctrl-0 = <&pinctrl_rgmii3_default>; 108}; 109 110&mac3 { 111 status = "okay"; 112 phy-mode = "rgmii"; 113 phy-handle = <ðphy3>; 114 pinctrl-names = "default"; 115 pinctrl-0 = <&pinctrl_rgmii4_default>; 116}; 117 118&fmc { 119 status = "okay"; 120 121 pinctrl-names = "default"; 122 pinctrl-0 = <&pinctrl_fmcquad_default>; 123 124 flash@0 { 125 compatible = "spi-flash", "sst,w25q256"; 126 status = "okay"; 127 spi-max-frequency = <50000000>; 128 spi-tx-bus-width = <4>; 129 spi-rx-bus-width = <4>; 130 }; 131 132 flash@1 { 133 compatible = "spi-flash", "sst,w25q256"; 134 status = "okay"; 135 spi-max-frequency = <50000000>; 136 spi-tx-bus-width = <4>; 137 spi-rx-bus-width = <4>; 138 }; 139 140 flash@2 { 141 compatible = "spi-flash", "sst,w25q256"; 142 status = "okay"; 143 spi-max-frequency = <50000000>; 144 spi-tx-bus-width = <4>; 145 spi-rx-bus-width = <4>; 146 }; 147}; 148 149&spi1 { 150 status = "okay"; 151 152 pinctrl-names = "default"; 153 pinctrl-0 = <&pinctrl_spi1_default &pinctrl_spi1abr_default 154 &pinctrl_spi1cs1_default &pinctrl_spi1wp_default 155 &pinctrl_spi1wp_default &pinctrl_spi1quad_default>; 156 157 flash@0 { 158 compatible = "spi-flash", "sst,w25q256"; 159 status = "okay"; 160 spi-max-frequency = <50000000>; 161 spi-tx-bus-width = <4>; 162 spi-rx-bus-width = <4>; 163 }; 164 165 flash@1 { 166 compatible = "spi-flash", "sst,w25q256"; 167 status = "okay"; 168 spi-max-frequency = <50000000>; 169 spi-tx-bus-width = <4>; 170 spi-rx-bus-width = <4>; 171 }; 172}; 173 174&spi2 { 175 status = "okay"; 176 177 pinctrl-names = "default"; 178 pinctrl-0 = <&pinctrl_spi2_default &pinctrl_spi2cs1_default 179 &pinctrl_spi2cs2_default &pinctrl_spi2quad_default>; 180 181 flash@0 { 182 compatible = "spi-flash", "sst,w25q256"; 183 status = "okay"; 184 spi-max-frequency = <50000000>; 185 spi-tx-bus-width = <4>; 186 spi-rx-bus-width = <4>; 187 }; 188 189 flash@1 { 190 compatible = "spi-flash", "sst,w25q256"; 191 status = "okay"; 192 spi-max-frequency = <50000000>; 193 spi-tx-bus-width = <4>; 194 spi-rx-bus-width = <4>; 195 }; 196 197 flash@2 { 198 compatible = "spi-flash", "sst,w25q256"; 199 status = "okay"; 200 spi-max-frequency = <50000000>; 201 spi-tx-bus-width = <4>; 202 spi-rx-bus-width = <4>; 203 }; 204}; 205 206&emmc { 207 u-boot,dm-pre-reloc; 208 timing-phase = <0x700ff>; 209}; 210 211&emmc_slot0 { 212 u-boot,dm-pre-reloc; 213 status = "okay"; 214 bus-width = <4>; 215 pinctrl-names = "default"; 216 pinctrl-0 = <&pinctrl_emmc_default>; 217 sdhci-drive-type = <1>; 218}; 219 220&sdhci { 221 timing-phase = <0xc6ffff>; 222}; 223 224&sdhci_slot0 { 225 status = "okay"; 226 bus-width = <4>; 227 pwr-gpios = <&gpio0 ASPEED_GPIO(V, 0) GPIO_ACTIVE_HIGH>; 228 pwr-sw-gpios = <&gpio0 ASPEED_GPIO(V, 1) GPIO_ACTIVE_HIGH>; 229 pinctrl-names = "default"; 230 pinctrl-0 = <&pinctrl_sd1_default>; 231 sdhci-drive-type = <1>; 232}; 233 234&sdhci_slot1 { 235 status = "okay"; 236 bus-width = <4>; 237 pwr-gpios = <&gpio0 ASPEED_GPIO(V, 2) GPIO_ACTIVE_HIGH>; 238 pwr-sw-gpios = <&gpio0 ASPEED_GPIO(V, 3) GPIO_ACTIVE_HIGH>; 239 pinctrl-names = "default"; 240 pinctrl-0 = <&pinctrl_sd2_default>; 241 sdhci-drive-type = <1>; 242}; 243 244&i2c4 { 245 status = "okay"; 246 247 pinctrl-names = "default"; 248 pinctrl-0 = <&pinctrl_i2c5_default>; 249}; 250 251&i2c5 { 252 status = "okay"; 253 254 pinctrl-names = "default"; 255 pinctrl-0 = <&pinctrl_i2c6_default>; 256}; 257 258&i2c6 { 259 status = "okay"; 260 261 pinctrl-names = "default"; 262 pinctrl-0 = <&pinctrl_i2c7_default>; 263}; 264 265&i2c7 { 266 status = "okay"; 267 268 pinctrl-names = "default"; 269 pinctrl-0 = <&pinctrl_i2c8_default>; 270}; 271 272&i2c8 { 273 status = "okay"; 274 275 pinctrl-names = "default"; 276 pinctrl-0 = <&pinctrl_i2c9_default>; 277}; 278 279&pcie_bridge1 { 280 status = "okay"; 281}; 282 283&h2x { 284 status = "okay"; 285}; 286 287#if 0 288&fsim0 { 289 status = "okay"; 290}; 291 292&fsim1 { 293 status = "okay"; 294}; 295#endif 296 297&ehci1 { 298 status = "okay"; 299}; 300 301&display_port { 302 status = "okay"; 303}; 304 305&scu { 306 mac0-clk-delay = <0x15 0x0a 307 0x10 0x10 308 0x10 0x10>; 309 mac1-clk-delay = <0x15 0x0a 310 0x10 0x10 311 0x10 0x10>; 312 mac2-clk-delay = <0x0a 0x04 313 0x08 0x04 314 0x08 0x04>; 315 mac3-clk-delay = <0x0a 0x04 316 0x08 0x04 317 0x08 0x04>; 318}; 319