1/* 2 * This device tree is copied from 3 * https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi 4 */ 5#include "skeleton.dtsi" 6 7/ { 8 model = "Aspeed BMC"; 9 compatible = "aspeed,ast2500"; 10 #address-cells = <1>; 11 #size-cells = <1>; 12 interrupt-parent = <&vic>; 13 14 aliases { 15 i2c0 = &i2c0; 16 i2c1 = &i2c1; 17 i2c2 = &i2c2; 18 i2c3 = &i2c3; 19 i2c4 = &i2c4; 20 i2c5 = &i2c5; 21 i2c6 = &i2c6; 22 i2c7 = &i2c7; 23 i2c8 = &i2c8; 24 i2c9 = &i2c9; 25 i2c10 = &i2c10; 26 i2c11 = &i2c11; 27 i2c12 = &i2c12; 28 i2c13 = &i2c13; 29 serial0 = &uart1; 30 serial1 = &uart2; 31 serial2 = &uart3; 32 serial3 = &uart4; 33 serial4 = &uart5; 34 serial5 = &vuart; 35 }; 36 37 cpus { 38 #address-cells = <1>; 39 #size-cells = <0>; 40 41 cpu@0 { 42 compatible = "arm,arm1176jzf-s"; 43 device_type = "cpu"; 44 reg = <0>; 45 }; 46 }; 47 48 memory@80000000 { 49 device_type = "memory"; 50 reg = <0x80000000 0>; 51 }; 52 53 ahb { 54 compatible = "simple-bus"; 55 #address-cells = <1>; 56 #size-cells = <1>; 57 ranges; 58 59 fmc: flash-controller@1e620000 { 60 reg = < 0x1e620000 0xc4 61 0x20000000 0x10000000 >; 62 #address-cells = <1>; 63 #size-cells = <0>; 64 compatible = "aspeed,ast2500-fmc"; 65 status = "disabled"; 66 interrupts = <19>; 67 clocks = <&scu ASPEED_CLK_AHB>; 68 flash@0 { 69 reg = < 0 >; 70 compatible = "jedec,spi-nor"; 71 status = "disabled"; 72 }; 73 flash@1 { 74 reg = < 1 >; 75 compatible = "jedec,spi-nor"; 76 status = "disabled"; 77 }; 78 flash@2 { 79 reg = < 2 >; 80 compatible = "jedec,spi-nor"; 81 status = "disabled"; 82 }; 83 }; 84 85 spi1: flash-controller@1e630000 { 86 reg = < 0x1e630000 0xc4 87 0x30000000 0x08000000 >; 88 #address-cells = <1>; 89 #size-cells = <0>; 90 compatible = "aspeed,ast2500-spi"; 91 clocks = <&scu ASPEED_CLK_AHB>; 92 status = "disabled"; 93 flash@0 { 94 reg = < 0 >; 95 compatible = "jedec,spi-nor"; 96 status = "disabled"; 97 }; 98 flash@1 { 99 reg = < 1 >; 100 compatible = "jedec,spi-nor"; 101 status = "disabled"; 102 }; 103 }; 104 105 spi2: flash-controller@1e631000 { 106 reg = < 0x1e631000 0xc4 107 0x38000000 0x08000000 >; 108 #address-cells = <1>; 109 #size-cells = <0>; 110 compatible = "aspeed,ast2500-spi"; 111 clocks = <&scu ASPEED_CLK_AHB>; 112 status = "disabled"; 113 flash@0 { 114 reg = < 0 >; 115 compatible = "jedec,spi-nor"; 116 status = "disabled"; 117 }; 118 flash@1 { 119 reg = < 1 >; 120 compatible = "jedec,spi-nor"; 121 status = "disabled"; 122 }; 123 }; 124 125 vic: interrupt-controller@1e6c0080 { 126 compatible = "aspeed,ast2400-vic"; 127 interrupt-controller; 128 #interrupt-cells = <1>; 129 valid-sources = <0xfefff7ff 0x0807ffff>; 130 reg = <0x1e6c0080 0x80>; 131 }; 132 133 mac0: ethernet@1e660000 { 134 compatible = "aspeed,ast2500-mac", "faraday,ftgmac100"; 135 reg = <0x1e660000 0x180>; 136 interrupts = <2>; 137 clocks = <&scu ASPEED_CLK_GATE_MAC1CLK>, <&scu ASPEED_CLK_D2PLL>; 138 status = "disabled"; 139 }; 140 141 mac1: ethernet@1e680000 { 142 compatible = "aspeed,ast2500-mac", "faraday,ftgmac100"; 143 reg = <0x1e680000 0x180>; 144 interrupts = <3>; 145 clocks = <&scu ASPEED_CLK_GATE_MAC2CLK>, <&scu ASPEED_CLK_D2PLL>; 146 status = "disabled"; 147 }; 148 149 ehci0: usb@1e6a1000 { 150 compatible = "aspeed,ast2500-ehci", "generic-ehci"; 151 reg = <0x1e6a1000 0x100>; 152 interrupts = <5>; 153 status = "disabled"; 154 }; 155 156 ehci1: usb@1e6a3000 { 157 compatible = "aspeed,ast2500-ehci", "generic-ehci"; 158 reg = <0x1e6a3000 0x100>; 159 interrupts = <13>; 160 status = "disabled"; 161 }; 162 163 uhci: usb@1e6b0000 { 164 compatible = "aspeed,ast2500-uhci", "generic-uhci"; 165 reg = <0x1e6b0000 0x100>; 166 interrupts = <14>; 167 #ports = <2>; 168 status = "disabled"; 169 }; 170 171 apb { 172 compatible = "simple-bus"; 173 #address-cells = <1>; 174 #size-cells = <1>; 175 ranges; 176 177 syscon: syscon@1e6e2000 { 178 compatible = "aspeed,g5-scu", "syscon", "simple-mfd"; 179 reg = <0x1e6e2000 0x1a8>; 180 #clock-cells = <1>; 181 #reset-cells = <1>; 182 183 pinctrl: pinctrl { 184 compatible = "aspeed,g5-pinctrl"; 185 aspeed,external-nodes = <&gfx &lhc>; 186 187 }; 188 }; 189 190 rng: hwrng@1e6e2078 { 191 compatible = "timeriomem_rng"; 192 reg = <0x1e6e2078 0x4>; 193 period = <1>; 194 quality = <100>; 195 }; 196 197 gfx: display@1e6e6000 { 198 compatible = "aspeed,ast2500-gfx", "syscon"; 199 reg = <0x1e6e6000 0x1000>; 200 reg-io-width = <4>; 201 }; 202 203 adc: adc@1e6e9000 { 204 compatible = "aspeed,ast2500-adc"; 205 reg = <0x1e6e9000 0xb0>; 206 #io-channel-cells = <1>; 207 status = "disabled"; 208 }; 209 210 sram@1e720000 { 211 compatible = "mmio-sram"; 212 reg = <0x1e720000 0x9000>; // 36K 213 }; 214 215 sdhci: sdhci@1e740000 { 216 #interrupt-cells = <1>; 217 compatible = "aspeed,aspeed-sdhci-irq", "simple-mfd"; 218 reg = <0x1e740000 0x1000>; 219 interrupts = <26>; 220 interrupt-controller; 221 clocks = <&scu ASPEED_CLK_GATE_SDCLK>, <&scu ASPEED_CLK_GATE_SDEXTCLK>; 222 clock-names = "ctrlclk", "extclk"; 223 #address-cells = <1>; 224 #size-cells = <1>; 225 ranges = <0x0 0x1e740000 0x1000>; 226 227 sdhci_slot0: sdhci_slot0@100 { 228 compatible = "aspeed,sdhci-ast2500"; 229 reg = <0x100 0x100>; 230 interrupts = <0>; 231 interrupt-parent = <&sdhci>; 232 sdhci,auto-cmd12; 233 clocks = <&scu ASPEED_CLK_SDIO>; 234 status = "disabled"; 235 }; 236 237 sdhci_slot1: sdhci_slot1@200 { 238 compatible = "aspeed,sdhci-ast2500"; 239 reg = <0x200 0x100>; 240 interrupts = <1>; 241 interrupt-parent = <&sdhci>; 242 sdhci,auto-cmd12; 243 clocks = <&scu ASPEED_CLK_SDIO>; 244 status = "disabled"; 245 }; 246 247 }; 248 249 gpio: gpio@1e780000 { 250 #gpio-cells = <2>; 251 gpio-controller; 252 compatible = "aspeed,ast2500-gpio"; 253 reg = <0x1e780000 0x1000>; 254 interrupts = <20>; 255 gpio-ranges = <&pinctrl 0 0 220>; 256 ngpios = <228>; 257 interrupt-controller; 258 }; 259 260 timer: timer@1e782000 { 261 /* This timer is a Faraday FTTMR010 derivative */ 262 compatible = "aspeed,ast2400-timer"; 263 reg = <0x1e782000 0x90>; 264 }; 265 266 uart1: serial@1e783000 { 267 compatible = "ns16550a"; 268 reg = <0x1e783000 0x20>; 269 reg-shift = <2>; 270 interrupts = <9>; 271 clocks = <&scu ASPEED_CLK_GATE_UART1CLK>; 272 clock-frequency = <24000000>; 273 no-loopback-test; 274 status = "disabled"; 275 }; 276 277 uart5: serial@1e784000 { 278 compatible = "ns16550a"; 279 reg = <0x1e784000 0x20>; 280 reg-shift = <2>; 281 interrupts = <10>; 282 clocks = <&scu ASPEED_CLK_GATE_UART5CLK>; 283 clock-frequency = <24000000>; 284 no-loopback-test; 285 status = "disabled"; 286 }; 287 288 wdt1: watchdog@1e785000 { 289 compatible = "aspeed,wdt"; 290 reg = <0x1e785000 0x1c>; 291 interrupts = <27>; 292 }; 293 294 wdt2: watchdog@1e785020 { 295 compatible = "aspeed,wdt"; 296 reg = <0x1e785020 0x1c>; 297 interrupts = <27>; 298 status = "disabled"; 299 }; 300 301 wdt3: watchdog@1e785040 { 302 compatible = "aspeed,wdt"; 303 reg = <0x1e785040 0x1c>; 304 status = "disabled"; 305 }; 306 307 pwm_tacho: pwm-tacho-controller@1e786000 { 308 compatible = "aspeed,ast2500-pwm-tacho"; 309 #address-cells = <1>; 310 #size-cells = <0>; 311 reg = <0x1e786000 0x1000>; 312 status = "disabled"; 313 }; 314 315 vuart: serial@1e787000 { 316 compatible = "aspeed,ast2500-vuart"; 317 reg = <0x1e787000 0x40>; 318 reg-shift = <2>; 319 interrupts = <8>; 320 no-loopback-test; 321 status = "disabled"; 322 }; 323 324 lpc: lpc@1e789000 { 325 compatible = "aspeed,ast2500-lpc", "simple-mfd"; 326 reg = <0x1e789000 0x1000>; 327 328 #address-cells = <1>; 329 #size-cells = <1>; 330 ranges = <0x0 0x1e789000 0x1000>; 331 332 lpc_bmc: lpc-bmc@0 { 333 compatible = "aspeed,ast2500-lpc-bmc"; 334 reg = <0x0 0x80>; 335 }; 336 337 lpc_host: lpc-host@80 { 338 compatible = "aspeed,ast2500-lpc-host", "simple-mfd", "syscon"; 339 reg = <0x80 0x1e0>; 340 reg-io-width = <4>; 341 342 #address-cells = <1>; 343 #size-cells = <1>; 344 ranges = <0x0 0x80 0x1e0>; 345 346 lpc_ctrl: lpc-ctrl@0 { 347 compatible = "aspeed,ast2500-lpc-ctrl"; 348 reg = <0x0 0x80>; 349 status = "disabled"; 350 }; 351 352 lpc_snoop: lpc-snoop@0 { 353 compatible = "aspeed,ast2500-lpc-snoop"; 354 reg = <0x0 0x80>; 355 interrupts = <8>; 356 status = "disabled"; 357 }; 358 359 lhc: lhc@20 { 360 compatible = "aspeed,ast2500-lhc"; 361 reg = <0x20 0x24 0x48 0x8>; 362 }; 363 364 lpc_reset: reset-controller@18 { 365 compatible = "aspeed,ast2500-lpc-reset"; 366 reg = <0x18 0x4>; 367 #reset-cells = <1>; 368 }; 369 370 ibt: ibt@c0 { 371 compatible = "aspeed,ast2500-ibt-bmc"; 372 reg = <0xc0 0x18>; 373 interrupts = <8>; 374 status = "disabled"; 375 }; 376 }; 377 }; 378 379 uart2: serial@1e78d000 { 380 compatible = "ns16550a"; 381 reg = <0x1e78d000 0x20>; 382 reg-shift = <2>; 383 interrupts = <32>; 384 clocks = <&scu ASPEED_CLK_GATE_UART2CLK>; 385 clock-frequency = <24000000>; 386 no-loopback-test; 387 status = "disabled"; 388 }; 389 390 uart3: serial@1e78e000 { 391 compatible = "ns16550a"; 392 reg = <0x1e78e000 0x20>; 393 reg-shift = <2>; 394 interrupts = <33>; 395 clocks = <&scu ASPEED_CLK_GATE_UART3CLK>; 396 clock-frequency = <24000000>; 397 no-loopback-test; 398 status = "disabled"; 399 }; 400 401 uart4: serial@1e78f000 { 402 compatible = "ns16550a"; 403 reg = <0x1e78f000 0x20>; 404 reg-shift = <2>; 405 interrupts = <34>; 406 clocks = <&scu ASPEED_CLK_GATE_UART4CLK>; 407 clock-frequency = <24000000>; 408 no-loopback-test; 409 status = "disabled"; 410 }; 411 412 i2c: i2c@1e78a000 { 413 compatible = "simple-bus"; 414 #address-cells = <1>; 415 #size-cells = <1>; 416 ranges = <0 0x1e78a000 0x1000>; 417 }; 418 }; 419 }; 420}; 421 422&i2c { 423 i2c_ic: interrupt-controller@0 { 424 #interrupt-cells = <1>; 425 compatible = "aspeed,ast2500-i2c-ic"; 426 reg = <0x0 0x40>; 427 interrupts = <12>; 428 interrupt-controller; 429 resets = <&rst ASPEED_RESET_I2C>; 430 }; 431 432 i2c0: i2c-bus@40 { 433 #address-cells = <1>; 434 #size-cells = <0>; 435 #interrupt-cells = <1>; 436 437 reg = <0x40 0x40>; 438 compatible = "aspeed,ast2500-i2c-bus"; 439 bus-frequency = <100000>; 440 interrupts = <0>; 441 interrupt-parent = <&i2c_ic>; 442 clocks = <&scu ASPEED_CLK_APB>; 443 status = "disabled"; 444 /* Does not need pinctrl properties */ 445 }; 446 447 i2c1: i2c-bus@80 { 448 #address-cells = <1>; 449 #size-cells = <0>; 450 #interrupt-cells = <1>; 451 452 reg = <0x80 0x40>; 453 compatible = "aspeed,ast2500-i2c-bus"; 454 bus-frequency = <100000>; 455 interrupts = <1>; 456 interrupt-parent = <&i2c_ic>; 457 clocks = <&scu ASPEED_CLK_APB>; 458 status = "disabled"; 459 /* Does not need pinctrl properties */ 460 }; 461 462 i2c2: i2c-bus@c0 { 463 #address-cells = <1>; 464 #size-cells = <0>; 465 #interrupt-cells = <1>; 466 467 reg = <0xc0 0x40>; 468 compatible = "aspeed,ast2500-i2c-bus"; 469 bus-frequency = <100000>; 470 interrupts = <2>; 471 interrupt-parent = <&i2c_ic>; 472 clocks = <&scu ASPEED_CLK_APB>; 473 pinctrl-names = "default"; 474 pinctrl-0 = <&pinctrl_i2c3_default>; 475 status = "disabled"; 476 }; 477 478 i2c3: i2c-bus@100 { 479 #address-cells = <1>; 480 #size-cells = <0>; 481 #interrupt-cells = <1>; 482 483 reg = <0x100 0x40>; 484 compatible = "aspeed,ast2500-i2c-bus"; 485 bus-frequency = <100000>; 486 interrupts = <3>; 487 interrupt-parent = <&i2c_ic>; 488 clocks = <&scu ASPEED_CLK_APB>; 489 pinctrl-names = "default"; 490 pinctrl-0 = <&pinctrl_i2c4_default>; 491 status = "disabled"; 492 }; 493 494 i2c4: i2c-bus@140 { 495 #address-cells = <1>; 496 #size-cells = <0>; 497 #interrupt-cells = <1>; 498 499 reg = <0x140 0x40>; 500 compatible = "aspeed,ast2500-i2c-bus"; 501 bus-frequency = <100000>; 502 interrupts = <4>; 503 interrupt-parent = <&i2c_ic>; 504 clocks = <&scu ASPEED_CLK_APB>; 505 pinctrl-names = "default"; 506 pinctrl-0 = <&pinctrl_i2c5_default>; 507 status = "disabled"; 508 }; 509 510 i2c5: i2c-bus@180 { 511 #address-cells = <1>; 512 #size-cells = <0>; 513 #interrupt-cells = <1>; 514 515 reg = <0x180 0x40>; 516 compatible = "aspeed,ast2500-i2c-bus"; 517 bus-frequency = <100000>; 518 interrupts = <5>; 519 interrupt-parent = <&i2c_ic>; 520 clocks = <&scu ASPEED_CLK_APB>; 521 pinctrl-names = "default"; 522 pinctrl-0 = <&pinctrl_i2c6_default>; 523 status = "disabled"; 524 }; 525 526 i2c6: i2c-bus@1c0 { 527 #address-cells = <1>; 528 #size-cells = <0>; 529 #interrupt-cells = <1>; 530 531 reg = <0x1c0 0x40>; 532 compatible = "aspeed,ast2500-i2c-bus"; 533 bus-frequency = <100000>; 534 interrupts = <6>; 535 interrupt-parent = <&i2c_ic>; 536 clocks = <&scu ASPEED_CLK_APB>; 537 pinctrl-names = "default"; 538 pinctrl-0 = <&pinctrl_i2c7_default>; 539 status = "disabled"; 540 }; 541 542 i2c7: i2c-bus@300 { 543 #address-cells = <1>; 544 #size-cells = <0>; 545 #interrupt-cells = <1>; 546 547 reg = <0x300 0x40>; 548 compatible = "aspeed,ast2500-i2c-bus"; 549 bus-frequency = <100000>; 550 interrupts = <7>; 551 interrupt-parent = <&i2c_ic>; 552 clocks = <&scu ASPEED_CLK_APB>; 553 pinctrl-names = "default"; 554 pinctrl-0 = <&pinctrl_i2c8_default>; 555 status = "disabled"; 556 }; 557 558 i2c8: i2c-bus@340 { 559 #address-cells = <1>; 560 #size-cells = <0>; 561 #interrupt-cells = <1>; 562 563 reg = <0x340 0x40>; 564 compatible = "aspeed,ast2500-i2c-bus"; 565 bus-frequency = <100000>; 566 interrupts = <8>; 567 interrupt-parent = <&i2c_ic>; 568 clocks = <&scu ASPEED_CLK_APB>; 569 pinctrl-names = "default"; 570 pinctrl-0 = <&pinctrl_i2c9_default>; 571 status = "disabled"; 572 }; 573 574 i2c9: i2c-bus@380 { 575 #address-cells = <1>; 576 #size-cells = <0>; 577 #interrupt-cells = <1>; 578 579 reg = <0x380 0x40>; 580 compatible = "aspeed,ast2500-i2c-bus"; 581 bus-frequency = <100000>; 582 interrupts = <9>; 583 interrupt-parent = <&i2c_ic>; 584 clocks = <&scu ASPEED_CLK_APB>; 585 pinctrl-names = "default"; 586 pinctrl-0 = <&pinctrl_i2c10_default>; 587 status = "disabled"; 588 }; 589 590 i2c10: i2c-bus@3c0 { 591 #address-cells = <1>; 592 #size-cells = <0>; 593 #interrupt-cells = <1>; 594 595 reg = <0x3c0 0x40>; 596 compatible = "aspeed,ast2500-i2c-bus"; 597 bus-frequency = <100000>; 598 interrupts = <10>; 599 interrupt-parent = <&i2c_ic>; 600 clocks = <&scu ASPEED_CLK_APB>; 601 pinctrl-names = "default"; 602 pinctrl-0 = <&pinctrl_i2c11_default>; 603 status = "disabled"; 604 }; 605 606 i2c11: i2c-bus@400 { 607 #address-cells = <1>; 608 #size-cells = <0>; 609 #interrupt-cells = <1>; 610 611 reg = <0x400 0x40>; 612 compatible = "aspeed,ast2500-i2c-bus"; 613 bus-frequency = <100000>; 614 interrupts = <11>; 615 interrupt-parent = <&i2c_ic>; 616 clocks = <&scu ASPEED_CLK_APB>; 617 pinctrl-names = "default"; 618 pinctrl-0 = <&pinctrl_i2c12_default>; 619 status = "disabled"; 620 }; 621 622 i2c12: i2c-bus@440 { 623 #address-cells = <1>; 624 #size-cells = <0>; 625 #interrupt-cells = <1>; 626 627 reg = <0x440 0x40>; 628 compatible = "aspeed,ast2500-i2c-bus"; 629 bus-frequency = <100000>; 630 interrupts = <12>; 631 interrupt-parent = <&i2c_ic>; 632 clocks = <&scu ASPEED_CLK_APB>; 633 pinctrl-names = "default"; 634 pinctrl-0 = <&pinctrl_i2c13_default>; 635 status = "disabled"; 636 }; 637 638 i2c13: i2c-bus@480 { 639 #address-cells = <1>; 640 #size-cells = <0>; 641 #interrupt-cells = <1>; 642 643 reg = <0x480 0x40>; 644 compatible = "aspeed,ast2500-i2c-bus"; 645 bus-frequency = <100000>; 646 interrupts = <13>; 647 interrupt-parent = <&i2c_ic>; 648 clocks = <&scu ASPEED_CLK_APB>; 649 pinctrl-names = "default"; 650 pinctrl-0 = <&pinctrl_i2c14_default>; 651 status = "disabled"; 652 }; 653}; 654 655&pinctrl { 656 pinctrl_acpi_default: acpi_default { 657 function = "ACPI"; 658 groups = "ACPI"; 659 }; 660 661 pinctrl_adc0_default: adc0_default { 662 function = "ADC0"; 663 groups = "ADC0"; 664 }; 665 666 pinctrl_adc1_default: adc1_default { 667 function = "ADC1"; 668 groups = "ADC1"; 669 }; 670 671 pinctrl_adc10_default: adc10_default { 672 function = "ADC10"; 673 groups = "ADC10"; 674 }; 675 676 pinctrl_adc11_default: adc11_default { 677 function = "ADC11"; 678 groups = "ADC11"; 679 }; 680 681 pinctrl_adc12_default: adc12_default { 682 function = "ADC12"; 683 groups = "ADC12"; 684 }; 685 686 pinctrl_adc13_default: adc13_default { 687 function = "ADC13"; 688 groups = "ADC13"; 689 }; 690 691 pinctrl_adc14_default: adc14_default { 692 function = "ADC14"; 693 groups = "ADC14"; 694 }; 695 696 pinctrl_adc15_default: adc15_default { 697 function = "ADC15"; 698 groups = "ADC15"; 699 }; 700 701 pinctrl_adc2_default: adc2_default { 702 function = "ADC2"; 703 groups = "ADC2"; 704 }; 705 706 pinctrl_adc3_default: adc3_default { 707 function = "ADC3"; 708 groups = "ADC3"; 709 }; 710 711 pinctrl_adc4_default: adc4_default { 712 function = "ADC4"; 713 groups = "ADC4"; 714 }; 715 716 pinctrl_adc5_default: adc5_default { 717 function = "ADC5"; 718 groups = "ADC5"; 719 }; 720 721 pinctrl_adc6_default: adc6_default { 722 function = "ADC6"; 723 groups = "ADC6"; 724 }; 725 726 pinctrl_adc7_default: adc7_default { 727 function = "ADC7"; 728 groups = "ADC7"; 729 }; 730 731 pinctrl_adc8_default: adc8_default { 732 function = "ADC8"; 733 groups = "ADC8"; 734 }; 735 736 pinctrl_adc9_default: adc9_default { 737 function = "ADC9"; 738 groups = "ADC9"; 739 }; 740 741 pinctrl_bmcint_default: bmcint_default { 742 function = "BMCINT"; 743 groups = "BMCINT"; 744 }; 745 746 pinctrl_ddcclk_default: ddcclk_default { 747 function = "DDCCLK"; 748 groups = "DDCCLK"; 749 }; 750 751 pinctrl_ddcdat_default: ddcdat_default { 752 function = "DDCDAT"; 753 groups = "DDCDAT"; 754 }; 755 756 pinctrl_espi_default: espi_default { 757 function = "ESPI"; 758 groups = "ESPI"; 759 }; 760 761 pinctrl_fwspics1_default: fwspics1_default { 762 function = "FWSPICS1"; 763 groups = "FWSPICS1"; 764 }; 765 766 pinctrl_fwspics2_default: fwspics2_default { 767 function = "FWSPICS2"; 768 groups = "FWSPICS2"; 769 }; 770 771 pinctrl_gpid0_default: gpid0_default { 772 function = "GPID0"; 773 groups = "GPID0"; 774 }; 775 776 pinctrl_gpid2_default: gpid2_default { 777 function = "GPID2"; 778 groups = "GPID2"; 779 }; 780 781 pinctrl_gpid4_default: gpid4_default { 782 function = "GPID4"; 783 groups = "GPID4"; 784 }; 785 786 pinctrl_gpid6_default: gpid6_default { 787 function = "GPID6"; 788 groups = "GPID6"; 789 }; 790 791 pinctrl_gpie0_default: gpie0_default { 792 function = "GPIE0"; 793 groups = "GPIE0"; 794 }; 795 796 pinctrl_gpie2_default: gpie2_default { 797 function = "GPIE2"; 798 groups = "GPIE2"; 799 }; 800 801 pinctrl_gpie4_default: gpie4_default { 802 function = "GPIE4"; 803 groups = "GPIE4"; 804 }; 805 806 pinctrl_gpie6_default: gpie6_default { 807 function = "GPIE6"; 808 groups = "GPIE6"; 809 }; 810 811 pinctrl_i2c10_default: i2c10_default { 812 function = "I2C10"; 813 groups = "I2C10"; 814 }; 815 816 pinctrl_i2c11_default: i2c11_default { 817 function = "I2C11"; 818 groups = "I2C11"; 819 }; 820 821 pinctrl_i2c12_default: i2c12_default { 822 function = "I2C12"; 823 groups = "I2C12"; 824 }; 825 826 pinctrl_i2c13_default: i2c13_default { 827 function = "I2C13"; 828 groups = "I2C13"; 829 }; 830 831 pinctrl_i2c14_default: i2c14_default { 832 function = "I2C14"; 833 groups = "I2C14"; 834 }; 835 836 pinctrl_i2c3_default: i2c3_default { 837 function = "I2C3"; 838 groups = "I2C3"; 839 }; 840 841 pinctrl_i2c4_default: i2c4_default { 842 function = "I2C4"; 843 groups = "I2C4"; 844 }; 845 846 pinctrl_i2c5_default: i2c5_default { 847 function = "I2C5"; 848 groups = "I2C5"; 849 }; 850 851 pinctrl_i2c6_default: i2c6_default { 852 function = "I2C6"; 853 groups = "I2C6"; 854 }; 855 856 pinctrl_i2c7_default: i2c7_default { 857 function = "I2C7"; 858 groups = "I2C7"; 859 }; 860 861 pinctrl_i2c8_default: i2c8_default { 862 function = "I2C8"; 863 groups = "I2C8"; 864 }; 865 866 pinctrl_i2c9_default: i2c9_default { 867 function = "I2C9"; 868 groups = "I2C9"; 869 }; 870 871 pinctrl_lad0_default: lad0_default { 872 function = "LAD0"; 873 groups = "LAD0"; 874 }; 875 876 pinctrl_lad1_default: lad1_default { 877 function = "LAD1"; 878 groups = "LAD1"; 879 }; 880 881 pinctrl_lad2_default: lad2_default { 882 function = "LAD2"; 883 groups = "LAD2"; 884 }; 885 886 pinctrl_lad3_default: lad3_default { 887 function = "LAD3"; 888 groups = "LAD3"; 889 }; 890 891 pinctrl_lclk_default: lclk_default { 892 function = "LCLK"; 893 groups = "LCLK"; 894 }; 895 896 pinctrl_lframe_default: lframe_default { 897 function = "LFRAME"; 898 groups = "LFRAME"; 899 }; 900 901 pinctrl_lpchc_default: lpchc_default { 902 function = "LPCHC"; 903 groups = "LPCHC"; 904 }; 905 906 pinctrl_lpcpd_default: lpcpd_default { 907 function = "LPCPD"; 908 groups = "LPCPD"; 909 }; 910 911 pinctrl_lpcplus_default: lpcplus_default { 912 function = "LPCPLUS"; 913 groups = "LPCPLUS"; 914 }; 915 916 pinctrl_lpcpme_default: lpcpme_default { 917 function = "LPCPME"; 918 groups = "LPCPME"; 919 }; 920 921 pinctrl_lpcrst_default: lpcrst_default { 922 function = "LPCRST"; 923 groups = "LPCRST"; 924 }; 925 926 pinctrl_lpcsmi_default: lpcsmi_default { 927 function = "LPCSMI"; 928 groups = "LPCSMI"; 929 }; 930 931 pinctrl_lsirq_default: lsirq_default { 932 function = "LSIRQ"; 933 groups = "LSIRQ"; 934 }; 935 936 pinctrl_mac1link_default: mac1link_default { 937 function = "MAC1LINK"; 938 groups = "MAC1LINK"; 939 }; 940 941 pinctrl_mac2link_default: mac2link_default { 942 function = "MAC2LINK"; 943 groups = "MAC2LINK"; 944 }; 945 946 pinctrl_mdio1_default: mdio1_default { 947 function = "MDIO1"; 948 groups = "MDIO1"; 949 }; 950 951 pinctrl_mdio2_default: mdio2_default { 952 function = "MDIO2"; 953 groups = "MDIO2"; 954 }; 955 956 pinctrl_ncts1_default: ncts1_default { 957 function = "NCTS1"; 958 groups = "NCTS1"; 959 }; 960 961 pinctrl_ncts2_default: ncts2_default { 962 function = "NCTS2"; 963 groups = "NCTS2"; 964 }; 965 966 pinctrl_ncts3_default: ncts3_default { 967 function = "NCTS3"; 968 groups = "NCTS3"; 969 }; 970 971 pinctrl_ncts4_default: ncts4_default { 972 function = "NCTS4"; 973 groups = "NCTS4"; 974 }; 975 976 pinctrl_ndcd1_default: ndcd1_default { 977 function = "NDCD1"; 978 groups = "NDCD1"; 979 }; 980 981 pinctrl_ndcd2_default: ndcd2_default { 982 function = "NDCD2"; 983 groups = "NDCD2"; 984 }; 985 986 pinctrl_ndcd3_default: ndcd3_default { 987 function = "NDCD3"; 988 groups = "NDCD3"; 989 }; 990 991 pinctrl_ndcd4_default: ndcd4_default { 992 function = "NDCD4"; 993 groups = "NDCD4"; 994 }; 995 996 pinctrl_ndsr1_default: ndsr1_default { 997 function = "NDSR1"; 998 groups = "NDSR1"; 999 }; 1000 1001 pinctrl_ndsr2_default: ndsr2_default { 1002 function = "NDSR2"; 1003 groups = "NDSR2"; 1004 }; 1005 1006 pinctrl_ndsr3_default: ndsr3_default { 1007 function = "NDSR3"; 1008 groups = "NDSR3"; 1009 }; 1010 1011 pinctrl_ndsr4_default: ndsr4_default { 1012 function = "NDSR4"; 1013 groups = "NDSR4"; 1014 }; 1015 1016 pinctrl_ndtr1_default: ndtr1_default { 1017 function = "NDTR1"; 1018 groups = "NDTR1"; 1019 }; 1020 1021 pinctrl_ndtr2_default: ndtr2_default { 1022 function = "NDTR2"; 1023 groups = "NDTR2"; 1024 }; 1025 1026 pinctrl_ndtr3_default: ndtr3_default { 1027 function = "NDTR3"; 1028 groups = "NDTR3"; 1029 }; 1030 1031 pinctrl_ndtr4_default: ndtr4_default { 1032 function = "NDTR4"; 1033 groups = "NDTR4"; 1034 }; 1035 1036 pinctrl_nri1_default: nri1_default { 1037 function = "NRI1"; 1038 groups = "NRI1"; 1039 }; 1040 1041 pinctrl_nri2_default: nri2_default { 1042 function = "NRI2"; 1043 groups = "NRI2"; 1044 }; 1045 1046 pinctrl_nri3_default: nri3_default { 1047 function = "NRI3"; 1048 groups = "NRI3"; 1049 }; 1050 1051 pinctrl_nri4_default: nri4_default { 1052 function = "NRI4"; 1053 groups = "NRI4"; 1054 }; 1055 1056 pinctrl_nrts1_default: nrts1_default { 1057 function = "NRTS1"; 1058 groups = "NRTS1"; 1059 }; 1060 1061 pinctrl_nrts2_default: nrts2_default { 1062 function = "NRTS2"; 1063 groups = "NRTS2"; 1064 }; 1065 1066 pinctrl_nrts3_default: nrts3_default { 1067 function = "NRTS3"; 1068 groups = "NRTS3"; 1069 }; 1070 1071 pinctrl_nrts4_default: nrts4_default { 1072 function = "NRTS4"; 1073 groups = "NRTS4"; 1074 }; 1075 1076 pinctrl_oscclk_default: oscclk_default { 1077 function = "OSCCLK"; 1078 groups = "OSCCLK"; 1079 }; 1080 1081 pinctrl_pewake_default: pewake_default { 1082 function = "PEWAKE"; 1083 groups = "PEWAKE"; 1084 }; 1085 1086 pinctrl_pnor_default: pnor_default { 1087 function = "PNOR"; 1088 groups = "PNOR"; 1089 }; 1090 1091 pinctrl_pwm0_default: pwm0_default { 1092 function = "PWM0"; 1093 groups = "PWM0"; 1094 }; 1095 1096 pinctrl_pwm1_default: pwm1_default { 1097 function = "PWM1"; 1098 groups = "PWM1"; 1099 }; 1100 1101 pinctrl_pwm2_default: pwm2_default { 1102 function = "PWM2"; 1103 groups = "PWM2"; 1104 }; 1105 1106 pinctrl_pwm3_default: pwm3_default { 1107 function = "PWM3"; 1108 groups = "PWM3"; 1109 }; 1110 1111 pinctrl_pwm4_default: pwm4_default { 1112 function = "PWM4"; 1113 groups = "PWM4"; 1114 }; 1115 1116 pinctrl_pwm5_default: pwm5_default { 1117 function = "PWM5"; 1118 groups = "PWM5"; 1119 }; 1120 1121 pinctrl_pwm6_default: pwm6_default { 1122 function = "PWM6"; 1123 groups = "PWM6"; 1124 }; 1125 1126 pinctrl_pwm7_default: pwm7_default { 1127 function = "PWM7"; 1128 groups = "PWM7"; 1129 }; 1130 1131 pinctrl_rgmii1_default: rgmii1_default { 1132 function = "RGMII1"; 1133 groups = "RGMII1"; 1134 }; 1135 1136 pinctrl_rgmii2_default: rgmii2_default { 1137 function = "RGMII2"; 1138 groups = "RGMII2"; 1139 }; 1140 1141 pinctrl_rmii1_default: rmii1_default { 1142 function = "RMII1"; 1143 groups = "RMII1"; 1144 }; 1145 1146 pinctrl_rmii2_default: rmii2_default { 1147 function = "RMII2"; 1148 groups = "RMII2"; 1149 }; 1150 1151 pinctrl_rxd1_default: rxd1_default { 1152 function = "RXD1"; 1153 groups = "RXD1"; 1154 }; 1155 1156 pinctrl_rxd2_default: rxd2_default { 1157 function = "RXD2"; 1158 groups = "RXD2"; 1159 }; 1160 1161 pinctrl_rxd3_default: rxd3_default { 1162 function = "RXD3"; 1163 groups = "RXD3"; 1164 }; 1165 1166 pinctrl_rxd4_default: rxd4_default { 1167 function = "RXD4"; 1168 groups = "RXD4"; 1169 }; 1170 1171 pinctrl_salt1_default: salt1_default { 1172 function = "SALT1"; 1173 groups = "SALT1"; 1174 }; 1175 1176 pinctrl_salt10_default: salt10_default { 1177 function = "SALT10"; 1178 groups = "SALT10"; 1179 }; 1180 1181 pinctrl_salt11_default: salt11_default { 1182 function = "SALT11"; 1183 groups = "SALT11"; 1184 }; 1185 1186 pinctrl_salt12_default: salt12_default { 1187 function = "SALT12"; 1188 groups = "SALT12"; 1189 }; 1190 1191 pinctrl_salt13_default: salt13_default { 1192 function = "SALT13"; 1193 groups = "SALT13"; 1194 }; 1195 1196 pinctrl_salt14_default: salt14_default { 1197 function = "SALT14"; 1198 groups = "SALT14"; 1199 }; 1200 1201 pinctrl_salt2_default: salt2_default { 1202 function = "SALT2"; 1203 groups = "SALT2"; 1204 }; 1205 1206 pinctrl_salt3_default: salt3_default { 1207 function = "SALT3"; 1208 groups = "SALT3"; 1209 }; 1210 1211 pinctrl_salt4_default: salt4_default { 1212 function = "SALT4"; 1213 groups = "SALT4"; 1214 }; 1215 1216 pinctrl_salt5_default: salt5_default { 1217 function = "SALT5"; 1218 groups = "SALT5"; 1219 }; 1220 1221 pinctrl_salt6_default: salt6_default { 1222 function = "SALT6"; 1223 groups = "SALT6"; 1224 }; 1225 1226 pinctrl_salt7_default: salt7_default { 1227 function = "SALT7"; 1228 groups = "SALT7"; 1229 }; 1230 1231 pinctrl_salt8_default: salt8_default { 1232 function = "SALT8"; 1233 groups = "SALT8"; 1234 }; 1235 1236 pinctrl_salt9_default: salt9_default { 1237 function = "SALT9"; 1238 groups = "SALT9"; 1239 }; 1240 1241 pinctrl_scl1_default: scl1_default { 1242 function = "SCL1"; 1243 groups = "SCL1"; 1244 }; 1245 1246 pinctrl_scl2_default: scl2_default { 1247 function = "SCL2"; 1248 groups = "SCL2"; 1249 }; 1250 1251 pinctrl_sd1_default: sd1_default { 1252 function = "SD1"; 1253 groups = "SD1"; 1254 }; 1255 1256 pinctrl_sd2_default: sd2_default { 1257 function = "SD2"; 1258 groups = "SD2"; 1259 }; 1260 1261 pinctrl_sda1_default: sda1_default { 1262 function = "SDA1"; 1263 groups = "SDA1"; 1264 }; 1265 1266 pinctrl_sda2_default: sda2_default { 1267 function = "SDA2"; 1268 groups = "SDA2"; 1269 }; 1270 1271 pinctrl_sgps1_default: sgps1_default { 1272 function = "SGPS1"; 1273 groups = "SGPS1"; 1274 }; 1275 1276 pinctrl_sgps2_default: sgps2_default { 1277 function = "SGPS2"; 1278 groups = "SGPS2"; 1279 }; 1280 1281 pinctrl_sioonctrl_default: sioonctrl_default { 1282 function = "SIOONCTRL"; 1283 groups = "SIOONCTRL"; 1284 }; 1285 1286 pinctrl_siopbi_default: siopbi_default { 1287 function = "SIOPBI"; 1288 groups = "SIOPBI"; 1289 }; 1290 1291 pinctrl_siopbo_default: siopbo_default { 1292 function = "SIOPBO"; 1293 groups = "SIOPBO"; 1294 }; 1295 1296 pinctrl_siopwreq_default: siopwreq_default { 1297 function = "SIOPWREQ"; 1298 groups = "SIOPWREQ"; 1299 }; 1300 1301 pinctrl_siopwrgd_default: siopwrgd_default { 1302 function = "SIOPWRGD"; 1303 groups = "SIOPWRGD"; 1304 }; 1305 1306 pinctrl_sios3_default: sios3_default { 1307 function = "SIOS3"; 1308 groups = "SIOS3"; 1309 }; 1310 1311 pinctrl_sios5_default: sios5_default { 1312 function = "SIOS5"; 1313 groups = "SIOS5"; 1314 }; 1315 1316 pinctrl_siosci_default: siosci_default { 1317 function = "SIOSCI"; 1318 groups = "SIOSCI"; 1319 }; 1320 1321 pinctrl_spi1_default: spi1_default { 1322 function = "SPI1"; 1323 groups = "SPI1"; 1324 }; 1325 1326 pinctrl_spi1cs1_default: spi1cs1_default { 1327 function = "SPI1CS1"; 1328 groups = "SPI1CS1"; 1329 }; 1330 1331 pinctrl_spi1debug_default: spi1debug_default { 1332 function = "SPI1DEBUG"; 1333 groups = "SPI1DEBUG"; 1334 }; 1335 1336 pinctrl_spi1passthru_default: spi1passthru_default { 1337 function = "SPI1PASSTHRU"; 1338 groups = "SPI1PASSTHRU"; 1339 }; 1340 1341 pinctrl_spi2ck_default: spi2ck_default { 1342 function = "SPI2CK"; 1343 groups = "SPI2CK"; 1344 }; 1345 1346 pinctrl_spi2cs0_default: spi2cs0_default { 1347 function = "SPI2CS0"; 1348 groups = "SPI2CS0"; 1349 }; 1350 1351 pinctrl_spi2cs1_default: spi2cs1_default { 1352 function = "SPI2CS1"; 1353 groups = "SPI2CS1"; 1354 }; 1355 1356 pinctrl_spi2miso_default: spi2miso_default { 1357 function = "SPI2MISO"; 1358 groups = "SPI2MISO"; 1359 }; 1360 1361 pinctrl_spi2mosi_default: spi2mosi_default { 1362 function = "SPI2MOSI"; 1363 groups = "SPI2MOSI"; 1364 }; 1365 1366 pinctrl_timer3_default: timer3_default { 1367 function = "TIMER3"; 1368 groups = "TIMER3"; 1369 }; 1370 1371 pinctrl_timer4_default: timer4_default { 1372 function = "TIMER4"; 1373 groups = "TIMER4"; 1374 }; 1375 1376 pinctrl_timer5_default: timer5_default { 1377 function = "TIMER5"; 1378 groups = "TIMER5"; 1379 }; 1380 1381 pinctrl_timer6_default: timer6_default { 1382 function = "TIMER6"; 1383 groups = "TIMER6"; 1384 }; 1385 1386 pinctrl_timer7_default: timer7_default { 1387 function = "TIMER7"; 1388 groups = "TIMER7"; 1389 }; 1390 1391 pinctrl_timer8_default: timer8_default { 1392 function = "TIMER8"; 1393 groups = "TIMER8"; 1394 }; 1395 1396 pinctrl_txd1_default: txd1_default { 1397 function = "TXD1"; 1398 groups = "TXD1"; 1399 }; 1400 1401 pinctrl_txd2_default: txd2_default { 1402 function = "TXD2"; 1403 groups = "TXD2"; 1404 }; 1405 1406 pinctrl_txd3_default: txd3_default { 1407 function = "TXD3"; 1408 groups = "TXD3"; 1409 }; 1410 1411 pinctrl_txd4_default: txd4_default { 1412 function = "TXD4"; 1413 groups = "TXD4"; 1414 }; 1415 1416 pinctrl_uart6_default: uart6_default { 1417 function = "UART6"; 1418 groups = "UART6"; 1419 }; 1420 1421 pinctrl_usbcki_default: usbcki_default { 1422 function = "USBCKI"; 1423 groups = "USBCKI"; 1424 }; 1425 1426 pinctrl_usb2ah_default: usb2ah_default { 1427 function = "USB2AH"; 1428 groups = "USB2AH"; 1429 }; 1430 1431 pinctrl_usb11bhid_default: usb11bhid_default { 1432 function = "USB11BHID"; 1433 groups = "USB11BHID"; 1434 }; 1435 1436 pinctrl_usb2bh_default: usb2bh_default { 1437 function = "USB2BH"; 1438 groups = "USB2BH"; 1439 }; 1440 1441 pinctrl_vgabiosrom_default: vgabiosrom_default { 1442 function = "VGABIOSROM"; 1443 groups = "VGABIOSROM"; 1444 }; 1445 1446 pinctrl_vgahs_default: vgahs_default { 1447 function = "VGAHS"; 1448 groups = "VGAHS"; 1449 }; 1450 1451 pinctrl_vgavs_default: vgavs_default { 1452 function = "VGAVS"; 1453 groups = "VGAVS"; 1454 }; 1455 1456 pinctrl_vpi24_default: vpi24_default { 1457 function = "VPI24"; 1458 groups = "VPI24"; 1459 }; 1460 1461 pinctrl_vpo_default: vpo_default { 1462 function = "VPO"; 1463 groups = "VPO"; 1464 }; 1465 1466 pinctrl_wdtrst1_default: wdtrst1_default { 1467 function = "WDTRST1"; 1468 groups = "WDTRST1"; 1469 }; 1470 1471 pinctrl_wdtrst2_default: wdtrst2_default { 1472 function = "WDTRST2"; 1473 groups = "WDTRST2"; 1474 }; 1475}; 1476