1/* 2 * This device tree is copied from 3 * https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi 4 */ 5#include "skeleton.dtsi" 6 7/ { 8 model = "Aspeed BMC"; 9 compatible = "aspeed,ast2500"; 10 #address-cells = <1>; 11 #size-cells = <1>; 12 interrupt-parent = <&vic>; 13 14 aliases { 15 i2c0 = &i2c0; 16 i2c1 = &i2c1; 17 i2c2 = &i2c2; 18 i2c3 = &i2c3; 19 i2c4 = &i2c4; 20 i2c5 = &i2c5; 21 i2c6 = &i2c6; 22 i2c7 = &i2c7; 23 i2c8 = &i2c8; 24 i2c9 = &i2c9; 25 i2c10 = &i2c10; 26 i2c11 = &i2c11; 27 i2c12 = &i2c12; 28 i2c13 = &i2c13; 29 serial0 = &uart1; 30 serial1 = &uart2; 31 serial2 = &uart3; 32 serial3 = &uart4; 33 serial4 = &uart5; 34 serial5 = &vuart; 35 }; 36 37 cpus { 38 #address-cells = <1>; 39 #size-cells = <0>; 40 41 cpu@0 { 42 compatible = "arm,arm1176jzf-s"; 43 device_type = "cpu"; 44 reg = <0>; 45 }; 46 }; 47 48 memory@80000000 { 49 device_type = "memory"; 50 reg = <0x80000000 0>; 51 }; 52 53 ahb { 54 compatible = "simple-bus"; 55 #address-cells = <1>; 56 #size-cells = <1>; 57 ranges; 58 59 fmc: flash-controller@1e620000 { 60 reg = < 0x1e620000 0xc4 61 0x20000000 0x10000000 >; 62 #address-cells = <1>; 63 #size-cells = <0>; 64 compatible = "aspeed,ast2500-fmc"; 65 status = "disabled"; 66 interrupts = <19>; 67 clocks = <&scu ASPEED_CLK_AHB>; 68 flash@0 { 69 reg = < 0 >; 70 compatible = "jedec,spi-nor"; 71 status = "disabled"; 72 }; 73 flash@1 { 74 reg = < 1 >; 75 compatible = "jedec,spi-nor"; 76 status = "disabled"; 77 }; 78 flash@2 { 79 reg = < 2 >; 80 compatible = "jedec,spi-nor"; 81 status = "disabled"; 82 }; 83 }; 84 85 spi1: flash-controller@1e630000 { 86 reg = < 0x1e630000 0xc4 87 0x30000000 0x08000000 >; 88 #address-cells = <1>; 89 #size-cells = <0>; 90 compatible = "aspeed,ast2500-spi"; 91 clocks = <&scu ASPEED_CLK_AHB>; 92 status = "disabled"; 93 flash@0 { 94 reg = < 0 >; 95 compatible = "jedec,spi-nor"; 96 status = "disabled"; 97 }; 98 flash@1 { 99 reg = < 1 >; 100 compatible = "jedec,spi-nor"; 101 status = "disabled"; 102 }; 103 }; 104 105 spi2: flash-controller@1e631000 { 106 reg = < 0x1e631000 0xc4 107 0x38000000 0x08000000 >; 108 #address-cells = <1>; 109 #size-cells = <0>; 110 compatible = "aspeed,ast2500-spi"; 111 clocks = <&scu ASPEED_CLK_AHB>; 112 status = "disabled"; 113 flash@0 { 114 reg = < 0 >; 115 compatible = "jedec,spi-nor"; 116 status = "disabled"; 117 }; 118 flash@1 { 119 reg = < 1 >; 120 compatible = "jedec,spi-nor"; 121 status = "disabled"; 122 }; 123 }; 124 125 vic: interrupt-controller@1e6c0080 { 126 compatible = "aspeed,ast2400-vic"; 127 interrupt-controller; 128 #interrupt-cells = <1>; 129 valid-sources = <0xfefff7ff 0x0807ffff>; 130 reg = <0x1e6c0080 0x80>; 131 }; 132 133 mac0: ethernet@1e660000 { 134 compatible = "aspeed,ast2500-mac", "faraday,ftgmac100"; 135 reg = <0x1e660000 0x180>; 136 interrupts = <2>; 137 clocks = <&scu ASPEED_CLK_GATE_MAC1CLK>, <&scu ASPEED_CLK_D2PLL>; 138 status = "disabled"; 139 }; 140 141 mac1: ethernet@1e680000 { 142 compatible = "aspeed,ast2500-mac", "faraday,ftgmac100"; 143 reg = <0x1e680000 0x180>; 144 interrupts = <3>; 145 clocks = <&scu ASPEED_CLK_GATE_MAC2CLK>, <&scu ASPEED_CLK_D2PLL>; 146 status = "disabled"; 147 }; 148 149 ehci0: usb@1e6a1000 { 150 compatible = "aspeed,ast2500-ehci", "generic-ehci"; 151 reg = <0x1e6a1000 0x100>; 152 interrupts = <5>; 153 status = "disabled"; 154 }; 155 156 ehci1: usb@1e6a3000 { 157 compatible = "aspeed,ast2500-ehci", "generic-ehci"; 158 reg = <0x1e6a3000 0x100>; 159 interrupts = <13>; 160 status = "disabled"; 161 }; 162 163 uhci: usb@1e6b0000 { 164 compatible = "aspeed,ast2500-uhci", "generic-uhci"; 165 reg = <0x1e6b0000 0x100>; 166 interrupts = <14>; 167 #ports = <2>; 168 status = "disabled"; 169 }; 170 171 apb { 172 compatible = "simple-bus"; 173 #address-cells = <1>; 174 #size-cells = <1>; 175 ranges; 176 177 syscon: syscon@1e6e2000 { 178 compatible = "aspeed,g5-scu", "syscon", "simple-mfd"; 179 reg = <0x1e6e2000 0x1a8>; 180 #clock-cells = <1>; 181 #reset-cells = <1>; 182 183 pinctrl: pinctrl { 184 compatible = "aspeed,g5-pinctrl"; 185 aspeed,external-nodes = <&gfx &lhc>; 186 187 }; 188 }; 189 190 rng: hwrng@1e6e2078 { 191 compatible = "timeriomem_rng"; 192 reg = <0x1e6e2078 0x4>; 193 period = <1>; 194 quality = <100>; 195 }; 196 197 gfx: display@1e6e6000 { 198 compatible = "aspeed,ast2500-gfx", "syscon"; 199 reg = <0x1e6e6000 0x1000>; 200 reg-io-width = <4>; 201 }; 202 203 adc: adc@1e6e9000 { 204 compatible = "aspeed,ast2500-adc"; 205 reg = <0x1e6e9000 0xb0>; 206 #io-channel-cells = <1>; 207 status = "disabled"; 208 }; 209 210 sram@1e720000 { 211 compatible = "mmio-sram"; 212 reg = <0x1e720000 0x9000>; // 36K 213 }; 214 215 sdhci: sdhci@1e740000 { 216 #interrupt-cells = <1>; 217 compatible = "aspeed,aspeed-sdhci-irq", "simple-mfd"; 218 reg = <0x1e740000 0x1000>; 219 interrupts = <26>; 220 interrupt-controller; 221 clocks = <&scu ASPEED_CLK_GATE_SDCLK>, <&scu ASPEED_CLK_GATE_SDEXTCLK>; 222 clock-names = "ctrlclk", "extclk"; 223 #address-cells = <1>; 224 #size-cells = <1>; 225 ranges = <0x0 0x1e740000 0x1000>; 226 227 sdhci_slot0: sdhci_slot0@100 { 228 compatible = "aspeed,sdhci-ast2500"; 229 reg = <0x100 0x100>; 230 interrupts = <0>; 231 interrupt-parent = <&sdhci>; 232 sdhci,auto-cmd12; 233 clocks = <&scu ASPEED_CLK_SDIO>; 234 status = "disabled"; 235 }; 236 237 sdhci_slot1: sdhci_slot1@200 { 238 compatible = "aspeed,sdhci-ast2500"; 239 reg = <0x200 0x100>; 240 interrupts = <1>; 241 interrupt-parent = <&sdhci>; 242 sdhci,auto-cmd12; 243 clocks = <&scu ASPEED_CLK_SDIO>; 244 status = "disabled"; 245 }; 246 247 }; 248 249 gpio: gpio@1e780000 { 250 #gpio-cells = <2>; 251 gpio-controller; 252 compatible = "aspeed,ast2500-gpio"; 253 reg = <0x1e780000 0x1000>; 254 interrupts = <20>; 255 gpio-ranges = <&pinctrl 0 0 220>; 256 interrupt-controller; 257 }; 258 259 timer: timer@1e782000 { 260 /* This timer is a Faraday FTTMR010 derivative */ 261 compatible = "aspeed,ast2400-timer"; 262 reg = <0x1e782000 0x90>; 263 }; 264 265 uart1: serial@1e783000 { 266 compatible = "ns16550a"; 267 reg = <0x1e783000 0x20>; 268 reg-shift = <2>; 269 interrupts = <9>; 270 clocks = <&scu ASPEED_CLK_GATE_UART1CLK>; 271 clock-frequency = <24000000>; 272 no-loopback-test; 273 status = "disabled"; 274 }; 275 276 uart5: serial@1e784000 { 277 compatible = "ns16550a"; 278 reg = <0x1e784000 0x20>; 279 reg-shift = <2>; 280 interrupts = <10>; 281 clocks = <&scu ASPEED_CLK_GATE_UART5CLK>; 282 clock-frequency = <24000000>; 283 no-loopback-test; 284 status = "disabled"; 285 }; 286 287 wdt1: watchdog@1e785000 { 288 compatible = "aspeed,wdt"; 289 reg = <0x1e785000 0x1c>; 290 interrupts = <27>; 291 }; 292 293 wdt2: watchdog@1e785020 { 294 compatible = "aspeed,wdt"; 295 reg = <0x1e785020 0x1c>; 296 interrupts = <27>; 297 status = "disabled"; 298 }; 299 300 wdt3: watchdog@1e785040 { 301 compatible = "aspeed,wdt"; 302 reg = <0x1e785040 0x1c>; 303 status = "disabled"; 304 }; 305 306 pwm_tacho: pwm-tacho-controller@1e786000 { 307 compatible = "aspeed,ast2500-pwm-tacho"; 308 #address-cells = <1>; 309 #size-cells = <0>; 310 reg = <0x1e786000 0x1000>; 311 status = "disabled"; 312 }; 313 314 vuart: serial@1e787000 { 315 compatible = "aspeed,ast2500-vuart"; 316 reg = <0x1e787000 0x40>; 317 reg-shift = <2>; 318 interrupts = <8>; 319 no-loopback-test; 320 status = "disabled"; 321 }; 322 323 lpc: lpc@1e789000 { 324 compatible = "aspeed,ast2500-lpc", "simple-mfd"; 325 reg = <0x1e789000 0x1000>; 326 327 #address-cells = <1>; 328 #size-cells = <1>; 329 ranges = <0x0 0x1e789000 0x1000>; 330 331 lpc_bmc: lpc-bmc@0 { 332 compatible = "aspeed,ast2500-lpc-bmc"; 333 reg = <0x0 0x80>; 334 }; 335 336 lpc_host: lpc-host@80 { 337 compatible = "aspeed,ast2500-lpc-host", "simple-mfd", "syscon"; 338 reg = <0x80 0x1e0>; 339 reg-io-width = <4>; 340 341 #address-cells = <1>; 342 #size-cells = <1>; 343 ranges = <0x0 0x80 0x1e0>; 344 345 lpc_ctrl: lpc-ctrl@0 { 346 compatible = "aspeed,ast2500-lpc-ctrl"; 347 reg = <0x0 0x80>; 348 status = "disabled"; 349 }; 350 351 lpc_snoop: lpc-snoop@0 { 352 compatible = "aspeed,ast2500-lpc-snoop"; 353 reg = <0x0 0x80>; 354 interrupts = <8>; 355 status = "disabled"; 356 }; 357 358 lhc: lhc@20 { 359 compatible = "aspeed,ast2500-lhc"; 360 reg = <0x20 0x24 0x48 0x8>; 361 }; 362 363 lpc_reset: reset-controller@18 { 364 compatible = "aspeed,ast2500-lpc-reset"; 365 reg = <0x18 0x4>; 366 #reset-cells = <1>; 367 }; 368 369 ibt: ibt@c0 { 370 compatible = "aspeed,ast2500-ibt-bmc"; 371 reg = <0xc0 0x18>; 372 interrupts = <8>; 373 status = "disabled"; 374 }; 375 }; 376 }; 377 378 uart2: serial@1e78d000 { 379 compatible = "ns16550a"; 380 reg = <0x1e78d000 0x20>; 381 reg-shift = <2>; 382 interrupts = <32>; 383 clocks = <&scu ASPEED_CLK_GATE_UART2CLK>; 384 clock-frequency = <24000000>; 385 no-loopback-test; 386 status = "disabled"; 387 }; 388 389 uart3: serial@1e78e000 { 390 compatible = "ns16550a"; 391 reg = <0x1e78e000 0x20>; 392 reg-shift = <2>; 393 interrupts = <33>; 394 clocks = <&scu ASPEED_CLK_GATE_UART3CLK>; 395 clock-frequency = <24000000>; 396 no-loopback-test; 397 status = "disabled"; 398 }; 399 400 uart4: serial@1e78f000 { 401 compatible = "ns16550a"; 402 reg = <0x1e78f000 0x20>; 403 reg-shift = <2>; 404 interrupts = <34>; 405 clocks = <&scu ASPEED_CLK_GATE_UART4CLK>; 406 clock-frequency = <24000000>; 407 no-loopback-test; 408 status = "disabled"; 409 }; 410 411 i2c: i2c@1e78a000 { 412 compatible = "simple-bus"; 413 #address-cells = <1>; 414 #size-cells = <1>; 415 ranges = <0 0x1e78a000 0x1000>; 416 }; 417 }; 418 }; 419}; 420 421&i2c { 422 i2c_ic: interrupt-controller@0 { 423 #interrupt-cells = <1>; 424 compatible = "aspeed,ast2500-i2c-ic"; 425 reg = <0x0 0x40>; 426 interrupts = <12>; 427 interrupt-controller; 428 resets = <&rst ASPEED_RESET_I2C>; 429 }; 430 431 i2c0: i2c-bus@40 { 432 #address-cells = <1>; 433 #size-cells = <0>; 434 #interrupt-cells = <1>; 435 436 reg = <0x40 0x40>; 437 compatible = "aspeed,ast2500-i2c-bus"; 438 bus-frequency = <100000>; 439 interrupts = <0>; 440 interrupt-parent = <&i2c_ic>; 441 clocks = <&scu ASPEED_CLK_APB>; 442 status = "disabled"; 443 /* Does not need pinctrl properties */ 444 }; 445 446 i2c1: i2c-bus@80 { 447 #address-cells = <1>; 448 #size-cells = <0>; 449 #interrupt-cells = <1>; 450 451 reg = <0x80 0x40>; 452 compatible = "aspeed,ast2500-i2c-bus"; 453 bus-frequency = <100000>; 454 interrupts = <1>; 455 interrupt-parent = <&i2c_ic>; 456 clocks = <&scu ASPEED_CLK_APB>; 457 status = "disabled"; 458 /* Does not need pinctrl properties */ 459 }; 460 461 i2c2: i2c-bus@c0 { 462 #address-cells = <1>; 463 #size-cells = <0>; 464 #interrupt-cells = <1>; 465 466 reg = <0xc0 0x40>; 467 compatible = "aspeed,ast2500-i2c-bus"; 468 bus-frequency = <100000>; 469 interrupts = <2>; 470 interrupt-parent = <&i2c_ic>; 471 clocks = <&scu ASPEED_CLK_APB>; 472 pinctrl-names = "default"; 473 pinctrl-0 = <&pinctrl_i2c3_default>; 474 status = "disabled"; 475 }; 476 477 i2c3: i2c-bus@100 { 478 #address-cells = <1>; 479 #size-cells = <0>; 480 #interrupt-cells = <1>; 481 482 reg = <0x100 0x40>; 483 compatible = "aspeed,ast2500-i2c-bus"; 484 bus-frequency = <100000>; 485 interrupts = <3>; 486 interrupt-parent = <&i2c_ic>; 487 clocks = <&scu ASPEED_CLK_APB>; 488 pinctrl-names = "default"; 489 pinctrl-0 = <&pinctrl_i2c4_default>; 490 status = "disabled"; 491 }; 492 493 i2c4: i2c-bus@140 { 494 #address-cells = <1>; 495 #size-cells = <0>; 496 #interrupt-cells = <1>; 497 498 reg = <0x140 0x40>; 499 compatible = "aspeed,ast2500-i2c-bus"; 500 bus-frequency = <100000>; 501 interrupts = <4>; 502 interrupt-parent = <&i2c_ic>; 503 clocks = <&scu ASPEED_CLK_APB>; 504 pinctrl-names = "default"; 505 pinctrl-0 = <&pinctrl_i2c5_default>; 506 status = "disabled"; 507 }; 508 509 i2c5: i2c-bus@180 { 510 #address-cells = <1>; 511 #size-cells = <0>; 512 #interrupt-cells = <1>; 513 514 reg = <0x180 0x40>; 515 compatible = "aspeed,ast2500-i2c-bus"; 516 bus-frequency = <100000>; 517 interrupts = <5>; 518 interrupt-parent = <&i2c_ic>; 519 clocks = <&scu ASPEED_CLK_APB>; 520 pinctrl-names = "default"; 521 pinctrl-0 = <&pinctrl_i2c6_default>; 522 status = "disabled"; 523 }; 524 525 i2c6: i2c-bus@1c0 { 526 #address-cells = <1>; 527 #size-cells = <0>; 528 #interrupt-cells = <1>; 529 530 reg = <0x1c0 0x40>; 531 compatible = "aspeed,ast2500-i2c-bus"; 532 bus-frequency = <100000>; 533 interrupts = <6>; 534 interrupt-parent = <&i2c_ic>; 535 clocks = <&scu ASPEED_CLK_APB>; 536 pinctrl-names = "default"; 537 pinctrl-0 = <&pinctrl_i2c7_default>; 538 status = "disabled"; 539 }; 540 541 i2c7: i2c-bus@300 { 542 #address-cells = <1>; 543 #size-cells = <0>; 544 #interrupt-cells = <1>; 545 546 reg = <0x300 0x40>; 547 compatible = "aspeed,ast2500-i2c-bus"; 548 bus-frequency = <100000>; 549 interrupts = <7>; 550 interrupt-parent = <&i2c_ic>; 551 clocks = <&scu ASPEED_CLK_APB>; 552 pinctrl-names = "default"; 553 pinctrl-0 = <&pinctrl_i2c8_default>; 554 status = "disabled"; 555 }; 556 557 i2c8: i2c-bus@340 { 558 #address-cells = <1>; 559 #size-cells = <0>; 560 #interrupt-cells = <1>; 561 562 reg = <0x340 0x40>; 563 compatible = "aspeed,ast2500-i2c-bus"; 564 bus-frequency = <100000>; 565 interrupts = <8>; 566 interrupt-parent = <&i2c_ic>; 567 clocks = <&scu ASPEED_CLK_APB>; 568 pinctrl-names = "default"; 569 pinctrl-0 = <&pinctrl_i2c9_default>; 570 status = "disabled"; 571 }; 572 573 i2c9: i2c-bus@380 { 574 #address-cells = <1>; 575 #size-cells = <0>; 576 #interrupt-cells = <1>; 577 578 reg = <0x380 0x40>; 579 compatible = "aspeed,ast2500-i2c-bus"; 580 bus-frequency = <100000>; 581 interrupts = <9>; 582 interrupt-parent = <&i2c_ic>; 583 clocks = <&scu ASPEED_CLK_APB>; 584 pinctrl-names = "default"; 585 pinctrl-0 = <&pinctrl_i2c10_default>; 586 status = "disabled"; 587 }; 588 589 i2c10: i2c-bus@3c0 { 590 #address-cells = <1>; 591 #size-cells = <0>; 592 #interrupt-cells = <1>; 593 594 reg = <0x3c0 0x40>; 595 compatible = "aspeed,ast2500-i2c-bus"; 596 bus-frequency = <100000>; 597 interrupts = <10>; 598 interrupt-parent = <&i2c_ic>; 599 clocks = <&scu ASPEED_CLK_APB>; 600 pinctrl-names = "default"; 601 pinctrl-0 = <&pinctrl_i2c11_default>; 602 status = "disabled"; 603 }; 604 605 i2c11: i2c-bus@400 { 606 #address-cells = <1>; 607 #size-cells = <0>; 608 #interrupt-cells = <1>; 609 610 reg = <0x400 0x40>; 611 compatible = "aspeed,ast2500-i2c-bus"; 612 bus-frequency = <100000>; 613 interrupts = <11>; 614 interrupt-parent = <&i2c_ic>; 615 clocks = <&scu ASPEED_CLK_APB>; 616 pinctrl-names = "default"; 617 pinctrl-0 = <&pinctrl_i2c12_default>; 618 status = "disabled"; 619 }; 620 621 i2c12: i2c-bus@440 { 622 #address-cells = <1>; 623 #size-cells = <0>; 624 #interrupt-cells = <1>; 625 626 reg = <0x440 0x40>; 627 compatible = "aspeed,ast2500-i2c-bus"; 628 bus-frequency = <100000>; 629 interrupts = <12>; 630 interrupt-parent = <&i2c_ic>; 631 clocks = <&scu ASPEED_CLK_APB>; 632 pinctrl-names = "default"; 633 pinctrl-0 = <&pinctrl_i2c13_default>; 634 status = "disabled"; 635 }; 636 637 i2c13: i2c-bus@480 { 638 #address-cells = <1>; 639 #size-cells = <0>; 640 #interrupt-cells = <1>; 641 642 reg = <0x480 0x40>; 643 compatible = "aspeed,ast2500-i2c-bus"; 644 bus-frequency = <100000>; 645 interrupts = <13>; 646 interrupt-parent = <&i2c_ic>; 647 clocks = <&scu ASPEED_CLK_APB>; 648 pinctrl-names = "default"; 649 pinctrl-0 = <&pinctrl_i2c14_default>; 650 status = "disabled"; 651 }; 652}; 653 654&pinctrl { 655 pinctrl_acpi_default: acpi_default { 656 function = "ACPI"; 657 groups = "ACPI"; 658 }; 659 660 pinctrl_adc0_default: adc0_default { 661 function = "ADC0"; 662 groups = "ADC0"; 663 }; 664 665 pinctrl_adc1_default: adc1_default { 666 function = "ADC1"; 667 groups = "ADC1"; 668 }; 669 670 pinctrl_adc10_default: adc10_default { 671 function = "ADC10"; 672 groups = "ADC10"; 673 }; 674 675 pinctrl_adc11_default: adc11_default { 676 function = "ADC11"; 677 groups = "ADC11"; 678 }; 679 680 pinctrl_adc12_default: adc12_default { 681 function = "ADC12"; 682 groups = "ADC12"; 683 }; 684 685 pinctrl_adc13_default: adc13_default { 686 function = "ADC13"; 687 groups = "ADC13"; 688 }; 689 690 pinctrl_adc14_default: adc14_default { 691 function = "ADC14"; 692 groups = "ADC14"; 693 }; 694 695 pinctrl_adc15_default: adc15_default { 696 function = "ADC15"; 697 groups = "ADC15"; 698 }; 699 700 pinctrl_adc2_default: adc2_default { 701 function = "ADC2"; 702 groups = "ADC2"; 703 }; 704 705 pinctrl_adc3_default: adc3_default { 706 function = "ADC3"; 707 groups = "ADC3"; 708 }; 709 710 pinctrl_adc4_default: adc4_default { 711 function = "ADC4"; 712 groups = "ADC4"; 713 }; 714 715 pinctrl_adc5_default: adc5_default { 716 function = "ADC5"; 717 groups = "ADC5"; 718 }; 719 720 pinctrl_adc6_default: adc6_default { 721 function = "ADC6"; 722 groups = "ADC6"; 723 }; 724 725 pinctrl_adc7_default: adc7_default { 726 function = "ADC7"; 727 groups = "ADC7"; 728 }; 729 730 pinctrl_adc8_default: adc8_default { 731 function = "ADC8"; 732 groups = "ADC8"; 733 }; 734 735 pinctrl_adc9_default: adc9_default { 736 function = "ADC9"; 737 groups = "ADC9"; 738 }; 739 740 pinctrl_bmcint_default: bmcint_default { 741 function = "BMCINT"; 742 groups = "BMCINT"; 743 }; 744 745 pinctrl_ddcclk_default: ddcclk_default { 746 function = "DDCCLK"; 747 groups = "DDCCLK"; 748 }; 749 750 pinctrl_ddcdat_default: ddcdat_default { 751 function = "DDCDAT"; 752 groups = "DDCDAT"; 753 }; 754 755 pinctrl_espi_default: espi_default { 756 function = "ESPI"; 757 groups = "ESPI"; 758 }; 759 760 pinctrl_fwspics1_default: fwspics1_default { 761 function = "FWSPICS1"; 762 groups = "FWSPICS1"; 763 }; 764 765 pinctrl_fwspics2_default: fwspics2_default { 766 function = "FWSPICS2"; 767 groups = "FWSPICS2"; 768 }; 769 770 pinctrl_gpid0_default: gpid0_default { 771 function = "GPID0"; 772 groups = "GPID0"; 773 }; 774 775 pinctrl_gpid2_default: gpid2_default { 776 function = "GPID2"; 777 groups = "GPID2"; 778 }; 779 780 pinctrl_gpid4_default: gpid4_default { 781 function = "GPID4"; 782 groups = "GPID4"; 783 }; 784 785 pinctrl_gpid6_default: gpid6_default { 786 function = "GPID6"; 787 groups = "GPID6"; 788 }; 789 790 pinctrl_gpie0_default: gpie0_default { 791 function = "GPIE0"; 792 groups = "GPIE0"; 793 }; 794 795 pinctrl_gpie2_default: gpie2_default { 796 function = "GPIE2"; 797 groups = "GPIE2"; 798 }; 799 800 pinctrl_gpie4_default: gpie4_default { 801 function = "GPIE4"; 802 groups = "GPIE4"; 803 }; 804 805 pinctrl_gpie6_default: gpie6_default { 806 function = "GPIE6"; 807 groups = "GPIE6"; 808 }; 809 810 pinctrl_i2c10_default: i2c10_default { 811 function = "I2C10"; 812 groups = "I2C10"; 813 }; 814 815 pinctrl_i2c11_default: i2c11_default { 816 function = "I2C11"; 817 groups = "I2C11"; 818 }; 819 820 pinctrl_i2c12_default: i2c12_default { 821 function = "I2C12"; 822 groups = "I2C12"; 823 }; 824 825 pinctrl_i2c13_default: i2c13_default { 826 function = "I2C13"; 827 groups = "I2C13"; 828 }; 829 830 pinctrl_i2c14_default: i2c14_default { 831 function = "I2C14"; 832 groups = "I2C14"; 833 }; 834 835 pinctrl_i2c3_default: i2c3_default { 836 function = "I2C3"; 837 groups = "I2C3"; 838 }; 839 840 pinctrl_i2c4_default: i2c4_default { 841 function = "I2C4"; 842 groups = "I2C4"; 843 }; 844 845 pinctrl_i2c5_default: i2c5_default { 846 function = "I2C5"; 847 groups = "I2C5"; 848 }; 849 850 pinctrl_i2c6_default: i2c6_default { 851 function = "I2C6"; 852 groups = "I2C6"; 853 }; 854 855 pinctrl_i2c7_default: i2c7_default { 856 function = "I2C7"; 857 groups = "I2C7"; 858 }; 859 860 pinctrl_i2c8_default: i2c8_default { 861 function = "I2C8"; 862 groups = "I2C8"; 863 }; 864 865 pinctrl_i2c9_default: i2c9_default { 866 function = "I2C9"; 867 groups = "I2C9"; 868 }; 869 870 pinctrl_lad0_default: lad0_default { 871 function = "LAD0"; 872 groups = "LAD0"; 873 }; 874 875 pinctrl_lad1_default: lad1_default { 876 function = "LAD1"; 877 groups = "LAD1"; 878 }; 879 880 pinctrl_lad2_default: lad2_default { 881 function = "LAD2"; 882 groups = "LAD2"; 883 }; 884 885 pinctrl_lad3_default: lad3_default { 886 function = "LAD3"; 887 groups = "LAD3"; 888 }; 889 890 pinctrl_lclk_default: lclk_default { 891 function = "LCLK"; 892 groups = "LCLK"; 893 }; 894 895 pinctrl_lframe_default: lframe_default { 896 function = "LFRAME"; 897 groups = "LFRAME"; 898 }; 899 900 pinctrl_lpchc_default: lpchc_default { 901 function = "LPCHC"; 902 groups = "LPCHC"; 903 }; 904 905 pinctrl_lpcpd_default: lpcpd_default { 906 function = "LPCPD"; 907 groups = "LPCPD"; 908 }; 909 910 pinctrl_lpcplus_default: lpcplus_default { 911 function = "LPCPLUS"; 912 groups = "LPCPLUS"; 913 }; 914 915 pinctrl_lpcpme_default: lpcpme_default { 916 function = "LPCPME"; 917 groups = "LPCPME"; 918 }; 919 920 pinctrl_lpcrst_default: lpcrst_default { 921 function = "LPCRST"; 922 groups = "LPCRST"; 923 }; 924 925 pinctrl_lpcsmi_default: lpcsmi_default { 926 function = "LPCSMI"; 927 groups = "LPCSMI"; 928 }; 929 930 pinctrl_lsirq_default: lsirq_default { 931 function = "LSIRQ"; 932 groups = "LSIRQ"; 933 }; 934 935 pinctrl_mac1link_default: mac1link_default { 936 function = "MAC1LINK"; 937 groups = "MAC1LINK"; 938 }; 939 940 pinctrl_mac2link_default: mac2link_default { 941 function = "MAC2LINK"; 942 groups = "MAC2LINK"; 943 }; 944 945 pinctrl_mdio1_default: mdio1_default { 946 function = "MDIO1"; 947 groups = "MDIO1"; 948 }; 949 950 pinctrl_mdio2_default: mdio2_default { 951 function = "MDIO2"; 952 groups = "MDIO2"; 953 }; 954 955 pinctrl_ncts1_default: ncts1_default { 956 function = "NCTS1"; 957 groups = "NCTS1"; 958 }; 959 960 pinctrl_ncts2_default: ncts2_default { 961 function = "NCTS2"; 962 groups = "NCTS2"; 963 }; 964 965 pinctrl_ncts3_default: ncts3_default { 966 function = "NCTS3"; 967 groups = "NCTS3"; 968 }; 969 970 pinctrl_ncts4_default: ncts4_default { 971 function = "NCTS4"; 972 groups = "NCTS4"; 973 }; 974 975 pinctrl_ndcd1_default: ndcd1_default { 976 function = "NDCD1"; 977 groups = "NDCD1"; 978 }; 979 980 pinctrl_ndcd2_default: ndcd2_default { 981 function = "NDCD2"; 982 groups = "NDCD2"; 983 }; 984 985 pinctrl_ndcd3_default: ndcd3_default { 986 function = "NDCD3"; 987 groups = "NDCD3"; 988 }; 989 990 pinctrl_ndcd4_default: ndcd4_default { 991 function = "NDCD4"; 992 groups = "NDCD4"; 993 }; 994 995 pinctrl_ndsr1_default: ndsr1_default { 996 function = "NDSR1"; 997 groups = "NDSR1"; 998 }; 999 1000 pinctrl_ndsr2_default: ndsr2_default { 1001 function = "NDSR2"; 1002 groups = "NDSR2"; 1003 }; 1004 1005 pinctrl_ndsr3_default: ndsr3_default { 1006 function = "NDSR3"; 1007 groups = "NDSR3"; 1008 }; 1009 1010 pinctrl_ndsr4_default: ndsr4_default { 1011 function = "NDSR4"; 1012 groups = "NDSR4"; 1013 }; 1014 1015 pinctrl_ndtr1_default: ndtr1_default { 1016 function = "NDTR1"; 1017 groups = "NDTR1"; 1018 }; 1019 1020 pinctrl_ndtr2_default: ndtr2_default { 1021 function = "NDTR2"; 1022 groups = "NDTR2"; 1023 }; 1024 1025 pinctrl_ndtr3_default: ndtr3_default { 1026 function = "NDTR3"; 1027 groups = "NDTR3"; 1028 }; 1029 1030 pinctrl_ndtr4_default: ndtr4_default { 1031 function = "NDTR4"; 1032 groups = "NDTR4"; 1033 }; 1034 1035 pinctrl_nri1_default: nri1_default { 1036 function = "NRI1"; 1037 groups = "NRI1"; 1038 }; 1039 1040 pinctrl_nri2_default: nri2_default { 1041 function = "NRI2"; 1042 groups = "NRI2"; 1043 }; 1044 1045 pinctrl_nri3_default: nri3_default { 1046 function = "NRI3"; 1047 groups = "NRI3"; 1048 }; 1049 1050 pinctrl_nri4_default: nri4_default { 1051 function = "NRI4"; 1052 groups = "NRI4"; 1053 }; 1054 1055 pinctrl_nrts1_default: nrts1_default { 1056 function = "NRTS1"; 1057 groups = "NRTS1"; 1058 }; 1059 1060 pinctrl_nrts2_default: nrts2_default { 1061 function = "NRTS2"; 1062 groups = "NRTS2"; 1063 }; 1064 1065 pinctrl_nrts3_default: nrts3_default { 1066 function = "NRTS3"; 1067 groups = "NRTS3"; 1068 }; 1069 1070 pinctrl_nrts4_default: nrts4_default { 1071 function = "NRTS4"; 1072 groups = "NRTS4"; 1073 }; 1074 1075 pinctrl_oscclk_default: oscclk_default { 1076 function = "OSCCLK"; 1077 groups = "OSCCLK"; 1078 }; 1079 1080 pinctrl_pewake_default: pewake_default { 1081 function = "PEWAKE"; 1082 groups = "PEWAKE"; 1083 }; 1084 1085 pinctrl_pnor_default: pnor_default { 1086 function = "PNOR"; 1087 groups = "PNOR"; 1088 }; 1089 1090 pinctrl_pwm0_default: pwm0_default { 1091 function = "PWM0"; 1092 groups = "PWM0"; 1093 }; 1094 1095 pinctrl_pwm1_default: pwm1_default { 1096 function = "PWM1"; 1097 groups = "PWM1"; 1098 }; 1099 1100 pinctrl_pwm2_default: pwm2_default { 1101 function = "PWM2"; 1102 groups = "PWM2"; 1103 }; 1104 1105 pinctrl_pwm3_default: pwm3_default { 1106 function = "PWM3"; 1107 groups = "PWM3"; 1108 }; 1109 1110 pinctrl_pwm4_default: pwm4_default { 1111 function = "PWM4"; 1112 groups = "PWM4"; 1113 }; 1114 1115 pinctrl_pwm5_default: pwm5_default { 1116 function = "PWM5"; 1117 groups = "PWM5"; 1118 }; 1119 1120 pinctrl_pwm6_default: pwm6_default { 1121 function = "PWM6"; 1122 groups = "PWM6"; 1123 }; 1124 1125 pinctrl_pwm7_default: pwm7_default { 1126 function = "PWM7"; 1127 groups = "PWM7"; 1128 }; 1129 1130 pinctrl_rgmii1_default: rgmii1_default { 1131 function = "RGMII1"; 1132 groups = "RGMII1"; 1133 }; 1134 1135 pinctrl_rgmii2_default: rgmii2_default { 1136 function = "RGMII2"; 1137 groups = "RGMII2"; 1138 }; 1139 1140 pinctrl_rmii1_default: rmii1_default { 1141 function = "RMII1"; 1142 groups = "RMII1"; 1143 }; 1144 1145 pinctrl_rmii2_default: rmii2_default { 1146 function = "RMII2"; 1147 groups = "RMII2"; 1148 }; 1149 1150 pinctrl_rxd1_default: rxd1_default { 1151 function = "RXD1"; 1152 groups = "RXD1"; 1153 }; 1154 1155 pinctrl_rxd2_default: rxd2_default { 1156 function = "RXD2"; 1157 groups = "RXD2"; 1158 }; 1159 1160 pinctrl_rxd3_default: rxd3_default { 1161 function = "RXD3"; 1162 groups = "RXD3"; 1163 }; 1164 1165 pinctrl_rxd4_default: rxd4_default { 1166 function = "RXD4"; 1167 groups = "RXD4"; 1168 }; 1169 1170 pinctrl_salt1_default: salt1_default { 1171 function = "SALT1"; 1172 groups = "SALT1"; 1173 }; 1174 1175 pinctrl_salt10_default: salt10_default { 1176 function = "SALT10"; 1177 groups = "SALT10"; 1178 }; 1179 1180 pinctrl_salt11_default: salt11_default { 1181 function = "SALT11"; 1182 groups = "SALT11"; 1183 }; 1184 1185 pinctrl_salt12_default: salt12_default { 1186 function = "SALT12"; 1187 groups = "SALT12"; 1188 }; 1189 1190 pinctrl_salt13_default: salt13_default { 1191 function = "SALT13"; 1192 groups = "SALT13"; 1193 }; 1194 1195 pinctrl_salt14_default: salt14_default { 1196 function = "SALT14"; 1197 groups = "SALT14"; 1198 }; 1199 1200 pinctrl_salt2_default: salt2_default { 1201 function = "SALT2"; 1202 groups = "SALT2"; 1203 }; 1204 1205 pinctrl_salt3_default: salt3_default { 1206 function = "SALT3"; 1207 groups = "SALT3"; 1208 }; 1209 1210 pinctrl_salt4_default: salt4_default { 1211 function = "SALT4"; 1212 groups = "SALT4"; 1213 }; 1214 1215 pinctrl_salt5_default: salt5_default { 1216 function = "SALT5"; 1217 groups = "SALT5"; 1218 }; 1219 1220 pinctrl_salt6_default: salt6_default { 1221 function = "SALT6"; 1222 groups = "SALT6"; 1223 }; 1224 1225 pinctrl_salt7_default: salt7_default { 1226 function = "SALT7"; 1227 groups = "SALT7"; 1228 }; 1229 1230 pinctrl_salt8_default: salt8_default { 1231 function = "SALT8"; 1232 groups = "SALT8"; 1233 }; 1234 1235 pinctrl_salt9_default: salt9_default { 1236 function = "SALT9"; 1237 groups = "SALT9"; 1238 }; 1239 1240 pinctrl_scl1_default: scl1_default { 1241 function = "SCL1"; 1242 groups = "SCL1"; 1243 }; 1244 1245 pinctrl_scl2_default: scl2_default { 1246 function = "SCL2"; 1247 groups = "SCL2"; 1248 }; 1249 1250 pinctrl_sd1_default: sd1_default { 1251 function = "SD1"; 1252 groups = "SD1"; 1253 }; 1254 1255 pinctrl_sd2_default: sd2_default { 1256 function = "SD2"; 1257 groups = "SD2"; 1258 }; 1259 1260 pinctrl_sda1_default: sda1_default { 1261 function = "SDA1"; 1262 groups = "SDA1"; 1263 }; 1264 1265 pinctrl_sda2_default: sda2_default { 1266 function = "SDA2"; 1267 groups = "SDA2"; 1268 }; 1269 1270 pinctrl_sgps1_default: sgps1_default { 1271 function = "SGPS1"; 1272 groups = "SGPS1"; 1273 }; 1274 1275 pinctrl_sgps2_default: sgps2_default { 1276 function = "SGPS2"; 1277 groups = "SGPS2"; 1278 }; 1279 1280 pinctrl_sioonctrl_default: sioonctrl_default { 1281 function = "SIOONCTRL"; 1282 groups = "SIOONCTRL"; 1283 }; 1284 1285 pinctrl_siopbi_default: siopbi_default { 1286 function = "SIOPBI"; 1287 groups = "SIOPBI"; 1288 }; 1289 1290 pinctrl_siopbo_default: siopbo_default { 1291 function = "SIOPBO"; 1292 groups = "SIOPBO"; 1293 }; 1294 1295 pinctrl_siopwreq_default: siopwreq_default { 1296 function = "SIOPWREQ"; 1297 groups = "SIOPWREQ"; 1298 }; 1299 1300 pinctrl_siopwrgd_default: siopwrgd_default { 1301 function = "SIOPWRGD"; 1302 groups = "SIOPWRGD"; 1303 }; 1304 1305 pinctrl_sios3_default: sios3_default { 1306 function = "SIOS3"; 1307 groups = "SIOS3"; 1308 }; 1309 1310 pinctrl_sios5_default: sios5_default { 1311 function = "SIOS5"; 1312 groups = "SIOS5"; 1313 }; 1314 1315 pinctrl_siosci_default: siosci_default { 1316 function = "SIOSCI"; 1317 groups = "SIOSCI"; 1318 }; 1319 1320 pinctrl_spi1_default: spi1_default { 1321 function = "SPI1"; 1322 groups = "SPI1"; 1323 }; 1324 1325 pinctrl_spi1cs1_default: spi1cs1_default { 1326 function = "SPI1CS1"; 1327 groups = "SPI1CS1"; 1328 }; 1329 1330 pinctrl_spi1debug_default: spi1debug_default { 1331 function = "SPI1DEBUG"; 1332 groups = "SPI1DEBUG"; 1333 }; 1334 1335 pinctrl_spi1passthru_default: spi1passthru_default { 1336 function = "SPI1PASSTHRU"; 1337 groups = "SPI1PASSTHRU"; 1338 }; 1339 1340 pinctrl_spi2ck_default: spi2ck_default { 1341 function = "SPI2CK"; 1342 groups = "SPI2CK"; 1343 }; 1344 1345 pinctrl_spi2cs0_default: spi2cs0_default { 1346 function = "SPI2CS0"; 1347 groups = "SPI2CS0"; 1348 }; 1349 1350 pinctrl_spi2cs1_default: spi2cs1_default { 1351 function = "SPI2CS1"; 1352 groups = "SPI2CS1"; 1353 }; 1354 1355 pinctrl_spi2miso_default: spi2miso_default { 1356 function = "SPI2MISO"; 1357 groups = "SPI2MISO"; 1358 }; 1359 1360 pinctrl_spi2mosi_default: spi2mosi_default { 1361 function = "SPI2MOSI"; 1362 groups = "SPI2MOSI"; 1363 }; 1364 1365 pinctrl_timer3_default: timer3_default { 1366 function = "TIMER3"; 1367 groups = "TIMER3"; 1368 }; 1369 1370 pinctrl_timer4_default: timer4_default { 1371 function = "TIMER4"; 1372 groups = "TIMER4"; 1373 }; 1374 1375 pinctrl_timer5_default: timer5_default { 1376 function = "TIMER5"; 1377 groups = "TIMER5"; 1378 }; 1379 1380 pinctrl_timer6_default: timer6_default { 1381 function = "TIMER6"; 1382 groups = "TIMER6"; 1383 }; 1384 1385 pinctrl_timer7_default: timer7_default { 1386 function = "TIMER7"; 1387 groups = "TIMER7"; 1388 }; 1389 1390 pinctrl_timer8_default: timer8_default { 1391 function = "TIMER8"; 1392 groups = "TIMER8"; 1393 }; 1394 1395 pinctrl_txd1_default: txd1_default { 1396 function = "TXD1"; 1397 groups = "TXD1"; 1398 }; 1399 1400 pinctrl_txd2_default: txd2_default { 1401 function = "TXD2"; 1402 groups = "TXD2"; 1403 }; 1404 1405 pinctrl_txd3_default: txd3_default { 1406 function = "TXD3"; 1407 groups = "TXD3"; 1408 }; 1409 1410 pinctrl_txd4_default: txd4_default { 1411 function = "TXD4"; 1412 groups = "TXD4"; 1413 }; 1414 1415 pinctrl_uart6_default: uart6_default { 1416 function = "UART6"; 1417 groups = "UART6"; 1418 }; 1419 1420 pinctrl_usbcki_default: usbcki_default { 1421 function = "USBCKI"; 1422 groups = "USBCKI"; 1423 }; 1424 1425 pinctrl_usb2ah_default: usb2ah_default { 1426 function = "USB2AH"; 1427 groups = "USB2AH"; 1428 }; 1429 1430 pinctrl_usb11bhid_default: usb11bhid_default { 1431 function = "USB11BHID"; 1432 groups = "USB11BHID"; 1433 }; 1434 1435 pinctrl_usb2bh_default: usb2bh_default { 1436 function = "USB2BH"; 1437 groups = "USB2BH"; 1438 }; 1439 1440 pinctrl_vgabiosrom_default: vgabiosrom_default { 1441 function = "VGABIOSROM"; 1442 groups = "VGABIOSROM"; 1443 }; 1444 1445 pinctrl_vgahs_default: vgahs_default { 1446 function = "VGAHS"; 1447 groups = "VGAHS"; 1448 }; 1449 1450 pinctrl_vgavs_default: vgavs_default { 1451 function = "VGAVS"; 1452 groups = "VGAVS"; 1453 }; 1454 1455 pinctrl_vpi24_default: vpi24_default { 1456 function = "VPI24"; 1457 groups = "VPI24"; 1458 }; 1459 1460 pinctrl_vpo_default: vpo_default { 1461 function = "VPO"; 1462 groups = "VPO"; 1463 }; 1464 1465 pinctrl_wdtrst1_default: wdtrst1_default { 1466 function = "WDTRST1"; 1467 groups = "WDTRST1"; 1468 }; 1469 1470 pinctrl_wdtrst2_default: wdtrst2_default { 1471 function = "WDTRST2"; 1472 groups = "WDTRST2"; 1473 }; 1474}; 1475