1/* 2 * This device tree is copied from 3 * https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi 4 */ 5#include "skeleton.dtsi" 6 7/ { 8 model = "Aspeed BMC"; 9 compatible = "aspeed,ast2500"; 10 #address-cells = <1>; 11 #size-cells = <1>; 12 interrupt-parent = <&vic>; 13 14 aliases { 15 i2c0 = &i2c0; 16 i2c1 = &i2c1; 17 i2c2 = &i2c2; 18 i2c3 = &i2c3; 19 i2c4 = &i2c4; 20 i2c5 = &i2c5; 21 i2c6 = &i2c6; 22 i2c7 = &i2c7; 23 i2c8 = &i2c8; 24 i2c9 = &i2c9; 25 i2c10 = &i2c10; 26 i2c11 = &i2c11; 27 i2c12 = &i2c12; 28 i2c13 = &i2c13; 29 serial0 = &uart1; 30 serial1 = &uart2; 31 serial2 = &uart3; 32 serial3 = &uart4; 33 serial4 = &uart5; 34 serial5 = &vuart; 35 }; 36 37 cpus { 38 #address-cells = <1>; 39 #size-cells = <0>; 40 41 cpu@0 { 42 compatible = "arm,arm1176jzf-s"; 43 device_type = "cpu"; 44 reg = <0>; 45 }; 46 }; 47 48 memory@80000000 { 49 device_type = "memory"; 50 reg = <0x80000000 0>; 51 }; 52 53 ahb { 54 compatible = "simple-bus"; 55 #address-cells = <1>; 56 #size-cells = <1>; 57 ranges; 58 59 fmc: flash-controller@1e620000 { 60 reg = < 0x1e620000 0xc4 61 0x20000000 0x10000000 >; 62 #address-cells = <1>; 63 #size-cells = <0>; 64 compatible = "aspeed,ast2500-fmc"; 65 status = "disabled"; 66 interrupts = <19>; 67 clocks = <&scu ASPEED_CLK_AHB>; 68 flash@0 { 69 reg = < 0 >; 70 compatible = "jedec,spi-nor"; 71 status = "disabled"; 72 }; 73 flash@1 { 74 reg = < 1 >; 75 compatible = "jedec,spi-nor"; 76 status = "disabled"; 77 }; 78 flash@2 { 79 reg = < 2 >; 80 compatible = "jedec,spi-nor"; 81 status = "disabled"; 82 }; 83 }; 84 85 spi1: flash-controller@1e630000 { 86 reg = < 0x1e630000 0xc4 87 0x30000000 0x08000000 >; 88 #address-cells = <1>; 89 #size-cells = <0>; 90 compatible = "aspeed,ast2500-spi"; 91 clocks = <&scu ASPEED_CLK_AHB>; 92 status = "disabled"; 93 flash@0 { 94 reg = < 0 >; 95 compatible = "jedec,spi-nor"; 96 status = "disabled"; 97 }; 98 flash@1 { 99 reg = < 1 >; 100 compatible = "jedec,spi-nor"; 101 status = "disabled"; 102 }; 103 }; 104 105 spi2: flash-controller@1e631000 { 106 reg = < 0x1e631000 0xc4 107 0x38000000 0x08000000 >; 108 #address-cells = <1>; 109 #size-cells = <0>; 110 compatible = "aspeed,ast2500-spi"; 111 clocks = <&scu ASPEED_CLK_AHB>; 112 status = "disabled"; 113 flash@0 { 114 reg = < 0 >; 115 compatible = "jedec,spi-nor"; 116 status = "disabled"; 117 }; 118 flash@1 { 119 reg = < 1 >; 120 compatible = "jedec,spi-nor"; 121 status = "disabled"; 122 }; 123 }; 124 125 vic: interrupt-controller@1e6c0080 { 126 compatible = "aspeed,ast2400-vic"; 127 interrupt-controller; 128 #interrupt-cells = <1>; 129 valid-sources = <0xfefff7ff 0x0807ffff>; 130 reg = <0x1e6c0080 0x80>; 131 }; 132 133 mac0: ethernet@1e660000 { 134 compatible = "aspeed,ast2500-mac", "faraday,ftgmac100"; 135 reg = <0x1e660000 0x180>; 136 interrupts = <2>; 137 clocks = <&scu ASPEED_CLK_GATE_MAC1CLK>, <&scu ASPEED_CLK_D2PLL>; 138 status = "disabled"; 139 }; 140 141 mac1: ethernet@1e680000 { 142 compatible = "aspeed,ast2500-mac", "faraday,ftgmac100"; 143 reg = <0x1e680000 0x180>; 144 interrupts = <3>; 145 clocks = <&scu ASPEED_CLK_GATE_MAC2CLK>, <&scu ASPEED_CLK_D2PLL>; 146 status = "disabled"; 147 }; 148 149 ehci0: usb@1e6a1000 { 150 compatible = "aspeed,ast2500-ehci", "generic-ehci"; 151 reg = <0x1e6a1000 0x100>; 152 interrupts = <5>; 153 status = "disabled"; 154 }; 155 156 ehci1: usb@1e6a3000 { 157 compatible = "aspeed,ast2500-ehci", "generic-ehci"; 158 reg = <0x1e6a3000 0x100>; 159 interrupts = <13>; 160 status = "disabled"; 161 }; 162 163 uhci: usb@1e6b0000 { 164 compatible = "aspeed,ast2500-uhci", "generic-uhci"; 165 reg = <0x1e6b0000 0x100>; 166 interrupts = <14>; 167 #ports = <2>; 168 status = "disabled"; 169 }; 170 171 apb { 172 compatible = "simple-bus"; 173 #address-cells = <1>; 174 #size-cells = <1>; 175 ranges; 176 177 syscon: syscon@1e6e2000 { 178 compatible = "aspeed,g5-scu", "syscon", "simple-mfd"; 179 reg = <0x1e6e2000 0x1a8>; 180 #clock-cells = <1>; 181 #reset-cells = <1>; 182 183 pinctrl: pinctrl { 184 compatible = "aspeed,g5-pinctrl"; 185 aspeed,external-nodes = <&gfx &lhc>; 186 187 }; 188 }; 189 190 rng: hwrng@1e6e2078 { 191 compatible = "timeriomem_rng"; 192 reg = <0x1e6e2078 0x4>; 193 period = <1>; 194 quality = <100>; 195 }; 196 197 gfx: display@1e6e6000 { 198 compatible = "aspeed,ast2500-gfx", "syscon"; 199 reg = <0x1e6e6000 0x1000>; 200 reg-io-width = <4>; 201 }; 202 203 adc: adc@1e6e9000 { 204 compatible = "aspeed,ast2500-adc"; 205 reg = <0x1e6e9000 0xb0>; 206 #io-channel-cells = <1>; 207 status = "disabled"; 208 }; 209 210 sram@1e720000 { 211 compatible = "mmio-sram"; 212 reg = <0x1e720000 0x9000>; // 36K 213 }; 214 215 sdhci: sdhci@1e740000 { 216 #interrupt-cells = <1>; 217 compatible = "aspeed,aspeed-sdhci-irq", "simple-mfd"; 218 reg = <0x1e740000 0x1000>; 219 interrupts = <26>; 220 interrupt-controller; 221 clocks = <&scu ASPEED_CLK_GATE_SDCLK>, <&scu ASPEED_CLK_GATE_SDEXTCLK>; 222 clock-names = "ctrlclk", "extclk"; 223 #address-cells = <1>; 224 #size-cells = <1>; 225 ranges = <0x0 0x1e740000 0x1000>; 226 227 sdhci_slot0: sdhci_slot0@100 { 228 compatible = "aspeed,sdhci-ast2500"; 229 reg = <0x100 0x100>; 230 interrupts = <0>; 231 interrupt-parent = <&sdhci>; 232 sdhci,auto-cmd12; 233 clocks = <&scu ASPEED_CLK_SDIO>; 234 status = "disabled"; 235 }; 236 237 sdhci_slot1: sdhci_slot1@200 { 238 compatible = "aspeed,sdhci-ast2500"; 239 reg = <0x200 0x100>; 240 interrupts = <1>; 241 interrupt-parent = <&sdhci>; 242 sdhci,auto-cmd12; 243 clocks = <&scu ASPEED_CLK_SDIO>; 244 status = "disabled"; 245 }; 246 247 }; 248 249 gpio: gpio@1e780000 { 250 #gpio-cells = <2>; 251 gpio-controller; 252 compatible = "aspeed,ast2500-gpio"; 253 reg = <0x1e780000 0x1000>; 254 interrupts = <20>; 255 gpio-ranges = <&pinctrl 0 0 220>; 256 interrupt-controller; 257 }; 258 259 timer: timer@1e782000 { 260 /* This timer is a Faraday FTTMR010 derivative */ 261 compatible = "aspeed,ast2400-timer"; 262 reg = <0x1e782000 0x90>; 263 }; 264 265 uart1: serial@1e783000 { 266 compatible = "ns16550a"; 267 reg = <0x1e783000 0x20>; 268 reg-shift = <2>; 269 interrupts = <9>; 270 clocks = <&scu ASPEED_CLK_GATE_UART1CLK>; 271 no-loopback-test; 272 status = "disabled"; 273 }; 274 275 uart5: serial@1e784000 { 276 compatible = "ns16550a"; 277 reg = <0x1e784000 0x20>; 278 reg-shift = <2>; 279 interrupts = <10>; 280 clocks = <&scu ASPEED_CLK_GATE_UART5CLK>; 281 no-loopback-test; 282 status = "disabled"; 283 }; 284 285 wdt1: watchdog@1e785000 { 286 compatible = "aspeed,wdt"; 287 reg = <0x1e785000 0x1c>; 288 interrupts = <27>; 289 }; 290 291 wdt2: watchdog@1e785020 { 292 compatible = "aspeed,wdt"; 293 reg = <0x1e785020 0x1c>; 294 interrupts = <27>; 295 status = "disabled"; 296 }; 297 298 wdt3: watchdog@1e785040 { 299 compatible = "aspeed,wdt"; 300 reg = <0x1e785040 0x1c>; 301 status = "disabled"; 302 }; 303 304 pwm_tacho: pwm-tacho-controller@1e786000 { 305 compatible = "aspeed,ast2500-pwm-tacho"; 306 #address-cells = <1>; 307 #size-cells = <0>; 308 reg = <0x1e786000 0x1000>; 309 status = "disabled"; 310 }; 311 312 vuart: serial@1e787000 { 313 compatible = "aspeed,ast2500-vuart"; 314 reg = <0x1e787000 0x40>; 315 reg-shift = <2>; 316 interrupts = <8>; 317 no-loopback-test; 318 status = "disabled"; 319 }; 320 321 lpc: lpc@1e789000 { 322 compatible = "aspeed,ast2500-lpc", "simple-mfd"; 323 reg = <0x1e789000 0x1000>; 324 325 #address-cells = <1>; 326 #size-cells = <1>; 327 ranges = <0x0 0x1e789000 0x1000>; 328 329 lpc_bmc: lpc-bmc@0 { 330 compatible = "aspeed,ast2500-lpc-bmc"; 331 reg = <0x0 0x80>; 332 }; 333 334 lpc_host: lpc-host@80 { 335 compatible = "aspeed,ast2500-lpc-host", "simple-mfd", "syscon"; 336 reg = <0x80 0x1e0>; 337 reg-io-width = <4>; 338 339 #address-cells = <1>; 340 #size-cells = <1>; 341 ranges = <0x0 0x80 0x1e0>; 342 343 lpc_ctrl: lpc-ctrl@0 { 344 compatible = "aspeed,ast2500-lpc-ctrl"; 345 reg = <0x0 0x80>; 346 status = "disabled"; 347 }; 348 349 lpc_snoop: lpc-snoop@0 { 350 compatible = "aspeed,ast2500-lpc-snoop"; 351 reg = <0x0 0x80>; 352 interrupts = <8>; 353 status = "disabled"; 354 }; 355 356 lhc: lhc@20 { 357 compatible = "aspeed,ast2500-lhc"; 358 reg = <0x20 0x24 0x48 0x8>; 359 }; 360 361 lpc_reset: reset-controller@18 { 362 compatible = "aspeed,ast2500-lpc-reset"; 363 reg = <0x18 0x4>; 364 #reset-cells = <1>; 365 }; 366 367 ibt: ibt@c0 { 368 compatible = "aspeed,ast2500-ibt-bmc"; 369 reg = <0xc0 0x18>; 370 interrupts = <8>; 371 status = "disabled"; 372 }; 373 }; 374 }; 375 376 uart2: serial@1e78d000 { 377 compatible = "ns16550a"; 378 reg = <0x1e78d000 0x20>; 379 reg-shift = <2>; 380 interrupts = <32>; 381 clocks = <&scu ASPEED_CLK_GATE_UART2CLK>; 382 no-loopback-test; 383 status = "disabled"; 384 }; 385 386 uart3: serial@1e78e000 { 387 compatible = "ns16550a"; 388 reg = <0x1e78e000 0x20>; 389 reg-shift = <2>; 390 interrupts = <33>; 391 clocks = <&scu ASPEED_CLK_GATE_UART3CLK>; 392 no-loopback-test; 393 status = "disabled"; 394 }; 395 396 uart4: serial@1e78f000 { 397 compatible = "ns16550a"; 398 reg = <0x1e78f000 0x20>; 399 reg-shift = <2>; 400 interrupts = <34>; 401 clocks = <&scu ASPEED_CLK_GATE_UART4CLK>; 402 no-loopback-test; 403 status = "disabled"; 404 }; 405 406 i2c: i2c@1e78a000 { 407 compatible = "simple-bus"; 408 #address-cells = <1>; 409 #size-cells = <1>; 410 ranges = <0 0x1e78a000 0x1000>; 411 }; 412 }; 413 }; 414}; 415 416&i2c { 417 i2c_ic: interrupt-controller@0 { 418 #interrupt-cells = <1>; 419 compatible = "aspeed,ast2500-i2c-ic"; 420 reg = <0x0 0x40>; 421 interrupts = <12>; 422 interrupt-controller; 423 }; 424 425 i2c0: i2c-bus@40 { 426 #address-cells = <1>; 427 #size-cells = <0>; 428 #interrupt-cells = <1>; 429 430 reg = <0x40 0x40>; 431 compatible = "aspeed,ast2500-i2c-bus"; 432 bus-frequency = <100000>; 433 interrupts = <0>; 434 interrupt-parent = <&i2c_ic>; 435 clocks = <&scu ASPEED_CLK_APB>; 436 status = "disabled"; 437 /* Does not need pinctrl properties */ 438 }; 439 440 i2c1: i2c-bus@80 { 441 #address-cells = <1>; 442 #size-cells = <0>; 443 #interrupt-cells = <1>; 444 445 reg = <0x80 0x40>; 446 compatible = "aspeed,ast2500-i2c-bus"; 447 bus-frequency = <100000>; 448 interrupts = <1>; 449 interrupt-parent = <&i2c_ic>; 450 clocks = <&scu ASPEED_CLK_APB>; 451 status = "disabled"; 452 /* Does not need pinctrl properties */ 453 }; 454 455 i2c2: i2c-bus@c0 { 456 #address-cells = <1>; 457 #size-cells = <0>; 458 #interrupt-cells = <1>; 459 460 reg = <0xc0 0x40>; 461 compatible = "aspeed,ast2500-i2c-bus"; 462 bus-frequency = <100000>; 463 interrupts = <2>; 464 interrupt-parent = <&i2c_ic>; 465 clocks = <&scu ASPEED_CLK_APB>; 466 pinctrl-names = "default"; 467 pinctrl-0 = <&pinctrl_i2c3_default>; 468 status = "disabled"; 469 }; 470 471 i2c3: i2c-bus@100 { 472 #address-cells = <1>; 473 #size-cells = <0>; 474 #interrupt-cells = <1>; 475 476 reg = <0x100 0x40>; 477 compatible = "aspeed,ast2500-i2c-bus"; 478 bus-frequency = <100000>; 479 interrupts = <3>; 480 interrupt-parent = <&i2c_ic>; 481 clocks = <&scu ASPEED_CLK_APB>; 482 pinctrl-names = "default"; 483 pinctrl-0 = <&pinctrl_i2c4_default>; 484 status = "disabled"; 485 }; 486 487 i2c4: i2c-bus@140 { 488 #address-cells = <1>; 489 #size-cells = <0>; 490 #interrupt-cells = <1>; 491 492 reg = <0x140 0x40>; 493 compatible = "aspeed,ast2500-i2c-bus"; 494 bus-frequency = <100000>; 495 interrupts = <4>; 496 interrupt-parent = <&i2c_ic>; 497 clocks = <&scu ASPEED_CLK_APB>; 498 pinctrl-names = "default"; 499 pinctrl-0 = <&pinctrl_i2c5_default>; 500 status = "disabled"; 501 }; 502 503 i2c5: i2c-bus@180 { 504 #address-cells = <1>; 505 #size-cells = <0>; 506 #interrupt-cells = <1>; 507 508 reg = <0x180 0x40>; 509 compatible = "aspeed,ast2500-i2c-bus"; 510 bus-frequency = <100000>; 511 interrupts = <5>; 512 interrupt-parent = <&i2c_ic>; 513 clocks = <&scu ASPEED_CLK_APB>; 514 pinctrl-names = "default"; 515 pinctrl-0 = <&pinctrl_i2c6_default>; 516 status = "disabled"; 517 }; 518 519 i2c6: i2c-bus@1c0 { 520 #address-cells = <1>; 521 #size-cells = <0>; 522 #interrupt-cells = <1>; 523 524 reg = <0x1c0 0x40>; 525 compatible = "aspeed,ast2500-i2c-bus"; 526 bus-frequency = <100000>; 527 interrupts = <6>; 528 interrupt-parent = <&i2c_ic>; 529 clocks = <&scu ASPEED_CLK_APB>; 530 pinctrl-names = "default"; 531 pinctrl-0 = <&pinctrl_i2c7_default>; 532 status = "disabled"; 533 }; 534 535 i2c7: i2c-bus@300 { 536 #address-cells = <1>; 537 #size-cells = <0>; 538 #interrupt-cells = <1>; 539 540 reg = <0x300 0x40>; 541 compatible = "aspeed,ast2500-i2c-bus"; 542 bus-frequency = <100000>; 543 interrupts = <7>; 544 interrupt-parent = <&i2c_ic>; 545 clocks = <&scu ASPEED_CLK_APB>; 546 pinctrl-names = "default"; 547 pinctrl-0 = <&pinctrl_i2c8_default>; 548 status = "disabled"; 549 }; 550 551 i2c8: i2c-bus@340 { 552 #address-cells = <1>; 553 #size-cells = <0>; 554 #interrupt-cells = <1>; 555 556 reg = <0x340 0x40>; 557 compatible = "aspeed,ast2500-i2c-bus"; 558 bus-frequency = <100000>; 559 interrupts = <8>; 560 interrupt-parent = <&i2c_ic>; 561 clocks = <&scu ASPEED_CLK_APB>; 562 pinctrl-names = "default"; 563 pinctrl-0 = <&pinctrl_i2c9_default>; 564 status = "disabled"; 565 }; 566 567 i2c9: i2c-bus@380 { 568 #address-cells = <1>; 569 #size-cells = <0>; 570 #interrupt-cells = <1>; 571 572 reg = <0x380 0x40>; 573 compatible = "aspeed,ast2500-i2c-bus"; 574 bus-frequency = <100000>; 575 interrupts = <9>; 576 interrupt-parent = <&i2c_ic>; 577 clocks = <&scu ASPEED_CLK_APB>; 578 pinctrl-names = "default"; 579 pinctrl-0 = <&pinctrl_i2c10_default>; 580 status = "disabled"; 581 }; 582 583 i2c10: i2c-bus@3c0 { 584 #address-cells = <1>; 585 #size-cells = <0>; 586 #interrupt-cells = <1>; 587 588 reg = <0x3c0 0x40>; 589 compatible = "aspeed,ast2500-i2c-bus"; 590 bus-frequency = <100000>; 591 interrupts = <10>; 592 interrupt-parent = <&i2c_ic>; 593 clocks = <&scu ASPEED_CLK_APB>; 594 pinctrl-names = "default"; 595 pinctrl-0 = <&pinctrl_i2c11_default>; 596 status = "disabled"; 597 }; 598 599 i2c11: i2c-bus@400 { 600 #address-cells = <1>; 601 #size-cells = <0>; 602 #interrupt-cells = <1>; 603 604 reg = <0x400 0x40>; 605 compatible = "aspeed,ast2500-i2c-bus"; 606 bus-frequency = <100000>; 607 interrupts = <11>; 608 interrupt-parent = <&i2c_ic>; 609 clocks = <&scu ASPEED_CLK_APB>; 610 pinctrl-names = "default"; 611 pinctrl-0 = <&pinctrl_i2c12_default>; 612 status = "disabled"; 613 }; 614 615 i2c12: i2c-bus@440 { 616 #address-cells = <1>; 617 #size-cells = <0>; 618 #interrupt-cells = <1>; 619 620 reg = <0x440 0x40>; 621 compatible = "aspeed,ast2500-i2c-bus"; 622 bus-frequency = <100000>; 623 interrupts = <12>; 624 interrupt-parent = <&i2c_ic>; 625 clocks = <&scu ASPEED_CLK_APB>; 626 pinctrl-names = "default"; 627 pinctrl-0 = <&pinctrl_i2c13_default>; 628 status = "disabled"; 629 }; 630 631 i2c13: i2c-bus@480 { 632 #address-cells = <1>; 633 #size-cells = <0>; 634 #interrupt-cells = <1>; 635 636 reg = <0x480 0x40>; 637 compatible = "aspeed,ast2500-i2c-bus"; 638 bus-frequency = <100000>; 639 interrupts = <13>; 640 interrupt-parent = <&i2c_ic>; 641 clocks = <&scu ASPEED_CLK_APB>; 642 pinctrl-names = "default"; 643 pinctrl-0 = <&pinctrl_i2c14_default>; 644 status = "disabled"; 645 }; 646}; 647 648&pinctrl { 649 pinctrl_acpi_default: acpi_default { 650 function = "ACPI"; 651 groups = "ACPI"; 652 }; 653 654 pinctrl_adc0_default: adc0_default { 655 function = "ADC0"; 656 groups = "ADC0"; 657 }; 658 659 pinctrl_adc1_default: adc1_default { 660 function = "ADC1"; 661 groups = "ADC1"; 662 }; 663 664 pinctrl_adc10_default: adc10_default { 665 function = "ADC10"; 666 groups = "ADC10"; 667 }; 668 669 pinctrl_adc11_default: adc11_default { 670 function = "ADC11"; 671 groups = "ADC11"; 672 }; 673 674 pinctrl_adc12_default: adc12_default { 675 function = "ADC12"; 676 groups = "ADC12"; 677 }; 678 679 pinctrl_adc13_default: adc13_default { 680 function = "ADC13"; 681 groups = "ADC13"; 682 }; 683 684 pinctrl_adc14_default: adc14_default { 685 function = "ADC14"; 686 groups = "ADC14"; 687 }; 688 689 pinctrl_adc15_default: adc15_default { 690 function = "ADC15"; 691 groups = "ADC15"; 692 }; 693 694 pinctrl_adc2_default: adc2_default { 695 function = "ADC2"; 696 groups = "ADC2"; 697 }; 698 699 pinctrl_adc3_default: adc3_default { 700 function = "ADC3"; 701 groups = "ADC3"; 702 }; 703 704 pinctrl_adc4_default: adc4_default { 705 function = "ADC4"; 706 groups = "ADC4"; 707 }; 708 709 pinctrl_adc5_default: adc5_default { 710 function = "ADC5"; 711 groups = "ADC5"; 712 }; 713 714 pinctrl_adc6_default: adc6_default { 715 function = "ADC6"; 716 groups = "ADC6"; 717 }; 718 719 pinctrl_adc7_default: adc7_default { 720 function = "ADC7"; 721 groups = "ADC7"; 722 }; 723 724 pinctrl_adc8_default: adc8_default { 725 function = "ADC8"; 726 groups = "ADC8"; 727 }; 728 729 pinctrl_adc9_default: adc9_default { 730 function = "ADC9"; 731 groups = "ADC9"; 732 }; 733 734 pinctrl_bmcint_default: bmcint_default { 735 function = "BMCINT"; 736 groups = "BMCINT"; 737 }; 738 739 pinctrl_ddcclk_default: ddcclk_default { 740 function = "DDCCLK"; 741 groups = "DDCCLK"; 742 }; 743 744 pinctrl_ddcdat_default: ddcdat_default { 745 function = "DDCDAT"; 746 groups = "DDCDAT"; 747 }; 748 749 pinctrl_espi_default: espi_default { 750 function = "ESPI"; 751 groups = "ESPI"; 752 }; 753 754 pinctrl_fwspics1_default: fwspics1_default { 755 function = "FWSPICS1"; 756 groups = "FWSPICS1"; 757 }; 758 759 pinctrl_fwspics2_default: fwspics2_default { 760 function = "FWSPICS2"; 761 groups = "FWSPICS2"; 762 }; 763 764 pinctrl_gpid0_default: gpid0_default { 765 function = "GPID0"; 766 groups = "GPID0"; 767 }; 768 769 pinctrl_gpid2_default: gpid2_default { 770 function = "GPID2"; 771 groups = "GPID2"; 772 }; 773 774 pinctrl_gpid4_default: gpid4_default { 775 function = "GPID4"; 776 groups = "GPID4"; 777 }; 778 779 pinctrl_gpid6_default: gpid6_default { 780 function = "GPID6"; 781 groups = "GPID6"; 782 }; 783 784 pinctrl_gpie0_default: gpie0_default { 785 function = "GPIE0"; 786 groups = "GPIE0"; 787 }; 788 789 pinctrl_gpie2_default: gpie2_default { 790 function = "GPIE2"; 791 groups = "GPIE2"; 792 }; 793 794 pinctrl_gpie4_default: gpie4_default { 795 function = "GPIE4"; 796 groups = "GPIE4"; 797 }; 798 799 pinctrl_gpie6_default: gpie6_default { 800 function = "GPIE6"; 801 groups = "GPIE6"; 802 }; 803 804 pinctrl_i2c10_default: i2c10_default { 805 function = "I2C10"; 806 groups = "I2C10"; 807 }; 808 809 pinctrl_i2c11_default: i2c11_default { 810 function = "I2C11"; 811 groups = "I2C11"; 812 }; 813 814 pinctrl_i2c12_default: i2c12_default { 815 function = "I2C12"; 816 groups = "I2C12"; 817 }; 818 819 pinctrl_i2c13_default: i2c13_default { 820 function = "I2C13"; 821 groups = "I2C13"; 822 }; 823 824 pinctrl_i2c14_default: i2c14_default { 825 function = "I2C14"; 826 groups = "I2C14"; 827 }; 828 829 pinctrl_i2c3_default: i2c3_default { 830 function = "I2C3"; 831 groups = "I2C3"; 832 }; 833 834 pinctrl_i2c4_default: i2c4_default { 835 function = "I2C4"; 836 groups = "I2C4"; 837 }; 838 839 pinctrl_i2c5_default: i2c5_default { 840 function = "I2C5"; 841 groups = "I2C5"; 842 }; 843 844 pinctrl_i2c6_default: i2c6_default { 845 function = "I2C6"; 846 groups = "I2C6"; 847 }; 848 849 pinctrl_i2c7_default: i2c7_default { 850 function = "I2C7"; 851 groups = "I2C7"; 852 }; 853 854 pinctrl_i2c8_default: i2c8_default { 855 function = "I2C8"; 856 groups = "I2C8"; 857 }; 858 859 pinctrl_i2c9_default: i2c9_default { 860 function = "I2C9"; 861 groups = "I2C9"; 862 }; 863 864 pinctrl_lad0_default: lad0_default { 865 function = "LAD0"; 866 groups = "LAD0"; 867 }; 868 869 pinctrl_lad1_default: lad1_default { 870 function = "LAD1"; 871 groups = "LAD1"; 872 }; 873 874 pinctrl_lad2_default: lad2_default { 875 function = "LAD2"; 876 groups = "LAD2"; 877 }; 878 879 pinctrl_lad3_default: lad3_default { 880 function = "LAD3"; 881 groups = "LAD3"; 882 }; 883 884 pinctrl_lclk_default: lclk_default { 885 function = "LCLK"; 886 groups = "LCLK"; 887 }; 888 889 pinctrl_lframe_default: lframe_default { 890 function = "LFRAME"; 891 groups = "LFRAME"; 892 }; 893 894 pinctrl_lpchc_default: lpchc_default { 895 function = "LPCHC"; 896 groups = "LPCHC"; 897 }; 898 899 pinctrl_lpcpd_default: lpcpd_default { 900 function = "LPCPD"; 901 groups = "LPCPD"; 902 }; 903 904 pinctrl_lpcplus_default: lpcplus_default { 905 function = "LPCPLUS"; 906 groups = "LPCPLUS"; 907 }; 908 909 pinctrl_lpcpme_default: lpcpme_default { 910 function = "LPCPME"; 911 groups = "LPCPME"; 912 }; 913 914 pinctrl_lpcrst_default: lpcrst_default { 915 function = "LPCRST"; 916 groups = "LPCRST"; 917 }; 918 919 pinctrl_lpcsmi_default: lpcsmi_default { 920 function = "LPCSMI"; 921 groups = "LPCSMI"; 922 }; 923 924 pinctrl_lsirq_default: lsirq_default { 925 function = "LSIRQ"; 926 groups = "LSIRQ"; 927 }; 928 929 pinctrl_mac1link_default: mac1link_default { 930 function = "MAC1LINK"; 931 groups = "MAC1LINK"; 932 }; 933 934 pinctrl_mac2link_default: mac2link_default { 935 function = "MAC2LINK"; 936 groups = "MAC2LINK"; 937 }; 938 939 pinctrl_mdio1_default: mdio1_default { 940 function = "MDIO1"; 941 groups = "MDIO1"; 942 }; 943 944 pinctrl_mdio2_default: mdio2_default { 945 function = "MDIO2"; 946 groups = "MDIO2"; 947 }; 948 949 pinctrl_ncts1_default: ncts1_default { 950 function = "NCTS1"; 951 groups = "NCTS1"; 952 }; 953 954 pinctrl_ncts2_default: ncts2_default { 955 function = "NCTS2"; 956 groups = "NCTS2"; 957 }; 958 959 pinctrl_ncts3_default: ncts3_default { 960 function = "NCTS3"; 961 groups = "NCTS3"; 962 }; 963 964 pinctrl_ncts4_default: ncts4_default { 965 function = "NCTS4"; 966 groups = "NCTS4"; 967 }; 968 969 pinctrl_ndcd1_default: ndcd1_default { 970 function = "NDCD1"; 971 groups = "NDCD1"; 972 }; 973 974 pinctrl_ndcd2_default: ndcd2_default { 975 function = "NDCD2"; 976 groups = "NDCD2"; 977 }; 978 979 pinctrl_ndcd3_default: ndcd3_default { 980 function = "NDCD3"; 981 groups = "NDCD3"; 982 }; 983 984 pinctrl_ndcd4_default: ndcd4_default { 985 function = "NDCD4"; 986 groups = "NDCD4"; 987 }; 988 989 pinctrl_ndsr1_default: ndsr1_default { 990 function = "NDSR1"; 991 groups = "NDSR1"; 992 }; 993 994 pinctrl_ndsr2_default: ndsr2_default { 995 function = "NDSR2"; 996 groups = "NDSR2"; 997 }; 998 999 pinctrl_ndsr3_default: ndsr3_default { 1000 function = "NDSR3"; 1001 groups = "NDSR3"; 1002 }; 1003 1004 pinctrl_ndsr4_default: ndsr4_default { 1005 function = "NDSR4"; 1006 groups = "NDSR4"; 1007 }; 1008 1009 pinctrl_ndtr1_default: ndtr1_default { 1010 function = "NDTR1"; 1011 groups = "NDTR1"; 1012 }; 1013 1014 pinctrl_ndtr2_default: ndtr2_default { 1015 function = "NDTR2"; 1016 groups = "NDTR2"; 1017 }; 1018 1019 pinctrl_ndtr3_default: ndtr3_default { 1020 function = "NDTR3"; 1021 groups = "NDTR3"; 1022 }; 1023 1024 pinctrl_ndtr4_default: ndtr4_default { 1025 function = "NDTR4"; 1026 groups = "NDTR4"; 1027 }; 1028 1029 pinctrl_nri1_default: nri1_default { 1030 function = "NRI1"; 1031 groups = "NRI1"; 1032 }; 1033 1034 pinctrl_nri2_default: nri2_default { 1035 function = "NRI2"; 1036 groups = "NRI2"; 1037 }; 1038 1039 pinctrl_nri3_default: nri3_default { 1040 function = "NRI3"; 1041 groups = "NRI3"; 1042 }; 1043 1044 pinctrl_nri4_default: nri4_default { 1045 function = "NRI4"; 1046 groups = "NRI4"; 1047 }; 1048 1049 pinctrl_nrts1_default: nrts1_default { 1050 function = "NRTS1"; 1051 groups = "NRTS1"; 1052 }; 1053 1054 pinctrl_nrts2_default: nrts2_default { 1055 function = "NRTS2"; 1056 groups = "NRTS2"; 1057 }; 1058 1059 pinctrl_nrts3_default: nrts3_default { 1060 function = "NRTS3"; 1061 groups = "NRTS3"; 1062 }; 1063 1064 pinctrl_nrts4_default: nrts4_default { 1065 function = "NRTS4"; 1066 groups = "NRTS4"; 1067 }; 1068 1069 pinctrl_oscclk_default: oscclk_default { 1070 function = "OSCCLK"; 1071 groups = "OSCCLK"; 1072 }; 1073 1074 pinctrl_pewake_default: pewake_default { 1075 function = "PEWAKE"; 1076 groups = "PEWAKE"; 1077 }; 1078 1079 pinctrl_pnor_default: pnor_default { 1080 function = "PNOR"; 1081 groups = "PNOR"; 1082 }; 1083 1084 pinctrl_pwm0_default: pwm0_default { 1085 function = "PWM0"; 1086 groups = "PWM0"; 1087 }; 1088 1089 pinctrl_pwm1_default: pwm1_default { 1090 function = "PWM1"; 1091 groups = "PWM1"; 1092 }; 1093 1094 pinctrl_pwm2_default: pwm2_default { 1095 function = "PWM2"; 1096 groups = "PWM2"; 1097 }; 1098 1099 pinctrl_pwm3_default: pwm3_default { 1100 function = "PWM3"; 1101 groups = "PWM3"; 1102 }; 1103 1104 pinctrl_pwm4_default: pwm4_default { 1105 function = "PWM4"; 1106 groups = "PWM4"; 1107 }; 1108 1109 pinctrl_pwm5_default: pwm5_default { 1110 function = "PWM5"; 1111 groups = "PWM5"; 1112 }; 1113 1114 pinctrl_pwm6_default: pwm6_default { 1115 function = "PWM6"; 1116 groups = "PWM6"; 1117 }; 1118 1119 pinctrl_pwm7_default: pwm7_default { 1120 function = "PWM7"; 1121 groups = "PWM7"; 1122 }; 1123 1124 pinctrl_rgmii1_default: rgmii1_default { 1125 function = "RGMII1"; 1126 groups = "RGMII1"; 1127 }; 1128 1129 pinctrl_rgmii2_default: rgmii2_default { 1130 function = "RGMII2"; 1131 groups = "RGMII2"; 1132 }; 1133 1134 pinctrl_rmii1_default: rmii1_default { 1135 function = "RMII1"; 1136 groups = "RMII1"; 1137 }; 1138 1139 pinctrl_rmii2_default: rmii2_default { 1140 function = "RMII2"; 1141 groups = "RMII2"; 1142 }; 1143 1144 pinctrl_rxd1_default: rxd1_default { 1145 function = "RXD1"; 1146 groups = "RXD1"; 1147 }; 1148 1149 pinctrl_rxd2_default: rxd2_default { 1150 function = "RXD2"; 1151 groups = "RXD2"; 1152 }; 1153 1154 pinctrl_rxd3_default: rxd3_default { 1155 function = "RXD3"; 1156 groups = "RXD3"; 1157 }; 1158 1159 pinctrl_rxd4_default: rxd4_default { 1160 function = "RXD4"; 1161 groups = "RXD4"; 1162 }; 1163 1164 pinctrl_salt1_default: salt1_default { 1165 function = "SALT1"; 1166 groups = "SALT1"; 1167 }; 1168 1169 pinctrl_salt10_default: salt10_default { 1170 function = "SALT10"; 1171 groups = "SALT10"; 1172 }; 1173 1174 pinctrl_salt11_default: salt11_default { 1175 function = "SALT11"; 1176 groups = "SALT11"; 1177 }; 1178 1179 pinctrl_salt12_default: salt12_default { 1180 function = "SALT12"; 1181 groups = "SALT12"; 1182 }; 1183 1184 pinctrl_salt13_default: salt13_default { 1185 function = "SALT13"; 1186 groups = "SALT13"; 1187 }; 1188 1189 pinctrl_salt14_default: salt14_default { 1190 function = "SALT14"; 1191 groups = "SALT14"; 1192 }; 1193 1194 pinctrl_salt2_default: salt2_default { 1195 function = "SALT2"; 1196 groups = "SALT2"; 1197 }; 1198 1199 pinctrl_salt3_default: salt3_default { 1200 function = "SALT3"; 1201 groups = "SALT3"; 1202 }; 1203 1204 pinctrl_salt4_default: salt4_default { 1205 function = "SALT4"; 1206 groups = "SALT4"; 1207 }; 1208 1209 pinctrl_salt5_default: salt5_default { 1210 function = "SALT5"; 1211 groups = "SALT5"; 1212 }; 1213 1214 pinctrl_salt6_default: salt6_default { 1215 function = "SALT6"; 1216 groups = "SALT6"; 1217 }; 1218 1219 pinctrl_salt7_default: salt7_default { 1220 function = "SALT7"; 1221 groups = "SALT7"; 1222 }; 1223 1224 pinctrl_salt8_default: salt8_default { 1225 function = "SALT8"; 1226 groups = "SALT8"; 1227 }; 1228 1229 pinctrl_salt9_default: salt9_default { 1230 function = "SALT9"; 1231 groups = "SALT9"; 1232 }; 1233 1234 pinctrl_scl1_default: scl1_default { 1235 function = "SCL1"; 1236 groups = "SCL1"; 1237 }; 1238 1239 pinctrl_scl2_default: scl2_default { 1240 function = "SCL2"; 1241 groups = "SCL2"; 1242 }; 1243 1244 pinctrl_sd1_default: sd1_default { 1245 function = "SD1"; 1246 groups = "SD1"; 1247 }; 1248 1249 pinctrl_sd2_default: sd2_default { 1250 function = "SD2"; 1251 groups = "SD2"; 1252 }; 1253 1254 pinctrl_sda1_default: sda1_default { 1255 function = "SDA1"; 1256 groups = "SDA1"; 1257 }; 1258 1259 pinctrl_sda2_default: sda2_default { 1260 function = "SDA2"; 1261 groups = "SDA2"; 1262 }; 1263 1264 pinctrl_sgps1_default: sgps1_default { 1265 function = "SGPS1"; 1266 groups = "SGPS1"; 1267 }; 1268 1269 pinctrl_sgps2_default: sgps2_default { 1270 function = "SGPS2"; 1271 groups = "SGPS2"; 1272 }; 1273 1274 pinctrl_sioonctrl_default: sioonctrl_default { 1275 function = "SIOONCTRL"; 1276 groups = "SIOONCTRL"; 1277 }; 1278 1279 pinctrl_siopbi_default: siopbi_default { 1280 function = "SIOPBI"; 1281 groups = "SIOPBI"; 1282 }; 1283 1284 pinctrl_siopbo_default: siopbo_default { 1285 function = "SIOPBO"; 1286 groups = "SIOPBO"; 1287 }; 1288 1289 pinctrl_siopwreq_default: siopwreq_default { 1290 function = "SIOPWREQ"; 1291 groups = "SIOPWREQ"; 1292 }; 1293 1294 pinctrl_siopwrgd_default: siopwrgd_default { 1295 function = "SIOPWRGD"; 1296 groups = "SIOPWRGD"; 1297 }; 1298 1299 pinctrl_sios3_default: sios3_default { 1300 function = "SIOS3"; 1301 groups = "SIOS3"; 1302 }; 1303 1304 pinctrl_sios5_default: sios5_default { 1305 function = "SIOS5"; 1306 groups = "SIOS5"; 1307 }; 1308 1309 pinctrl_siosci_default: siosci_default { 1310 function = "SIOSCI"; 1311 groups = "SIOSCI"; 1312 }; 1313 1314 pinctrl_spi1_default: spi1_default { 1315 function = "SPI1"; 1316 groups = "SPI1"; 1317 }; 1318 1319 pinctrl_spi1cs1_default: spi1cs1_default { 1320 function = "SPI1CS1"; 1321 groups = "SPI1CS1"; 1322 }; 1323 1324 pinctrl_spi1debug_default: spi1debug_default { 1325 function = "SPI1DEBUG"; 1326 groups = "SPI1DEBUG"; 1327 }; 1328 1329 pinctrl_spi1passthru_default: spi1passthru_default { 1330 function = "SPI1PASSTHRU"; 1331 groups = "SPI1PASSTHRU"; 1332 }; 1333 1334 pinctrl_spi2ck_default: spi2ck_default { 1335 function = "SPI2CK"; 1336 groups = "SPI2CK"; 1337 }; 1338 1339 pinctrl_spi2cs0_default: spi2cs0_default { 1340 function = "SPI2CS0"; 1341 groups = "SPI2CS0"; 1342 }; 1343 1344 pinctrl_spi2cs1_default: spi2cs1_default { 1345 function = "SPI2CS1"; 1346 groups = "SPI2CS1"; 1347 }; 1348 1349 pinctrl_spi2miso_default: spi2miso_default { 1350 function = "SPI2MISO"; 1351 groups = "SPI2MISO"; 1352 }; 1353 1354 pinctrl_spi2mosi_default: spi2mosi_default { 1355 function = "SPI2MOSI"; 1356 groups = "SPI2MOSI"; 1357 }; 1358 1359 pinctrl_timer3_default: timer3_default { 1360 function = "TIMER3"; 1361 groups = "TIMER3"; 1362 }; 1363 1364 pinctrl_timer4_default: timer4_default { 1365 function = "TIMER4"; 1366 groups = "TIMER4"; 1367 }; 1368 1369 pinctrl_timer5_default: timer5_default { 1370 function = "TIMER5"; 1371 groups = "TIMER5"; 1372 }; 1373 1374 pinctrl_timer6_default: timer6_default { 1375 function = "TIMER6"; 1376 groups = "TIMER6"; 1377 }; 1378 1379 pinctrl_timer7_default: timer7_default { 1380 function = "TIMER7"; 1381 groups = "TIMER7"; 1382 }; 1383 1384 pinctrl_timer8_default: timer8_default { 1385 function = "TIMER8"; 1386 groups = "TIMER8"; 1387 }; 1388 1389 pinctrl_txd1_default: txd1_default { 1390 function = "TXD1"; 1391 groups = "TXD1"; 1392 }; 1393 1394 pinctrl_txd2_default: txd2_default { 1395 function = "TXD2"; 1396 groups = "TXD2"; 1397 }; 1398 1399 pinctrl_txd3_default: txd3_default { 1400 function = "TXD3"; 1401 groups = "TXD3"; 1402 }; 1403 1404 pinctrl_txd4_default: txd4_default { 1405 function = "TXD4"; 1406 groups = "TXD4"; 1407 }; 1408 1409 pinctrl_uart6_default: uart6_default { 1410 function = "UART6"; 1411 groups = "UART6"; 1412 }; 1413 1414 pinctrl_usbcki_default: usbcki_default { 1415 function = "USBCKI"; 1416 groups = "USBCKI"; 1417 }; 1418 1419 pinctrl_usb2ah_default: usb2ah_default { 1420 function = "USB2AH"; 1421 groups = "USB2AH"; 1422 }; 1423 1424 pinctrl_usb11bhid_default: usb11bhid_default { 1425 function = "USB11BHID"; 1426 groups = "USB11BHID"; 1427 }; 1428 1429 pinctrl_usb2bh_default: usb2bh_default { 1430 function = "USB2BH"; 1431 groups = "USB2BH"; 1432 }; 1433 1434 pinctrl_vgabiosrom_default: vgabiosrom_default { 1435 function = "VGABIOSROM"; 1436 groups = "VGABIOSROM"; 1437 }; 1438 1439 pinctrl_vgahs_default: vgahs_default { 1440 function = "VGAHS"; 1441 groups = "VGAHS"; 1442 }; 1443 1444 pinctrl_vgavs_default: vgavs_default { 1445 function = "VGAVS"; 1446 groups = "VGAVS"; 1447 }; 1448 1449 pinctrl_vpi24_default: vpi24_default { 1450 function = "VPI24"; 1451 groups = "VPI24"; 1452 }; 1453 1454 pinctrl_vpo_default: vpo_default { 1455 function = "VPO"; 1456 groups = "VPO"; 1457 }; 1458 1459 pinctrl_wdtrst1_default: wdtrst1_default { 1460 function = "WDTRST1"; 1461 groups = "WDTRST1"; 1462 }; 1463 1464 pinctrl_wdtrst2_default: wdtrst2_default { 1465 function = "WDTRST2"; 1466 groups = "WDTRST2"; 1467 }; 1468}; 1469