1/* 2 * This device tree is copied from 3 * https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi 4 */ 5#include "skeleton.dtsi" 6 7/ { 8 model = "Aspeed BMC"; 9 compatible = "aspeed,ast2400"; 10 #address-cells = <1>; 11 #size-cells = <1>; 12 interrupt-parent = <&vic>; 13 14 aliases { 15 i2c0 = &i2c0; 16 i2c1 = &i2c1; 17 i2c2 = &i2c2; 18 i2c3 = &i2c3; 19 i2c4 = &i2c4; 20 i2c5 = &i2c5; 21 i2c6 = &i2c6; 22 i2c7 = &i2c7; 23 i2c8 = &i2c8; 24 i2c9 = &i2c9; 25 i2c10 = &i2c10; 26 i2c11 = &i2c11; 27 i2c12 = &i2c12; 28 i2c13 = &i2c13; 29 serial0 = &uart1; 30 serial1 = &uart2; 31 serial2 = &uart3; 32 serial3 = &uart4; 33 serial4 = &uart5; 34 serial5 = &vuart; 35 }; 36 37 cpus { 38 #address-cells = <1>; 39 #size-cells = <0>; 40 41 cpu@0 { 42 compatible = "arm,arm926ej-s"; 43 device_type = "cpu"; 44 reg = <0>; 45 }; 46 }; 47 48 memory@40000000 { 49 device_type = "memory"; 50 reg = <0x40000000 0>; 51 }; 52 53 ahb { 54 compatible = "simple-bus"; 55 #address-cells = <1>; 56 #size-cells = <1>; 57 ranges; 58 59 fmc: flash-controller@1e620000 { 60 reg = < 0x1e620000 0xc4 61 0x20000000 0x10000000 >; 62 #address-cells = <1>; 63 #size-cells = <0>; 64 compatible = "aspeed,ast2400-fmc"; 65 status = "disabled"; 66 interrupts = <19>; 67 clocks = <&scu ASPEED_CLK_AHB>; 68 num-cs = <3>; 69 flash@0 { 70 reg = < 0 >; 71 compatible = "jedec,spi-nor"; 72 status = "disabled"; 73 }; 74 flash@1 { 75 reg = < 1 >; 76 compatible = "jedec,spi-nor"; 77 status = "disabled"; 78 }; 79 flash@2 { 80 reg = < 2 >; 81 compatible = "jedec,spi-nor"; 82 status = "disabled"; 83 }; 84 }; 85 86 spi1: flash-controller@1e630000 { 87 reg = < 0x1e630000 0xc4 88 0x30000000 0x08000000 >; 89 #address-cells = <1>; 90 #size-cells = <0>; 91 compatible = "aspeed,ast2400-spi"; 92 clocks = <&scu ASPEED_CLK_AHB>; 93 status = "disabled"; 94 num-cs = <2>; 95 flash@0 { 96 reg = < 0 >; 97 compatible = "jedec,spi-nor"; 98 status = "disabled"; 99 }; 100 flash@1 { 101 reg = < 1 >; 102 compatible = "jedec,spi-nor"; 103 status = "disabled"; 104 }; 105 }; 106 107 spi2: flash-controller@1e631000 { 108 reg = < 0x1e631000 0xc4 109 0x38000000 0x08000000 >; 110 #address-cells = <1>; 111 #size-cells = <0>; 112 compatible = "aspeed,ast2400-spi"; 113 clocks = <&scu ASPEED_CLK_AHB>; 114 status = "disabled"; 115 num-cs = <2>; 116 flash@0 { 117 reg = < 0 >; 118 compatible = "jedec,spi-nor"; 119 status = "disabled"; 120 }; 121 flash@1 { 122 reg = < 1 >; 123 compatible = "jedec,spi-nor"; 124 status = "disabled"; 125 }; 126 }; 127 128 vic: interrupt-controller@1e6c0080 { 129 compatible = "aspeed,ast2400-vic"; 130 interrupt-controller; 131 #interrupt-cells = <1>; 132 valid-sources = <0xfefff7ff 0x0807ffff>; 133 reg = <0x1e6c0080 0x80>; 134 }; 135 136 mac0: ethernet@1e660000 { 137 compatible = "aspeed,ast2400-mac", "faraday,ftgmac100"; 138 reg = <0x1e660000 0x180>; 139 interrupts = <2>; 140 clocks = <&scu ASPEED_CLK_GATE_MAC1CLK>, <&scu ASPEED_CLK_D2PLL>; 141 status = "disabled"; 142 }; 143 144 mac1: ethernet@1e680000 { 145 compatible = "aspeed,ast2400-mac", "faraday,ftgmac100"; 146 reg = <0x1e680000 0x180>; 147 interrupts = <3>; 148 clocks = <&scu ASPEED_CLK_GATE_MAC2CLK>, <&scu ASPEED_CLK_D2PLL>; 149 status = "disabled"; 150 }; 151 152 ehci0: usb@1e6a1000 { 153 compatible = "aspeed,ast2400-ehci", "generic-ehci"; 154 reg = <0x1e6a1000 0x100>; 155 interrupts = <5>; 156 status = "disabled"; 157 }; 158 159 ehci1: usb@1e6a3000 { 160 compatible = "aspeed,ast2400-ehci", "generic-ehci"; 161 reg = <0x1e6a3000 0x100>; 162 interrupts = <13>; 163 status = "disabled"; 164 }; 165 166 uhci: usb@1e6b0000 { 167 compatible = "aspeed,ast2400-uhci", "generic-uhci"; 168 reg = <0x1e6b0000 0x100>; 169 interrupts = <14>; 170 #ports = <2>; 171 status = "disabled"; 172 }; 173 174 apb { 175 compatible = "simple-bus"; 176 #address-cells = <1>; 177 #size-cells = <1>; 178 ranges; 179 180 syscon: syscon@1e6e2000 { 181 compatible = "aspeed,g5-scu", "syscon", "simple-mfd"; 182 reg = <0x1e6e2000 0x1a8>; 183 #clock-cells = <1>; 184 #reset-cells = <1>; 185 186 pinctrl: pinctrl { 187 compatible = "aspeed,g5-pinctrl"; 188 aspeed,external-nodes = <&gfx &lhc>; 189 190 }; 191 }; 192 193 rng: hwrng@1e6e2078 { 194 compatible = "timeriomem_rng"; 195 reg = <0x1e6e2078 0x4>; 196 period = <1>; 197 quality = <100>; 198 }; 199 200 gfx: display@1e6e6000 { 201 compatible = "aspeed,ast2400-gfx", "syscon"; 202 reg = <0x1e6e6000 0x1000>; 203 reg-io-width = <4>; 204 }; 205 206 adc: adc@1e6e9000 { 207 compatible = "aspeed,ast2400-adc"; 208 reg = <0x1e6e9000 0xb0>; 209 #io-channel-cells = <1>; 210 status = "disabled"; 211 }; 212 213 sram@1e720000 { 214 compatible = "mmio-sram"; 215 reg = <0x1e720000 0x9000>; // 36K 216 }; 217 218 sdhci: sdhci@1e740000 { 219 #interrupt-cells = <1>; 220 compatible = "aspeed,aspeed-sdhci-irq", "simple-mfd"; 221 reg = <0x1e740000 0x1000>; 222 interrupts = <26>; 223 interrupt-controller; 224 clocks = <&scu ASPEED_CLK_GATE_SDCLK>, <&scu ASPEED_CLK_GATE_SDEXTCLK>; 225 clock-names = "ctrlclk", "extclk"; 226 #address-cells = <1>; 227 #size-cells = <1>; 228 ranges = <0x0 0x1e740000 0x1000>; 229 230 sdhci_slot0: sdhci_slot0@100 { 231 compatible = "aspeed,sdhci-ast2400"; 232 reg = <0x100 0x100>; 233 interrupts = <0>; 234 interrupt-parent = <&sdhci>; 235 sdhci,auto-cmd12; 236 clocks = <&scu ASPEED_CLK_SDIO>; 237 status = "disabled"; 238 }; 239 240 sdhci_slot1: sdhci_slot1@200 { 241 compatible = "aspeed,sdhci-ast2400"; 242 reg = <0x200 0x100>; 243 interrupts = <1>; 244 interrupt-parent = <&sdhci>; 245 sdhci,auto-cmd12; 246 clocks = <&scu ASPEED_CLK_SDIO>; 247 status = "disabled"; 248 }; 249 250 }; 251 252 gpio: gpio@1e780000 { 253 #gpio-cells = <2>; 254 gpio-controller; 255 compatible = "aspeed,ast2400-gpio"; 256 reg = <0x1e780000 0x1000>; 257 interrupts = <20>; 258 gpio-ranges = <&pinctrl 0 0 220>; 259 ngpios = <228>; 260 interrupt-controller; 261 }; 262 263 timer: timer@1e782000 { 264 /* This timer is a Faraday FTTMR010 derivative */ 265 compatible = "aspeed,ast2400-timer"; 266 reg = <0x1e782000 0x90>; 267 }; 268 269 uart1: serial@1e783000 { 270 compatible = "ns16550a"; 271 reg = <0x1e783000 0x20>; 272 reg-shift = <2>; 273 interrupts = <9>; 274 clocks = <&scu ASPEED_CLK_GATE_UART1CLK>; 275 clock-frequency = <24000000>; 276 no-loopback-test; 277 status = "disabled"; 278 }; 279 280 uart5: serial@1e784000 { 281 compatible = "ns16550a"; 282 reg = <0x1e784000 0x20>; 283 reg-shift = <2>; 284 interrupts = <10>; 285 clocks = <&scu ASPEED_CLK_GATE_UART5CLK>; 286 clock-frequency = <24000000>; 287 no-loopback-test; 288 status = "disabled"; 289 }; 290 291 wdt1: watchdog@1e785000 { 292 compatible = "aspeed,wdt"; 293 reg = <0x1e785000 0x1c>; 294 interrupts = <27>; 295 }; 296 297 wdt2: watchdog@1e785020 { 298 compatible = "aspeed,wdt"; 299 reg = <0x1e785020 0x1c>; 300 interrupts = <27>; 301 status = "disabled"; 302 }; 303 304 wdt3: watchdog@1e785040 { 305 compatible = "aspeed,wdt"; 306 reg = <0x1e785040 0x1c>; 307 status = "disabled"; 308 }; 309 310 pwm_tacho: pwm-tacho-controller@1e786000 { 311 compatible = "aspeed,ast2400-pwm-tacho"; 312 #address-cells = <1>; 313 #size-cells = <0>; 314 reg = <0x1e786000 0x1000>; 315 status = "disabled"; 316 }; 317 318 vuart: serial@1e787000 { 319 compatible = "aspeed,ast2400-vuart"; 320 reg = <0x1e787000 0x40>; 321 reg-shift = <2>; 322 interrupts = <8>; 323 no-loopback-test; 324 status = "disabled"; 325 }; 326 327 lpc: lpc@1e789000 { 328 compatible = "aspeed,ast2400-lpc", "simple-mfd"; 329 reg = <0x1e789000 0x1000>; 330 331 #address-cells = <1>; 332 #size-cells = <1>; 333 ranges = <0x0 0x1e789000 0x1000>; 334 335 lpc_bmc: lpc-bmc@0 { 336 compatible = "aspeed,ast2400-lpc-bmc"; 337 reg = <0x0 0x80>; 338 }; 339 340 lpc_host: lpc-host@80 { 341 compatible = "aspeed,ast2400-lpc-host", "simple-mfd", "syscon"; 342 reg = <0x80 0x1e0>; 343 reg-io-width = <4>; 344 345 #address-cells = <1>; 346 #size-cells = <1>; 347 ranges = <0x0 0x80 0x1e0>; 348 349 lpc_ctrl: lpc-ctrl@0 { 350 compatible = "aspeed,ast2400-lpc-ctrl"; 351 reg = <0x0 0x80>; 352 status = "disabled"; 353 }; 354 355 lpc_snoop: lpc-snoop@0 { 356 compatible = "aspeed,ast2400-lpc-snoop"; 357 reg = <0x0 0x80>; 358 interrupts = <8>; 359 status = "disabled"; 360 }; 361 362 lhc: lhc@20 { 363 compatible = "aspeed,ast2400-lhc"; 364 reg = <0x20 0x24 0x48 0x8>; 365 }; 366 367 lpc_reset: reset-controller@18 { 368 compatible = "aspeed,ast2400-lpc-reset"; 369 reg = <0x18 0x4>; 370 #reset-cells = <1>; 371 }; 372 373 ibt: ibt@c0 { 374 compatible = "aspeed,ast2400-ibt-bmc"; 375 reg = <0xc0 0x18>; 376 interrupts = <8>; 377 status = "disabled"; 378 }; 379 }; 380 }; 381 382 uart2: serial@1e78d000 { 383 compatible = "ns16550a"; 384 reg = <0x1e78d000 0x20>; 385 reg-shift = <2>; 386 interrupts = <32>; 387 clocks = <&scu ASPEED_CLK_GATE_UART2CLK>; 388 clock-frequency = <24000000>; 389 no-loopback-test; 390 status = "disabled"; 391 }; 392 393 uart3: serial@1e78e000 { 394 compatible = "ns16550a"; 395 reg = <0x1e78e000 0x20>; 396 reg-shift = <2>; 397 interrupts = <33>; 398 clocks = <&scu ASPEED_CLK_GATE_UART3CLK>; 399 clock-frequency = <24000000>; 400 no-loopback-test; 401 status = "disabled"; 402 }; 403 404 uart4: serial@1e78f000 { 405 compatible = "ns16550a"; 406 reg = <0x1e78f000 0x20>; 407 reg-shift = <2>; 408 interrupts = <34>; 409 clocks = <&scu ASPEED_CLK_GATE_UART4CLK>; 410 clock-frequency = <24000000>; 411 no-loopback-test; 412 status = "disabled"; 413 }; 414 415 i2c: i2c@1e78a000 { 416 compatible = "simple-bus"; 417 #address-cells = <1>; 418 #size-cells = <1>; 419 ranges = <0 0x1e78a000 0x1000>; 420 }; 421 }; 422 }; 423}; 424 425&i2c { 426 i2c_ic: interrupt-controller@0 { 427 #interrupt-cells = <1>; 428 compatible = "aspeed,ast2400-i2c-ic"; 429 reg = <0x0 0x40>; 430 interrupts = <12>; 431 interrupt-controller; 432 resets = <&rst ASPEED_RESET_I2C>; 433 }; 434 435 i2c0: i2c-bus@40 { 436 #address-cells = <1>; 437 #size-cells = <0>; 438 #interrupt-cells = <1>; 439 440 reg = <0x40 0x40>; 441 compatible = "aspeed,ast2400-i2c-bus"; 442 bus-frequency = <100000>; 443 interrupts = <0>; 444 interrupt-parent = <&i2c_ic>; 445 clocks = <&scu ASPEED_CLK_APB>; 446 status = "disabled"; 447 /* Does not need pinctrl properties */ 448 }; 449 450 i2c1: i2c-bus@80 { 451 #address-cells = <1>; 452 #size-cells = <0>; 453 #interrupt-cells = <1>; 454 455 reg = <0x80 0x40>; 456 compatible = "aspeed,ast2400-i2c-bus"; 457 bus-frequency = <100000>; 458 interrupts = <1>; 459 interrupt-parent = <&i2c_ic>; 460 clocks = <&scu ASPEED_CLK_APB>; 461 status = "disabled"; 462 /* Does not need pinctrl properties */ 463 }; 464 465 i2c2: i2c-bus@c0 { 466 #address-cells = <1>; 467 #size-cells = <0>; 468 #interrupt-cells = <1>; 469 470 reg = <0xc0 0x40>; 471 compatible = "aspeed,ast2400-i2c-bus"; 472 bus-frequency = <100000>; 473 interrupts = <2>; 474 interrupt-parent = <&i2c_ic>; 475 clocks = <&scu ASPEED_CLK_APB>; 476 pinctrl-names = "default"; 477 pinctrl-0 = <&pinctrl_i2c3_default>; 478 status = "disabled"; 479 }; 480 481 i2c3: i2c-bus@100 { 482 #address-cells = <1>; 483 #size-cells = <0>; 484 #interrupt-cells = <1>; 485 486 reg = <0x100 0x40>; 487 compatible = "aspeed,ast2400-i2c-bus"; 488 bus-frequency = <100000>; 489 interrupts = <3>; 490 interrupt-parent = <&i2c_ic>; 491 clocks = <&scu ASPEED_CLK_APB>; 492 pinctrl-names = "default"; 493 pinctrl-0 = <&pinctrl_i2c4_default>; 494 status = "disabled"; 495 }; 496 497 i2c4: i2c-bus@140 { 498 #address-cells = <1>; 499 #size-cells = <0>; 500 #interrupt-cells = <1>; 501 502 reg = <0x140 0x40>; 503 compatible = "aspeed,ast2400-i2c-bus"; 504 bus-frequency = <100000>; 505 interrupts = <4>; 506 interrupt-parent = <&i2c_ic>; 507 clocks = <&scu ASPEED_CLK_APB>; 508 pinctrl-names = "default"; 509 pinctrl-0 = <&pinctrl_i2c5_default>; 510 status = "disabled"; 511 }; 512 513 i2c5: i2c-bus@180 { 514 #address-cells = <1>; 515 #size-cells = <0>; 516 #interrupt-cells = <1>; 517 518 reg = <0x180 0x40>; 519 compatible = "aspeed,ast2400-i2c-bus"; 520 bus-frequency = <100000>; 521 interrupts = <5>; 522 interrupt-parent = <&i2c_ic>; 523 clocks = <&scu ASPEED_CLK_APB>; 524 pinctrl-names = "default"; 525 pinctrl-0 = <&pinctrl_i2c6_default>; 526 status = "disabled"; 527 }; 528 529 i2c6: i2c-bus@1c0 { 530 #address-cells = <1>; 531 #size-cells = <0>; 532 #interrupt-cells = <1>; 533 534 reg = <0x1c0 0x40>; 535 compatible = "aspeed,ast2400-i2c-bus"; 536 bus-frequency = <100000>; 537 interrupts = <6>; 538 interrupt-parent = <&i2c_ic>; 539 clocks = <&scu ASPEED_CLK_APB>; 540 pinctrl-names = "default"; 541 pinctrl-0 = <&pinctrl_i2c7_default>; 542 status = "disabled"; 543 }; 544 545 i2c7: i2c-bus@300 { 546 #address-cells = <1>; 547 #size-cells = <0>; 548 #interrupt-cells = <1>; 549 550 reg = <0x300 0x40>; 551 compatible = "aspeed,ast2400-i2c-bus"; 552 bus-frequency = <100000>; 553 interrupts = <7>; 554 interrupt-parent = <&i2c_ic>; 555 clocks = <&scu ASPEED_CLK_APB>; 556 pinctrl-names = "default"; 557 pinctrl-0 = <&pinctrl_i2c8_default>; 558 status = "disabled"; 559 }; 560 561 i2c8: i2c-bus@340 { 562 #address-cells = <1>; 563 #size-cells = <0>; 564 #interrupt-cells = <1>; 565 566 reg = <0x340 0x40>; 567 compatible = "aspeed,ast2400-i2c-bus"; 568 bus-frequency = <100000>; 569 interrupts = <8>; 570 interrupt-parent = <&i2c_ic>; 571 clocks = <&scu ASPEED_CLK_APB>; 572 pinctrl-names = "default"; 573 pinctrl-0 = <&pinctrl_i2c9_default>; 574 status = "disabled"; 575 }; 576 577 i2c9: i2c-bus@380 { 578 #address-cells = <1>; 579 #size-cells = <0>; 580 #interrupt-cells = <1>; 581 582 reg = <0x380 0x40>; 583 compatible = "aspeed,ast2400-i2c-bus"; 584 bus-frequency = <100000>; 585 interrupts = <9>; 586 interrupt-parent = <&i2c_ic>; 587 clocks = <&scu ASPEED_CLK_APB>; 588 pinctrl-names = "default"; 589 pinctrl-0 = <&pinctrl_i2c10_default>; 590 status = "disabled"; 591 }; 592 593 i2c10: i2c-bus@3c0 { 594 #address-cells = <1>; 595 #size-cells = <0>; 596 #interrupt-cells = <1>; 597 598 reg = <0x3c0 0x40>; 599 compatible = "aspeed,ast2400-i2c-bus"; 600 bus-frequency = <100000>; 601 interrupts = <10>; 602 interrupt-parent = <&i2c_ic>; 603 clocks = <&scu ASPEED_CLK_APB>; 604 pinctrl-names = "default"; 605 pinctrl-0 = <&pinctrl_i2c11_default>; 606 status = "disabled"; 607 }; 608 609 i2c11: i2c-bus@400 { 610 #address-cells = <1>; 611 #size-cells = <0>; 612 #interrupt-cells = <1>; 613 614 reg = <0x400 0x40>; 615 compatible = "aspeed,ast2400-i2c-bus"; 616 bus-frequency = <100000>; 617 interrupts = <11>; 618 interrupt-parent = <&i2c_ic>; 619 clocks = <&scu ASPEED_CLK_APB>; 620 pinctrl-names = "default"; 621 pinctrl-0 = <&pinctrl_i2c12_default>; 622 status = "disabled"; 623 }; 624 625 i2c12: i2c-bus@440 { 626 #address-cells = <1>; 627 #size-cells = <0>; 628 #interrupt-cells = <1>; 629 630 reg = <0x440 0x40>; 631 compatible = "aspeed,ast2400-i2c-bus"; 632 bus-frequency = <100000>; 633 interrupts = <12>; 634 interrupt-parent = <&i2c_ic>; 635 clocks = <&scu ASPEED_CLK_APB>; 636 pinctrl-names = "default"; 637 pinctrl-0 = <&pinctrl_i2c13_default>; 638 status = "disabled"; 639 }; 640 641 i2c13: i2c-bus@480 { 642 #address-cells = <1>; 643 #size-cells = <0>; 644 #interrupt-cells = <1>; 645 646 reg = <0x480 0x40>; 647 compatible = "aspeed,ast2400-i2c-bus"; 648 bus-frequency = <100000>; 649 interrupts = <13>; 650 interrupt-parent = <&i2c_ic>; 651 clocks = <&scu ASPEED_CLK_APB>; 652 pinctrl-names = "default"; 653 pinctrl-0 = <&pinctrl_i2c14_default>; 654 status = "disabled"; 655 }; 656}; 657 658&pinctrl { 659 pinctrl_acpi_default: acpi_default { 660 function = "ACPI"; 661 groups = "ACPI"; 662 }; 663 664 pinctrl_adc0_default: adc0_default { 665 function = "ADC0"; 666 groups = "ADC0"; 667 }; 668 669 pinctrl_adc1_default: adc1_default { 670 function = "ADC1"; 671 groups = "ADC1"; 672 }; 673 674 pinctrl_adc10_default: adc10_default { 675 function = "ADC10"; 676 groups = "ADC10"; 677 }; 678 679 pinctrl_adc11_default: adc11_default { 680 function = "ADC11"; 681 groups = "ADC11"; 682 }; 683 684 pinctrl_adc12_default: adc12_default { 685 function = "ADC12"; 686 groups = "ADC12"; 687 }; 688 689 pinctrl_adc13_default: adc13_default { 690 function = "ADC13"; 691 groups = "ADC13"; 692 }; 693 694 pinctrl_adc14_default: adc14_default { 695 function = "ADC14"; 696 groups = "ADC14"; 697 }; 698 699 pinctrl_adc15_default: adc15_default { 700 function = "ADC15"; 701 groups = "ADC15"; 702 }; 703 704 pinctrl_adc2_default: adc2_default { 705 function = "ADC2"; 706 groups = "ADC2"; 707 }; 708 709 pinctrl_adc3_default: adc3_default { 710 function = "ADC3"; 711 groups = "ADC3"; 712 }; 713 714 pinctrl_adc4_default: adc4_default { 715 function = "ADC4"; 716 groups = "ADC4"; 717 }; 718 719 pinctrl_adc5_default: adc5_default { 720 function = "ADC5"; 721 groups = "ADC5"; 722 }; 723 724 pinctrl_adc6_default: adc6_default { 725 function = "ADC6"; 726 groups = "ADC6"; 727 }; 728 729 pinctrl_adc7_default: adc7_default { 730 function = "ADC7"; 731 groups = "ADC7"; 732 }; 733 734 pinctrl_adc8_default: adc8_default { 735 function = "ADC8"; 736 groups = "ADC8"; 737 }; 738 739 pinctrl_adc9_default: adc9_default { 740 function = "ADC9"; 741 groups = "ADC9"; 742 }; 743 744 pinctrl_bmcint_default: bmcint_default { 745 function = "BMCINT"; 746 groups = "BMCINT"; 747 }; 748 749 pinctrl_ddcclk_default: ddcclk_default { 750 function = "DDCCLK"; 751 groups = "DDCCLK"; 752 }; 753 754 pinctrl_ddcdat_default: ddcdat_default { 755 function = "DDCDAT"; 756 groups = "DDCDAT"; 757 }; 758 759 pinctrl_espi_default: espi_default { 760 function = "ESPI"; 761 groups = "ESPI"; 762 }; 763 764 pinctrl_fwspics1_default: fwspics1_default { 765 function = "FWSPICS1"; 766 groups = "FWSPICS1"; 767 }; 768 769 pinctrl_fwspics2_default: fwspics2_default { 770 function = "FWSPICS2"; 771 groups = "FWSPICS2"; 772 }; 773 774 pinctrl_gpid0_default: gpid0_default { 775 function = "GPID0"; 776 groups = "GPID0"; 777 }; 778 779 pinctrl_gpid2_default: gpid2_default { 780 function = "GPID2"; 781 groups = "GPID2"; 782 }; 783 784 pinctrl_gpid4_default: gpid4_default { 785 function = "GPID4"; 786 groups = "GPID4"; 787 }; 788 789 pinctrl_gpid6_default: gpid6_default { 790 function = "GPID6"; 791 groups = "GPID6"; 792 }; 793 794 pinctrl_gpie0_default: gpie0_default { 795 function = "GPIE0"; 796 groups = "GPIE0"; 797 }; 798 799 pinctrl_gpie2_default: gpie2_default { 800 function = "GPIE2"; 801 groups = "GPIE2"; 802 }; 803 804 pinctrl_gpie4_default: gpie4_default { 805 function = "GPIE4"; 806 groups = "GPIE4"; 807 }; 808 809 pinctrl_gpie6_default: gpie6_default { 810 function = "GPIE6"; 811 groups = "GPIE6"; 812 }; 813 814 pinctrl_i2c10_default: i2c10_default { 815 function = "I2C10"; 816 groups = "I2C10"; 817 }; 818 819 pinctrl_i2c11_default: i2c11_default { 820 function = "I2C11"; 821 groups = "I2C11"; 822 }; 823 824 pinctrl_i2c12_default: i2c12_default { 825 function = "I2C12"; 826 groups = "I2C12"; 827 }; 828 829 pinctrl_i2c13_default: i2c13_default { 830 function = "I2C13"; 831 groups = "I2C13"; 832 }; 833 834 pinctrl_i2c14_default: i2c14_default { 835 function = "I2C14"; 836 groups = "I2C14"; 837 }; 838 839 pinctrl_i2c3_default: i2c3_default { 840 function = "I2C3"; 841 groups = "I2C3"; 842 }; 843 844 pinctrl_i2c4_default: i2c4_default { 845 function = "I2C4"; 846 groups = "I2C4"; 847 }; 848 849 pinctrl_i2c5_default: i2c5_default { 850 function = "I2C5"; 851 groups = "I2C5"; 852 }; 853 854 pinctrl_i2c6_default: i2c6_default { 855 function = "I2C6"; 856 groups = "I2C6"; 857 }; 858 859 pinctrl_i2c7_default: i2c7_default { 860 function = "I2C7"; 861 groups = "I2C7"; 862 }; 863 864 pinctrl_i2c8_default: i2c8_default { 865 function = "I2C8"; 866 groups = "I2C8"; 867 }; 868 869 pinctrl_i2c9_default: i2c9_default { 870 function = "I2C9"; 871 groups = "I2C9"; 872 }; 873 874 pinctrl_lad0_default: lad0_default { 875 function = "LAD0"; 876 groups = "LAD0"; 877 }; 878 879 pinctrl_lad1_default: lad1_default { 880 function = "LAD1"; 881 groups = "LAD1"; 882 }; 883 884 pinctrl_lad2_default: lad2_default { 885 function = "LAD2"; 886 groups = "LAD2"; 887 }; 888 889 pinctrl_lad3_default: lad3_default { 890 function = "LAD3"; 891 groups = "LAD3"; 892 }; 893 894 pinctrl_lclk_default: lclk_default { 895 function = "LCLK"; 896 groups = "LCLK"; 897 }; 898 899 pinctrl_lframe_default: lframe_default { 900 function = "LFRAME"; 901 groups = "LFRAME"; 902 }; 903 904 pinctrl_lpchc_default: lpchc_default { 905 function = "LPCHC"; 906 groups = "LPCHC"; 907 }; 908 909 pinctrl_lpcpd_default: lpcpd_default { 910 function = "LPCPD"; 911 groups = "LPCPD"; 912 }; 913 914 pinctrl_lpcplus_default: lpcplus_default { 915 function = "LPCPLUS"; 916 groups = "LPCPLUS"; 917 }; 918 919 pinctrl_lpcpme_default: lpcpme_default { 920 function = "LPCPME"; 921 groups = "LPCPME"; 922 }; 923 924 pinctrl_lpcrst_default: lpcrst_default { 925 function = "LPCRST"; 926 groups = "LPCRST"; 927 }; 928 929 pinctrl_lpcsmi_default: lpcsmi_default { 930 function = "LPCSMI"; 931 groups = "LPCSMI"; 932 }; 933 934 pinctrl_lsirq_default: lsirq_default { 935 function = "LSIRQ"; 936 groups = "LSIRQ"; 937 }; 938 939 pinctrl_mac1link_default: mac1link_default { 940 function = "MAC1LINK"; 941 groups = "MAC1LINK"; 942 }; 943 944 pinctrl_mac2link_default: mac2link_default { 945 function = "MAC2LINK"; 946 groups = "MAC2LINK"; 947 }; 948 949 pinctrl_mdio1_default: mdio1_default { 950 function = "MDIO1"; 951 groups = "MDIO1"; 952 }; 953 954 pinctrl_mdio2_default: mdio2_default { 955 function = "MDIO2"; 956 groups = "MDIO2"; 957 }; 958 959 pinctrl_ncts1_default: ncts1_default { 960 function = "NCTS1"; 961 groups = "NCTS1"; 962 }; 963 964 pinctrl_ncts2_default: ncts2_default { 965 function = "NCTS2"; 966 groups = "NCTS2"; 967 }; 968 969 pinctrl_ncts3_default: ncts3_default { 970 function = "NCTS3"; 971 groups = "NCTS3"; 972 }; 973 974 pinctrl_ncts4_default: ncts4_default { 975 function = "NCTS4"; 976 groups = "NCTS4"; 977 }; 978 979 pinctrl_ndcd1_default: ndcd1_default { 980 function = "NDCD1"; 981 groups = "NDCD1"; 982 }; 983 984 pinctrl_ndcd2_default: ndcd2_default { 985 function = "NDCD2"; 986 groups = "NDCD2"; 987 }; 988 989 pinctrl_ndcd3_default: ndcd3_default { 990 function = "NDCD3"; 991 groups = "NDCD3"; 992 }; 993 994 pinctrl_ndcd4_default: ndcd4_default { 995 function = "NDCD4"; 996 groups = "NDCD4"; 997 }; 998 999 pinctrl_ndsr1_default: ndsr1_default { 1000 function = "NDSR1"; 1001 groups = "NDSR1"; 1002 }; 1003 1004 pinctrl_ndsr2_default: ndsr2_default { 1005 function = "NDSR2"; 1006 groups = "NDSR2"; 1007 }; 1008 1009 pinctrl_ndsr3_default: ndsr3_default { 1010 function = "NDSR3"; 1011 groups = "NDSR3"; 1012 }; 1013 1014 pinctrl_ndsr4_default: ndsr4_default { 1015 function = "NDSR4"; 1016 groups = "NDSR4"; 1017 }; 1018 1019 pinctrl_ndtr1_default: ndtr1_default { 1020 function = "NDTR1"; 1021 groups = "NDTR1"; 1022 }; 1023 1024 pinctrl_ndtr2_default: ndtr2_default { 1025 function = "NDTR2"; 1026 groups = "NDTR2"; 1027 }; 1028 1029 pinctrl_ndtr3_default: ndtr3_default { 1030 function = "NDTR3"; 1031 groups = "NDTR3"; 1032 }; 1033 1034 pinctrl_ndtr4_default: ndtr4_default { 1035 function = "NDTR4"; 1036 groups = "NDTR4"; 1037 }; 1038 1039 pinctrl_nri1_default: nri1_default { 1040 function = "NRI1"; 1041 groups = "NRI1"; 1042 }; 1043 1044 pinctrl_nri2_default: nri2_default { 1045 function = "NRI2"; 1046 groups = "NRI2"; 1047 }; 1048 1049 pinctrl_nri3_default: nri3_default { 1050 function = "NRI3"; 1051 groups = "NRI3"; 1052 }; 1053 1054 pinctrl_nri4_default: nri4_default { 1055 function = "NRI4"; 1056 groups = "NRI4"; 1057 }; 1058 1059 pinctrl_nrts1_default: nrts1_default { 1060 function = "NRTS1"; 1061 groups = "NRTS1"; 1062 }; 1063 1064 pinctrl_nrts2_default: nrts2_default { 1065 function = "NRTS2"; 1066 groups = "NRTS2"; 1067 }; 1068 1069 pinctrl_nrts3_default: nrts3_default { 1070 function = "NRTS3"; 1071 groups = "NRTS3"; 1072 }; 1073 1074 pinctrl_nrts4_default: nrts4_default { 1075 function = "NRTS4"; 1076 groups = "NRTS4"; 1077 }; 1078 1079 pinctrl_oscclk_default: oscclk_default { 1080 function = "OSCCLK"; 1081 groups = "OSCCLK"; 1082 }; 1083 1084 pinctrl_pewake_default: pewake_default { 1085 function = "PEWAKE"; 1086 groups = "PEWAKE"; 1087 }; 1088 1089 pinctrl_pnor_default: pnor_default { 1090 function = "PNOR"; 1091 groups = "PNOR"; 1092 }; 1093 1094 pinctrl_pwm0_default: pwm0_default { 1095 function = "PWM0"; 1096 groups = "PWM0"; 1097 }; 1098 1099 pinctrl_pwm1_default: pwm1_default { 1100 function = "PWM1"; 1101 groups = "PWM1"; 1102 }; 1103 1104 pinctrl_pwm2_default: pwm2_default { 1105 function = "PWM2"; 1106 groups = "PWM2"; 1107 }; 1108 1109 pinctrl_pwm3_default: pwm3_default { 1110 function = "PWM3"; 1111 groups = "PWM3"; 1112 }; 1113 1114 pinctrl_pwm4_default: pwm4_default { 1115 function = "PWM4"; 1116 groups = "PWM4"; 1117 }; 1118 1119 pinctrl_pwm5_default: pwm5_default { 1120 function = "PWM5"; 1121 groups = "PWM5"; 1122 }; 1123 1124 pinctrl_pwm6_default: pwm6_default { 1125 function = "PWM6"; 1126 groups = "PWM6"; 1127 }; 1128 1129 pinctrl_pwm7_default: pwm7_default { 1130 function = "PWM7"; 1131 groups = "PWM7"; 1132 }; 1133 1134 pinctrl_rgmii1_default: rgmii1_default { 1135 function = "RGMII1"; 1136 groups = "RGMII1"; 1137 }; 1138 1139 pinctrl_rgmii2_default: rgmii2_default { 1140 function = "RGMII2"; 1141 groups = "RGMII2"; 1142 }; 1143 1144 pinctrl_rmii1_default: rmii1_default { 1145 function = "RMII1"; 1146 groups = "RMII1"; 1147 }; 1148 1149 pinctrl_rmii2_default: rmii2_default { 1150 function = "RMII2"; 1151 groups = "RMII2"; 1152 }; 1153 1154 pinctrl_rxd1_default: rxd1_default { 1155 function = "RXD1"; 1156 groups = "RXD1"; 1157 }; 1158 1159 pinctrl_rxd2_default: rxd2_default { 1160 function = "RXD2"; 1161 groups = "RXD2"; 1162 }; 1163 1164 pinctrl_rxd3_default: rxd3_default { 1165 function = "RXD3"; 1166 groups = "RXD3"; 1167 }; 1168 1169 pinctrl_rxd4_default: rxd4_default { 1170 function = "RXD4"; 1171 groups = "RXD4"; 1172 }; 1173 1174 pinctrl_salt1_default: salt1_default { 1175 function = "SALT1"; 1176 groups = "SALT1"; 1177 }; 1178 1179 pinctrl_salt10_default: salt10_default { 1180 function = "SALT10"; 1181 groups = "SALT10"; 1182 }; 1183 1184 pinctrl_salt11_default: salt11_default { 1185 function = "SALT11"; 1186 groups = "SALT11"; 1187 }; 1188 1189 pinctrl_salt12_default: salt12_default { 1190 function = "SALT12"; 1191 groups = "SALT12"; 1192 }; 1193 1194 pinctrl_salt13_default: salt13_default { 1195 function = "SALT13"; 1196 groups = "SALT13"; 1197 }; 1198 1199 pinctrl_salt14_default: salt14_default { 1200 function = "SALT14"; 1201 groups = "SALT14"; 1202 }; 1203 1204 pinctrl_salt2_default: salt2_default { 1205 function = "SALT2"; 1206 groups = "SALT2"; 1207 }; 1208 1209 pinctrl_salt3_default: salt3_default { 1210 function = "SALT3"; 1211 groups = "SALT3"; 1212 }; 1213 1214 pinctrl_salt4_default: salt4_default { 1215 function = "SALT4"; 1216 groups = "SALT4"; 1217 }; 1218 1219 pinctrl_salt5_default: salt5_default { 1220 function = "SALT5"; 1221 groups = "SALT5"; 1222 }; 1223 1224 pinctrl_salt6_default: salt6_default { 1225 function = "SALT6"; 1226 groups = "SALT6"; 1227 }; 1228 1229 pinctrl_salt7_default: salt7_default { 1230 function = "SALT7"; 1231 groups = "SALT7"; 1232 }; 1233 1234 pinctrl_salt8_default: salt8_default { 1235 function = "SALT8"; 1236 groups = "SALT8"; 1237 }; 1238 1239 pinctrl_salt9_default: salt9_default { 1240 function = "SALT9"; 1241 groups = "SALT9"; 1242 }; 1243 1244 pinctrl_scl1_default: scl1_default { 1245 function = "SCL1"; 1246 groups = "SCL1"; 1247 }; 1248 1249 pinctrl_scl2_default: scl2_default { 1250 function = "SCL2"; 1251 groups = "SCL2"; 1252 }; 1253 1254 pinctrl_sd1_default: sd1_default { 1255 function = "SD1"; 1256 groups = "SD1"; 1257 }; 1258 1259 pinctrl_sd2_default: sd2_default { 1260 function = "SD2"; 1261 groups = "SD2"; 1262 }; 1263 1264 pinctrl_sda1_default: sda1_default { 1265 function = "SDA1"; 1266 groups = "SDA1"; 1267 }; 1268 1269 pinctrl_sda2_default: sda2_default { 1270 function = "SDA2"; 1271 groups = "SDA2"; 1272 }; 1273 1274 pinctrl_sgps1_default: sgps1_default { 1275 function = "SGPS1"; 1276 groups = "SGPS1"; 1277 }; 1278 1279 pinctrl_sgps2_default: sgps2_default { 1280 function = "SGPS2"; 1281 groups = "SGPS2"; 1282 }; 1283 1284 pinctrl_sioonctrl_default: sioonctrl_default { 1285 function = "SIOONCTRL"; 1286 groups = "SIOONCTRL"; 1287 }; 1288 1289 pinctrl_siopbi_default: siopbi_default { 1290 function = "SIOPBI"; 1291 groups = "SIOPBI"; 1292 }; 1293 1294 pinctrl_siopbo_default: siopbo_default { 1295 function = "SIOPBO"; 1296 groups = "SIOPBO"; 1297 }; 1298 1299 pinctrl_siopwreq_default: siopwreq_default { 1300 function = "SIOPWREQ"; 1301 groups = "SIOPWREQ"; 1302 }; 1303 1304 pinctrl_siopwrgd_default: siopwrgd_default { 1305 function = "SIOPWRGD"; 1306 groups = "SIOPWRGD"; 1307 }; 1308 1309 pinctrl_sios3_default: sios3_default { 1310 function = "SIOS3"; 1311 groups = "SIOS3"; 1312 }; 1313 1314 pinctrl_sios5_default: sios5_default { 1315 function = "SIOS5"; 1316 groups = "SIOS5"; 1317 }; 1318 1319 pinctrl_siosci_default: siosci_default { 1320 function = "SIOSCI"; 1321 groups = "SIOSCI"; 1322 }; 1323 1324 pinctrl_spi1_default: spi1_default { 1325 function = "SPI1"; 1326 groups = "SPI1"; 1327 }; 1328 1329 pinctrl_spi1cs1_default: spi1cs1_default { 1330 function = "SPI1CS1"; 1331 groups = "SPI1CS1"; 1332 }; 1333 1334 pinctrl_spi1debug_default: spi1debug_default { 1335 function = "SPI1DEBUG"; 1336 groups = "SPI1DEBUG"; 1337 }; 1338 1339 pinctrl_spi1passthru_default: spi1passthru_default { 1340 function = "SPI1PASSTHRU"; 1341 groups = "SPI1PASSTHRU"; 1342 }; 1343 1344 pinctrl_spi2ck_default: spi2ck_default { 1345 function = "SPI2CK"; 1346 groups = "SPI2CK"; 1347 }; 1348 1349 pinctrl_spi2cs0_default: spi2cs0_default { 1350 function = "SPI2CS0"; 1351 groups = "SPI2CS0"; 1352 }; 1353 1354 pinctrl_spi2cs1_default: spi2cs1_default { 1355 function = "SPI2CS1"; 1356 groups = "SPI2CS1"; 1357 }; 1358 1359 pinctrl_spi2miso_default: spi2miso_default { 1360 function = "SPI2MISO"; 1361 groups = "SPI2MISO"; 1362 }; 1363 1364 pinctrl_spi2mosi_default: spi2mosi_default { 1365 function = "SPI2MOSI"; 1366 groups = "SPI2MOSI"; 1367 }; 1368 1369 pinctrl_timer3_default: timer3_default { 1370 function = "TIMER3"; 1371 groups = "TIMER3"; 1372 }; 1373 1374 pinctrl_timer4_default: timer4_default { 1375 function = "TIMER4"; 1376 groups = "TIMER4"; 1377 }; 1378 1379 pinctrl_timer5_default: timer5_default { 1380 function = "TIMER5"; 1381 groups = "TIMER5"; 1382 }; 1383 1384 pinctrl_timer6_default: timer6_default { 1385 function = "TIMER6"; 1386 groups = "TIMER6"; 1387 }; 1388 1389 pinctrl_timer7_default: timer7_default { 1390 function = "TIMER7"; 1391 groups = "TIMER7"; 1392 }; 1393 1394 pinctrl_timer8_default: timer8_default { 1395 function = "TIMER8"; 1396 groups = "TIMER8"; 1397 }; 1398 1399 pinctrl_txd1_default: txd1_default { 1400 function = "TXD1"; 1401 groups = "TXD1"; 1402 }; 1403 1404 pinctrl_txd2_default: txd2_default { 1405 function = "TXD2"; 1406 groups = "TXD2"; 1407 }; 1408 1409 pinctrl_txd3_default: txd3_default { 1410 function = "TXD3"; 1411 groups = "TXD3"; 1412 }; 1413 1414 pinctrl_txd4_default: txd4_default { 1415 function = "TXD4"; 1416 groups = "TXD4"; 1417 }; 1418 1419 pinctrl_uart6_default: uart6_default { 1420 function = "UART6"; 1421 groups = "UART6"; 1422 }; 1423 1424 pinctrl_usbcki_default: usbcki_default { 1425 function = "USBCKI"; 1426 groups = "USBCKI"; 1427 }; 1428 1429 pinctrl_usb2ah_default: usb2ah_default { 1430 function = "USB2AH"; 1431 groups = "USB2AH"; 1432 }; 1433 1434 pinctrl_usb11bhid_default: usb11bhid_default { 1435 function = "USB11BHID"; 1436 groups = "USB11BHID"; 1437 }; 1438 1439 pinctrl_usb2bh_default: usb2bh_default { 1440 function = "USB2BH"; 1441 groups = "USB2BH"; 1442 }; 1443 1444 pinctrl_vgabiosrom_default: vgabiosrom_default { 1445 function = "VGABIOSROM"; 1446 groups = "VGABIOSROM"; 1447 }; 1448 1449 pinctrl_vgahs_default: vgahs_default { 1450 function = "VGAHS"; 1451 groups = "VGAHS"; 1452 }; 1453 1454 pinctrl_vgavs_default: vgavs_default { 1455 function = "VGAVS"; 1456 groups = "VGAVS"; 1457 }; 1458 1459 pinctrl_vpi24_default: vpi24_default { 1460 function = "VPI24"; 1461 groups = "VPI24"; 1462 }; 1463 1464 pinctrl_vpo_default: vpo_default { 1465 function = "VPO"; 1466 groups = "VPO"; 1467 }; 1468 1469 pinctrl_wdtrst1_default: wdtrst1_default { 1470 function = "WDTRST1"; 1471 groups = "WDTRST1"; 1472 }; 1473 1474 pinctrl_wdtrst2_default: wdtrst2_default { 1475 function = "WDTRST2"; 1476 groups = "WDTRST2"; 1477 }; 1478}; 1479