1/* 2 * Device Tree Include file for Marvell Armada XP family SoC 3 * 4 * Copyright (C) 2012 Marvell 5 * 6 * Lior Amsalem <alior@marvell.com> 7 * Gregory CLEMENT <gregory.clement@free-electrons.com> 8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 9 * Ben Dooks <ben.dooks@codethink.co.uk> 10 * 11 * This file is dual-licensed: you can use it either under the terms 12 * of the GPL or the X11 license, at your option. Note that this dual 13 * licensing only applies to this file, and not this project as a 14 * whole. 15 * 16 * a) This file is free software; you can redistribute it and/or 17 * modify it under the terms of the GNU General Public License as 18 * published by the Free Software Foundation; either version 2 of the 19 * License, or (at your option) any later version. 20 * 21 * This file is distributed in the hope that it will be useful 22 * but WITHOUT ANY WARRANTY; without even the implied warranty of 23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 24 * GNU General Public License for more details. 25 * 26 * Or, alternatively 27 * 28 * b) Permission is hereby granted, free of charge, to any person 29 * obtaining a copy of this software and associated documentation 30 * files (the "Software"), to deal in the Software without 31 * restriction, including without limitation the rights to use 32 * copy, modify, merge, publish, distribute, sublicense, and/or 33 * sell copies of the Software, and to permit persons to whom the 34 * Software is furnished to do so, subject to the following 35 * conditions: 36 * 37 * The above copyright notice and this permission notice shall be 38 * included in all copies or substantial portions of the Software. 39 * 40 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND 41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY 45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 47 * OTHER DEALINGS IN THE SOFTWARE. 48 * 49 * Contains definitions specific to the Armada XP SoC that are not 50 * common to all Armada SoCs. 51 */ 52 53#include "armada-370-xp.dtsi" 54 55/ { 56 model = "Marvell Armada XP family SoC"; 57 compatible = "marvell,armadaxp", "marvell,armada-370-xp"; 58 59 aliases { 60 serial2 = &uart2; 61 serial3 = &uart3; 62 }; 63 64 soc { 65 compatible = "marvell,armadaxp-mbus", "simple-bus"; 66 67 bootrom { 68 compatible = "marvell,bootrom"; 69 reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>; 70 }; 71 72 internal-regs { 73 sdramc@1400 { 74 compatible = "marvell,armada-xp-sdram-controller"; 75 reg = <0x1400 0x500>; 76 }; 77 78 L2: l2-cache { 79 compatible = "marvell,aurora-system-cache"; 80 reg = <0x08000 0x1000>; 81 cache-id-part = <0x100>; 82 cache-level = <2>; 83 cache-unified; 84 wt-override; 85 }; 86 87 spi0: spi@10600 { 88 compatible = "marvell,armada-xp-spi", 89 "marvell,orion-spi"; 90 pinctrl-0 = <&spi0_pins>; 91 pinctrl-names = "default"; 92 }; 93 94 spi1: spi@10680 { 95 compatible = "marvell,armada-xp-spi", 96 "marvell,orion-spi"; 97 }; 98 99 100 i2c0: i2c@11000 { 101 compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; 102 reg = <0x11000 0x100>; 103 }; 104 105 i2c1: i2c@11100 { 106 compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; 107 reg = <0x11100 0x100>; 108 }; 109 110 uart2: serial@12200 { 111 compatible = "snps,dw-apb-uart"; 112 pinctrl-0 = <&uart2_pins>; 113 pinctrl-names = "default"; 114 reg = <0x12200 0x100>; 115 reg-shift = <2>; 116 interrupts = <43>; 117 reg-io-width = <1>; 118 clocks = <&coreclk 0>; 119 status = "disabled"; 120 }; 121 122 uart3: serial@12300 { 123 compatible = "snps,dw-apb-uart"; 124 pinctrl-0 = <&uart3_pins>; 125 pinctrl-names = "default"; 126 reg = <0x12300 0x100>; 127 reg-shift = <2>; 128 interrupts = <44>; 129 reg-io-width = <1>; 130 clocks = <&coreclk 0>; 131 status = "disabled"; 132 }; 133 134 system-controller@18200 { 135 compatible = "marvell,armada-370-xp-system-controller"; 136 reg = <0x18200 0x500>; 137 }; 138 139 gateclk: clock-gating-control@18220 { 140 compatible = "marvell,armada-xp-gating-clock"; 141 reg = <0x18220 0x4>; 142 clocks = <&coreclk 0>; 143 #clock-cells = <1>; 144 }; 145 146 coreclk: mvebu-sar@18230 { 147 compatible = "marvell,armada-xp-core-clock"; 148 reg = <0x18230 0x08>; 149 #clock-cells = <1>; 150 }; 151 152 thermal@182b0 { 153 compatible = "marvell,armadaxp-thermal"; 154 reg = <0x182b0 0x4 155 0x184d0 0x4>; 156 status = "okay"; 157 }; 158 159 cpuclk: clock-complex@18700 { 160 #clock-cells = <1>; 161 compatible = "marvell,armada-xp-cpu-clock"; 162 reg = <0x18700 0x24>, <0x1c054 0x10>; 163 clocks = <&coreclk 1>; 164 }; 165 166 interrupt-controller@20a00 { 167 reg = <0x20a00 0x2d0>, <0x21070 0x58>; 168 }; 169 170 timer@20300 { 171 compatible = "marvell,armada-xp-timer"; 172 clocks = <&coreclk 2>, <&refclk>; 173 clock-names = "nbclk", "fixed"; 174 }; 175 176 watchdog@20300 { 177 compatible = "marvell,armada-xp-wdt"; 178 clocks = <&coreclk 2>, <&refclk>; 179 clock-names = "nbclk", "fixed"; 180 }; 181 182 cpurst@20800 { 183 compatible = "marvell,armada-370-cpu-reset"; 184 reg = <0x20800 0x20>; 185 }; 186 187 eth2: ethernet@30000 { 188 compatible = "marvell,armada-xp-neta"; 189 reg = <0x30000 0x4000>; 190 interrupts = <12>; 191 clocks = <&gateclk 2>; 192 status = "disabled"; 193 }; 194 195 usb@50000 { 196 clocks = <&gateclk 18>; 197 }; 198 199 usb@51000 { 200 clocks = <&gateclk 19>; 201 }; 202 203 usb@52000 { 204 compatible = "marvell,orion-ehci"; 205 reg = <0x52000 0x500>; 206 interrupts = <47>; 207 clocks = <&gateclk 20>; 208 status = "disabled"; 209 }; 210 211 xor@60900 { 212 compatible = "marvell,orion-xor"; 213 reg = <0x60900 0x100 214 0x60b00 0x100>; 215 clocks = <&gateclk 22>; 216 status = "okay"; 217 218 xor10 { 219 interrupts = <51>; 220 dmacap,memcpy; 221 dmacap,xor; 222 }; 223 xor11 { 224 interrupts = <52>; 225 dmacap,memcpy; 226 dmacap,xor; 227 dmacap,memset; 228 }; 229 }; 230 231 ethernet@70000 { 232 compatible = "marvell,armada-xp-neta"; 233 }; 234 235 ethernet@74000 { 236 compatible = "marvell,armada-xp-neta"; 237 }; 238 239 xor@f0900 { 240 compatible = "marvell,orion-xor"; 241 reg = <0xF0900 0x100 242 0xF0B00 0x100>; 243 clocks = <&gateclk 28>; 244 status = "okay"; 245 246 xor00 { 247 interrupts = <94>; 248 dmacap,memcpy; 249 dmacap,xor; 250 }; 251 xor01 { 252 interrupts = <95>; 253 dmacap,memcpy; 254 dmacap,xor; 255 dmacap,memset; 256 }; 257 }; 258 }; 259 }; 260 261 clocks { 262 /* 25 MHz reference crystal */ 263 refclk: oscillator { 264 compatible = "fixed-clock"; 265 #clock-cells = <0>; 266 clock-frequency = <25000000>; 267 }; 268 }; 269}; 270 271&pinctrl { 272 ge0_gmii_pins: ge0-gmii-pins { 273 marvell,pins = 274 "mpp0", "mpp1", "mpp2", "mpp3", 275 "mpp4", "mpp5", "mpp6", "mpp7", 276 "mpp8", "mpp9", "mpp10", "mpp11", 277 "mpp12", "mpp13", "mpp14", "mpp15", 278 "mpp16", "mpp17", "mpp18", "mpp19", 279 "mpp20", "mpp21", "mpp22", "mpp23"; 280 marvell,function = "ge0"; 281 }; 282 283 ge0_rgmii_pins: ge0-rgmii-pins { 284 marvell,pins = 285 "mpp0", "mpp1", "mpp2", "mpp3", 286 "mpp4", "mpp5", "mpp6", "mpp7", 287 "mpp8", "mpp9", "mpp10", "mpp11"; 288 marvell,function = "ge0"; 289 }; 290 291 ge1_rgmii_pins: ge1-rgmii-pins { 292 marvell,pins = 293 "mpp12", "mpp13", "mpp14", "mpp15", 294 "mpp16", "mpp17", "mpp18", "mpp19", 295 "mpp20", "mpp21", "mpp22", "mpp23"; 296 marvell,function = "ge1"; 297 }; 298 299 sdio_pins: sdio-pins { 300 marvell,pins = "mpp30", "mpp31", "mpp32", 301 "mpp33", "mpp34", "mpp35"; 302 marvell,function = "sd0"; 303 }; 304 305 spi0_pins: spi0-pins { 306 marvell,pins = "mpp36", "mpp37", 307 "mpp38", "mpp39"; 308 marvell,function = "spi0"; 309 }; 310 311 uart2_pins: uart2-pins { 312 marvell,pins = "mpp42", "mpp43"; 313 marvell,function = "uart2"; 314 }; 315 316 uart3_pins: uart3-pins { 317 marvell,pins = "mpp44", "mpp45"; 318 marvell,function = "uart3"; 319 }; 320}; 321