1*b20c38a9SStefan Roese/* 2*b20c38a9SStefan Roese * Device Tree file for Marvell Armada XP theadorable board 3*b20c38a9SStefan Roese * 4*b20c38a9SStefan Roese * Copyright (C) 2013-2014 Marvell 5*b20c38a9SStefan Roese * 6*b20c38a9SStefan Roese * Lior Amsalem <alior@marvell.com> 7*b20c38a9SStefan Roese * Gregory CLEMENT <gregory.clement@free-electrons.com> 8*b20c38a9SStefan Roese * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 9*b20c38a9SStefan Roese * 10*b20c38a9SStefan Roese * This file is dual-licensed: you can use it either under the terms 11*b20c38a9SStefan Roese * of the GPL or the X11 license, at your option. Note that this dual 12*b20c38a9SStefan Roese * licensing only applies to this file, and not this project as a 13*b20c38a9SStefan Roese * whole. 14*b20c38a9SStefan Roese * 15*b20c38a9SStefan Roese * a) This file is free software; you can redistribute it and/or 16*b20c38a9SStefan Roese * modify it under the terms of the GNU General Public License as 17*b20c38a9SStefan Roese * published by the Free Software Foundation; either version 2 of the 18*b20c38a9SStefan Roese * License, or (at your option) any later version. 19*b20c38a9SStefan Roese * 20*b20c38a9SStefan Roese * This file is distributed in the hope that it will be useful 21*b20c38a9SStefan Roese * but WITHOUT ANY WARRANTY; without even the implied warranty of 22*b20c38a9SStefan Roese * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23*b20c38a9SStefan Roese * GNU General Public License for more details. 24*b20c38a9SStefan Roese * 25*b20c38a9SStefan Roese * Or, alternatively 26*b20c38a9SStefan Roese * 27*b20c38a9SStefan Roese * b) Permission is hereby granted, free of charge, to any person 28*b20c38a9SStefan Roese * obtaining a copy of this software and associated documentation 29*b20c38a9SStefan Roese * files (the "Software"), to deal in the Software without 30*b20c38a9SStefan Roese * restriction, including without limitation the rights to use 31*b20c38a9SStefan Roese * copy, modify, merge, publish, distribute, sublicense, and/or 32*b20c38a9SStefan Roese * sell copies of the Software, and to permit persons to whom the 33*b20c38a9SStefan Roese * Software is furnished to do so, subject to the following 34*b20c38a9SStefan Roese * conditions: 35*b20c38a9SStefan Roese * 36*b20c38a9SStefan Roese * The above copyright notice and this permission notice shall be 37*b20c38a9SStefan Roese * included in all copies or substantial portions of the Software. 38*b20c38a9SStefan Roese * 39*b20c38a9SStefan Roese * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND 40*b20c38a9SStefan Roese * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 41*b20c38a9SStefan Roese * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 42*b20c38a9SStefan Roese * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 43*b20c38a9SStefan Roese * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY 44*b20c38a9SStefan Roese * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 45*b20c38a9SStefan Roese * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 46*b20c38a9SStefan Roese * OTHER DEALINGS IN THE SOFTWARE. 47*b20c38a9SStefan Roese * 48*b20c38a9SStefan Roese * Note: this Device Tree assumes that the bootloader has remapped the 49*b20c38a9SStefan Roese * internal registers to 0xf1000000 (instead of the default 50*b20c38a9SStefan Roese * 0xd0000000). The 0xf1000000 is the default used by the recent, 51*b20c38a9SStefan Roese * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier 52*b20c38a9SStefan Roese * boards were delivered with an older version of the bootloader that 53*b20c38a9SStefan Roese * left internal registers mapped at 0xd0000000. If you are in this 54*b20c38a9SStefan Roese * situation, you should either update your bootloader (preferred 55*b20c38a9SStefan Roese * solution) or the below Device Tree should be adjusted. 56*b20c38a9SStefan Roese */ 57*b20c38a9SStefan Roese 58*b20c38a9SStefan Roese/dts-v1/; 59*b20c38a9SStefan Roese#include <dt-bindings/gpio/gpio.h> 60*b20c38a9SStefan Roese#include "armada-xp-mv78260.dtsi" 61*b20c38a9SStefan Roese 62*b20c38a9SStefan Roese/ { 63*b20c38a9SStefan Roese model = "Marvell Armada XP theadorable"; 64*b20c38a9SStefan Roese compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp"; 65*b20c38a9SStefan Roese 66*b20c38a9SStefan Roese chosen { 67*b20c38a9SStefan Roese stdout-path = "serial0:115200n8"; 68*b20c38a9SStefan Roese }; 69*b20c38a9SStefan Roese 70*b20c38a9SStefan Roese aliases { 71*b20c38a9SStefan Roese spi0 = &spi0; 72*b20c38a9SStefan Roese ethernet0 = ð0; 73*b20c38a9SStefan Roese }; 74*b20c38a9SStefan Roese 75*b20c38a9SStefan Roese memory { 76*b20c38a9SStefan Roese device_type = "memory"; 77*b20c38a9SStefan Roese reg = <0x00000000 0x00000000 0x00000000 0x80000000>; 78*b20c38a9SStefan Roese }; 79*b20c38a9SStefan Roese 80*b20c38a9SStefan Roese soc { 81*b20c38a9SStefan Roese ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000 82*b20c38a9SStefan Roese MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000 83*b20c38a9SStefan Roese MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>; 84*b20c38a9SStefan Roese 85*b20c38a9SStefan Roese internal-regs { 86*b20c38a9SStefan Roese serial@12000 { 87*b20c38a9SStefan Roese status = "okay"; 88*b20c38a9SStefan Roese u-boot,dm-pre-reloc; 89*b20c38a9SStefan Roese }; 90*b20c38a9SStefan Roese 91*b20c38a9SStefan Roese serial@12100 { 92*b20c38a9SStefan Roese status = "okay"; 93*b20c38a9SStefan Roese }; 94*b20c38a9SStefan Roese 95*b20c38a9SStefan Roese serial@12200 { 96*b20c38a9SStefan Roese status = "okay"; 97*b20c38a9SStefan Roese }; 98*b20c38a9SStefan Roese 99*b20c38a9SStefan Roese serial@12300 { 100*b20c38a9SStefan Roese status = "okay"; 101*b20c38a9SStefan Roese }; 102*b20c38a9SStefan Roese 103*b20c38a9SStefan Roese sata@a0000 { 104*b20c38a9SStefan Roese nr-ports = <2>; 105*b20c38a9SStefan Roese status = "okay"; 106*b20c38a9SStefan Roese }; 107*b20c38a9SStefan Roese 108*b20c38a9SStefan Roese mdio { 109*b20c38a9SStefan Roese phy0: ethernet-phy@0 { 110*b20c38a9SStefan Roese reg = <0>; 111*b20c38a9SStefan Roese }; 112*b20c38a9SStefan Roese }; 113*b20c38a9SStefan Roese 114*b20c38a9SStefan Roese ethernet@70000 { 115*b20c38a9SStefan Roese status = "okay"; 116*b20c38a9SStefan Roese phy = <&phy0>; 117*b20c38a9SStefan Roese phy-mode = "sgmii"; 118*b20c38a9SStefan Roese }; 119*b20c38a9SStefan Roese 120*b20c38a9SStefan Roese usb@50000 { 121*b20c38a9SStefan Roese status = "okay"; 122*b20c38a9SStefan Roese }; 123*b20c38a9SStefan Roese 124*b20c38a9SStefan Roese usb@51000 { 125*b20c38a9SStefan Roese status = "okay"; 126*b20c38a9SStefan Roese }; 127*b20c38a9SStefan Roese 128*b20c38a9SStefan Roese spi0: spi@10600 { 129*b20c38a9SStefan Roese status = "okay"; 130*b20c38a9SStefan Roese u-boot,dm-pre-reloc; 131*b20c38a9SStefan Roese 132*b20c38a9SStefan Roese spi-flash@0 { 133*b20c38a9SStefan Roese u-boot,dm-pre-reloc; 134*b20c38a9SStefan Roese #address-cells = <1>; 135*b20c38a9SStefan Roese #size-cells = <1>; 136*b20c38a9SStefan Roese compatible = "n25q128a13", "jedec,spi-nor"; 137*b20c38a9SStefan Roese reg = <0>; /* Chip select 0 */ 138*b20c38a9SStefan Roese spi-max-frequency = <27777777>; 139*b20c38a9SStefan Roese }; 140*b20c38a9SStefan Roese }; 141*b20c38a9SStefan Roese }; 142*b20c38a9SStefan Roese }; 143*b20c38a9SStefan Roese}; 144