1/* 2 * Device Tree Include file for Marvell Armada XP family SoC 3 * 4 * Copyright (C) 2012 Marvell 5 * 6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 7 * 8 * This file is dual-licensed: you can use it either under the terms 9 * of the GPL or the X11 license, at your option. Note that this dual 10 * licensing only applies to this file, and not this project as a 11 * whole. 12 * 13 * a) This file is free software; you can redistribute it and/or 14 * modify it under the terms of the GNU General Public License as 15 * published by the Free Software Foundation; either version 2 of the 16 * License, or (at your option) any later version. 17 * 18 * This file is distributed in the hope that it will be useful 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * Or, alternatively 24 * 25 * b) Permission is hereby granted, free of charge, to any person 26 * obtaining a copy of this software and associated documentation 27 * files (the "Software"), to deal in the Software without 28 * restriction, including without limitation the rights to use 29 * copy, modify, merge, publish, distribute, sublicense, and/or 30 * sell copies of the Software, and to permit persons to whom the 31 * Software is furnished to do so, subject to the following 32 * conditions: 33 * 34 * The above copyright notice and this permission notice shall be 35 * included in all copies or substantial portions of the Software. 36 * 37 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND 38 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 39 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 40 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 41 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY 42 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 43 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 44 * OTHER DEALINGS IN THE SOFTWARE. 45 * 46 * Contains definitions specific to the Armada XP MV78460 SoC that are not 47 * common to all Armada XP SoCs. 48 */ 49 50#include "armada-xp.dtsi" 51 52/ { 53 model = "Marvell Armada XP MV78460 SoC"; 54 compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp"; 55 56 aliases { 57 gpio0 = &gpio0; 58 gpio1 = &gpio1; 59 gpio2 = &gpio2; 60 }; 61 62 63 cpus { 64 #address-cells = <1>; 65 #size-cells = <0>; 66 enable-method = "marvell,armada-xp-smp"; 67 68 cpu@0 { 69 device_type = "cpu"; 70 compatible = "marvell,sheeva-v7"; 71 reg = <0>; 72 clocks = <&cpuclk 0>; 73 clock-latency = <1000000>; 74 }; 75 76 cpu@1 { 77 device_type = "cpu"; 78 compatible = "marvell,sheeva-v7"; 79 reg = <1>; 80 clocks = <&cpuclk 1>; 81 clock-latency = <1000000>; 82 }; 83 84 cpu@2 { 85 device_type = "cpu"; 86 compatible = "marvell,sheeva-v7"; 87 reg = <2>; 88 clocks = <&cpuclk 2>; 89 clock-latency = <1000000>; 90 }; 91 92 cpu@3 { 93 device_type = "cpu"; 94 compatible = "marvell,sheeva-v7"; 95 reg = <3>; 96 clocks = <&cpuclk 3>; 97 clock-latency = <1000000>; 98 }; 99 }; 100 101 soc { 102 /* 103 * MV78460 has 4 PCIe units Gen2.0: Two units can be 104 * configured as x4 or quad x1 lanes. Two units are 105 * x4/x1. 106 */ 107 pciec: pcie@82000000 { 108 compatible = "marvell,armada-xp-pcie"; 109 status = "disabled"; 110 device_type = "pci"; 111 112 #address-cells = <3>; 113 #size-cells = <2>; 114 115 msi-parent = <&mpic>; 116 bus-range = <0x00 0xff>; 117 118 ranges = 119 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */ 120 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */ 121 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */ 122 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */ 123 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */ 124 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */ 125 0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */ 126 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */ 127 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */ 128 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */ 129 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ 130 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ 131 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */ 132 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */ 133 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */ 134 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */ 135 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */ 136 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */ 137 138 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */ 139 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */ 140 0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */ 141 0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */ 142 0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */ 143 0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */ 144 0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */ 145 0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */ 146 147 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */ 148 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */ 149 150 0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */ 151 0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>; 152 153 pcie1: pcie@1,0 { 154 device_type = "pci"; 155 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; 156 reg = <0x0800 0 0 0 0>; 157 #address-cells = <3>; 158 #size-cells = <2>; 159 #interrupt-cells = <1>; 160 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 161 0x81000000 0 0 0x81000000 0x1 0 1 0>; 162 bus-range = <0x00 0xff>; 163 interrupt-map-mask = <0 0 0 0>; 164 interrupt-map = <0 0 0 0 &mpic 58>; 165 marvell,pcie-port = <0>; 166 marvell,pcie-lane = <0>; 167 clocks = <&gateclk 5>; 168 status = "disabled"; 169 }; 170 171 pcie2: pcie@2,0 { 172 device_type = "pci"; 173 assigned-addresses = <0x82001000 0 0x44000 0 0x2000>; 174 reg = <0x1000 0 0 0 0>; 175 #address-cells = <3>; 176 #size-cells = <2>; 177 #interrupt-cells = <1>; 178 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 179 0x81000000 0 0 0x81000000 0x2 0 1 0>; 180 bus-range = <0x00 0xff>; 181 interrupt-map-mask = <0 0 0 0>; 182 interrupt-map = <0 0 0 0 &mpic 59>; 183 marvell,pcie-port = <0>; 184 marvell,pcie-lane = <1>; 185 clocks = <&gateclk 6>; 186 status = "disabled"; 187 }; 188 189 pcie3: pcie@3,0 { 190 device_type = "pci"; 191 assigned-addresses = <0x82001800 0 0x48000 0 0x2000>; 192 reg = <0x1800 0 0 0 0>; 193 #address-cells = <3>; 194 #size-cells = <2>; 195 #interrupt-cells = <1>; 196 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 197 0x81000000 0 0 0x81000000 0x3 0 1 0>; 198 bus-range = <0x00 0xff>; 199 interrupt-map-mask = <0 0 0 0>; 200 interrupt-map = <0 0 0 0 &mpic 60>; 201 marvell,pcie-port = <0>; 202 marvell,pcie-lane = <2>; 203 clocks = <&gateclk 7>; 204 status = "disabled"; 205 }; 206 207 pcie4: pcie@4,0 { 208 device_type = "pci"; 209 assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>; 210 reg = <0x2000 0 0 0 0>; 211 #address-cells = <3>; 212 #size-cells = <2>; 213 #interrupt-cells = <1>; 214 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 215 0x81000000 0 0 0x81000000 0x4 0 1 0>; 216 bus-range = <0x00 0xff>; 217 interrupt-map-mask = <0 0 0 0>; 218 interrupt-map = <0 0 0 0 &mpic 61>; 219 marvell,pcie-port = <0>; 220 marvell,pcie-lane = <3>; 221 clocks = <&gateclk 8>; 222 status = "disabled"; 223 }; 224 225 pcie5: pcie@5,0 { 226 device_type = "pci"; 227 assigned-addresses = <0x82002800 0 0x80000 0 0x2000>; 228 reg = <0x2800 0 0 0 0>; 229 #address-cells = <3>; 230 #size-cells = <2>; 231 #interrupt-cells = <1>; 232 ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0 233 0x81000000 0 0 0x81000000 0x5 0 1 0>; 234 bus-range = <0x00 0xff>; 235 interrupt-map-mask = <0 0 0 0>; 236 interrupt-map = <0 0 0 0 &mpic 62>; 237 marvell,pcie-port = <1>; 238 marvell,pcie-lane = <0>; 239 clocks = <&gateclk 9>; 240 status = "disabled"; 241 }; 242 243 pcie6: pcie@6,0 { 244 device_type = "pci"; 245 assigned-addresses = <0x82003000 0 0x84000 0 0x2000>; 246 reg = <0x3000 0 0 0 0>; 247 #address-cells = <3>; 248 #size-cells = <2>; 249 #interrupt-cells = <1>; 250 ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0 251 0x81000000 0 0 0x81000000 0x6 0 1 0>; 252 bus-range = <0x00 0xff>; 253 interrupt-map-mask = <0 0 0 0>; 254 interrupt-map = <0 0 0 0 &mpic 63>; 255 marvell,pcie-port = <1>; 256 marvell,pcie-lane = <1>; 257 clocks = <&gateclk 10>; 258 status = "disabled"; 259 }; 260 261 pcie7: pcie@7,0 { 262 device_type = "pci"; 263 assigned-addresses = <0x82003800 0 0x88000 0 0x2000>; 264 reg = <0x3800 0 0 0 0>; 265 #address-cells = <3>; 266 #size-cells = <2>; 267 #interrupt-cells = <1>; 268 ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0 269 0x81000000 0 0 0x81000000 0x7 0 1 0>; 270 bus-range = <0x00 0xff>; 271 interrupt-map-mask = <0 0 0 0>; 272 interrupt-map = <0 0 0 0 &mpic 64>; 273 marvell,pcie-port = <1>; 274 marvell,pcie-lane = <2>; 275 clocks = <&gateclk 11>; 276 status = "disabled"; 277 }; 278 279 pcie8: pcie@8,0 { 280 device_type = "pci"; 281 assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>; 282 reg = <0x4000 0 0 0 0>; 283 #address-cells = <3>; 284 #size-cells = <2>; 285 #interrupt-cells = <1>; 286 ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0 287 0x81000000 0 0 0x81000000 0x8 0 1 0>; 288 bus-range = <0x00 0xff>; 289 interrupt-map-mask = <0 0 0 0>; 290 interrupt-map = <0 0 0 0 &mpic 65>; 291 marvell,pcie-port = <1>; 292 marvell,pcie-lane = <3>; 293 clocks = <&gateclk 12>; 294 status = "disabled"; 295 }; 296 297 pcie9: pcie@9,0 { 298 device_type = "pci"; 299 assigned-addresses = <0x82004800 0 0x42000 0 0x2000>; 300 reg = <0x4800 0 0 0 0>; 301 #address-cells = <3>; 302 #size-cells = <2>; 303 #interrupt-cells = <1>; 304 ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0 305 0x81000000 0 0 0x81000000 0x9 0 1 0>; 306 bus-range = <0x00 0xff>; 307 interrupt-map-mask = <0 0 0 0>; 308 interrupt-map = <0 0 0 0 &mpic 99>; 309 marvell,pcie-port = <2>; 310 marvell,pcie-lane = <0>; 311 clocks = <&gateclk 26>; 312 status = "disabled"; 313 }; 314 315 pcie10: pcie@a,0 { 316 device_type = "pci"; 317 assigned-addresses = <0x82005000 0 0x82000 0 0x2000>; 318 reg = <0x5000 0 0 0 0>; 319 #address-cells = <3>; 320 #size-cells = <2>; 321 #interrupt-cells = <1>; 322 ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0 323 0x81000000 0 0 0x81000000 0xa 0 1 0>; 324 bus-range = <0x00 0xff>; 325 interrupt-map-mask = <0 0 0 0>; 326 interrupt-map = <0 0 0 0 &mpic 103>; 327 marvell,pcie-port = <3>; 328 marvell,pcie-lane = <0>; 329 clocks = <&gateclk 27>; 330 status = "disabled"; 331 }; 332 }; 333 334 internal-regs { 335 gpio0: gpio@18100 { 336 compatible = "marvell,orion-gpio"; 337 reg = <0x18100 0x40>; 338 ngpios = <32>; 339 gpio-controller; 340 #gpio-cells = <2>; 341 interrupt-controller; 342 #interrupt-cells = <2>; 343 interrupts = <82>, <83>, <84>, <85>; 344 }; 345 346 gpio1: gpio@18140 { 347 compatible = "marvell,orion-gpio"; 348 reg = <0x18140 0x40>; 349 ngpios = <32>; 350 gpio-controller; 351 #gpio-cells = <2>; 352 interrupt-controller; 353 #interrupt-cells = <2>; 354 interrupts = <87>, <88>, <89>, <90>; 355 }; 356 357 gpio2: gpio@18180 { 358 compatible = "marvell,orion-gpio"; 359 reg = <0x18180 0x40>; 360 ngpios = <3>; 361 gpio-controller; 362 #gpio-cells = <2>; 363 interrupt-controller; 364 #interrupt-cells = <2>; 365 interrupts = <91>; 366 }; 367 368 eth3: ethernet@34000 { 369 compatible = "marvell,armada-xp-neta"; 370 reg = <0x34000 0x4000>; 371 interrupts = <14>; 372 clocks = <&gateclk 1>; 373 status = "disabled"; 374 }; 375 }; 376 }; 377}; 378 379&pinctrl { 380 compatible = "marvell,mv78460-pinctrl"; 381}; 382