1/* 2 * Device Tree Include file for Marvell Armada XP family SoC 3 * 4 * Copyright (C) 2012 Marvell 5 * 6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 7 * 8 * This file is dual-licensed: you can use it either under the terms 9 * of the GPL or the X11 license, at your option. Note that this dual 10 * licensing only applies to this file, and not this project as a 11 * whole. 12 * 13 * a) This file is free software; you can redistribute it and/or 14 * modify it under the terms of the GNU General Public License as 15 * published by the Free Software Foundation; either version 2 of the 16 * License, or (at your option) any later version. 17 * 18 * This file is distributed in the hope that it will be useful 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * Or, alternatively 24 * 25 * b) Permission is hereby granted, free of charge, to any person 26 * obtaining a copy of this software and associated documentation 27 * files (the "Software"), to deal in the Software without 28 * restriction, including without limitation the rights to use 29 * copy, modify, merge, publish, distribute, sublicense, and/or 30 * sell copies of the Software, and to permit persons to whom the 31 * Software is furnished to do so, subject to the following 32 * conditions: 33 * 34 * The above copyright notice and this permission notice shall be 35 * included in all copies or substantial portions of the Software. 36 * 37 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND 38 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 39 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 40 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 41 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY 42 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 43 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 44 * OTHER DEALINGS IN THE SOFTWARE. 45 * 46 * Contains definitions specific to the Armada XP MV78260 SoC that are not 47 * common to all Armada XP SoCs. 48 */ 49 50#include "armada-xp.dtsi" 51 52/ { 53 model = "Marvell Armada XP MV78260 SoC"; 54 compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp"; 55 56 aliases { 57 gpio0 = &gpio0; 58 gpio1 = &gpio1; 59 gpio2 = &gpio2; 60 }; 61 62 cpus { 63 #address-cells = <1>; 64 #size-cells = <0>; 65 enable-method = "marvell,armada-xp-smp"; 66 67 cpu@0 { 68 device_type = "cpu"; 69 compatible = "marvell,sheeva-v7"; 70 reg = <0>; 71 clocks = <&cpuclk 0>; 72 clock-latency = <1000000>; 73 }; 74 75 cpu@1 { 76 device_type = "cpu"; 77 compatible = "marvell,sheeva-v7"; 78 reg = <1>; 79 clocks = <&cpuclk 1>; 80 clock-latency = <1000000>; 81 }; 82 }; 83 84 soc { 85 /* 86 * MV78260 has 3 PCIe units Gen2.0: Two units can be 87 * configured as x4 or quad x1 lanes. One unit is 88 * x4 only. 89 */ 90 pciec: pcie@82000000 { 91 compatible = "marvell,armada-xp-pcie"; 92 status = "disabled"; 93 device_type = "pci"; 94 95 #address-cells = <3>; 96 #size-cells = <2>; 97 98 msi-parent = <&mpic>; 99 bus-range = <0x00 0xff>; 100 101 ranges = 102 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */ 103 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */ 104 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */ 105 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */ 106 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */ 107 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */ 108 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */ 109 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */ 110 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */ 111 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ 112 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ 113 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */ 114 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */ 115 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */ 116 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */ 117 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */ 118 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */ 119 120 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */ 121 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */ 122 0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */ 123 0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */ 124 0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */ 125 0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */ 126 0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */ 127 0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */ 128 129 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */ 130 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */>; 131 132 pcie1: pcie@1,0 { 133 device_type = "pci"; 134 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; 135 reg = <0x0800 0 0 0 0>; 136 #address-cells = <3>; 137 #size-cells = <2>; 138 #interrupt-cells = <1>; 139 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 140 0x81000000 0 0 0x81000000 0x1 0 1 0>; 141 bus-range = <0x00 0xff>; 142 interrupt-map-mask = <0 0 0 0>; 143 interrupt-map = <0 0 0 0 &mpic 58>; 144 marvell,pcie-port = <0>; 145 marvell,pcie-lane = <0>; 146 clocks = <&gateclk 5>; 147 status = "disabled"; 148 }; 149 150 pcie2: pcie@2,0 { 151 device_type = "pci"; 152 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; 153 reg = <0x1000 0 0 0 0>; 154 #address-cells = <3>; 155 #size-cells = <2>; 156 #interrupt-cells = <1>; 157 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 158 0x81000000 0 0 0x81000000 0x2 0 1 0>; 159 bus-range = <0x00 0xff>; 160 interrupt-map-mask = <0 0 0 0>; 161 interrupt-map = <0 0 0 0 &mpic 59>; 162 marvell,pcie-port = <0>; 163 marvell,pcie-lane = <1>; 164 clocks = <&gateclk 6>; 165 status = "disabled"; 166 }; 167 168 pcie3: pcie@3,0 { 169 device_type = "pci"; 170 assigned-addresses = <0x82000800 0 0x48000 0 0x2000>; 171 reg = <0x1800 0 0 0 0>; 172 #address-cells = <3>; 173 #size-cells = <2>; 174 #interrupt-cells = <1>; 175 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 176 0x81000000 0 0 0x81000000 0x3 0 1 0>; 177 bus-range = <0x00 0xff>; 178 interrupt-map-mask = <0 0 0 0>; 179 interrupt-map = <0 0 0 0 &mpic 60>; 180 marvell,pcie-port = <0>; 181 marvell,pcie-lane = <2>; 182 clocks = <&gateclk 7>; 183 status = "disabled"; 184 }; 185 186 pcie4: pcie@4,0 { 187 device_type = "pci"; 188 assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>; 189 reg = <0x2000 0 0 0 0>; 190 #address-cells = <3>; 191 #size-cells = <2>; 192 #interrupt-cells = <1>; 193 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 194 0x81000000 0 0 0x81000000 0x4 0 1 0>; 195 bus-range = <0x00 0xff>; 196 interrupt-map-mask = <0 0 0 0>; 197 interrupt-map = <0 0 0 0 &mpic 61>; 198 marvell,pcie-port = <0>; 199 marvell,pcie-lane = <3>; 200 clocks = <&gateclk 8>; 201 status = "disabled"; 202 }; 203 204 pcie5: pcie@5,0 { 205 device_type = "pci"; 206 assigned-addresses = <0x82000800 0 0x80000 0 0x2000>; 207 reg = <0x2800 0 0 0 0>; 208 #address-cells = <3>; 209 #size-cells = <2>; 210 #interrupt-cells = <1>; 211 ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0 212 0x81000000 0 0 0x81000000 0x5 0 1 0>; 213 bus-range = <0x00 0xff>; 214 interrupt-map-mask = <0 0 0 0>; 215 interrupt-map = <0 0 0 0 &mpic 62>; 216 marvell,pcie-port = <1>; 217 marvell,pcie-lane = <0>; 218 clocks = <&gateclk 9>; 219 status = "disabled"; 220 }; 221 222 pcie6: pcie@6,0 { 223 device_type = "pci"; 224 assigned-addresses = <0x82000800 0 0x84000 0 0x2000>; 225 reg = <0x3000 0 0 0 0>; 226 #address-cells = <3>; 227 #size-cells = <2>; 228 #interrupt-cells = <1>; 229 ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0 230 0x81000000 0 0 0x81000000 0x6 0 1 0>; 231 bus-range = <0x00 0xff>; 232 interrupt-map-mask = <0 0 0 0>; 233 interrupt-map = <0 0 0 0 &mpic 63>; 234 marvell,pcie-port = <1>; 235 marvell,pcie-lane = <1>; 236 clocks = <&gateclk 10>; 237 status = "disabled"; 238 }; 239 240 pcie7: pcie@7,0 { 241 device_type = "pci"; 242 assigned-addresses = <0x82000800 0 0x88000 0 0x2000>; 243 reg = <0x3800 0 0 0 0>; 244 #address-cells = <3>; 245 #size-cells = <2>; 246 #interrupt-cells = <1>; 247 ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0 248 0x81000000 0 0 0x81000000 0x7 0 1 0>; 249 bus-range = <0x00 0xff>; 250 interrupt-map-mask = <0 0 0 0>; 251 interrupt-map = <0 0 0 0 &mpic 64>; 252 marvell,pcie-port = <1>; 253 marvell,pcie-lane = <2>; 254 clocks = <&gateclk 11>; 255 status = "disabled"; 256 }; 257 258 pcie8: pcie@8,0 { 259 device_type = "pci"; 260 assigned-addresses = <0x82000800 0 0x8c000 0 0x2000>; 261 reg = <0x4000 0 0 0 0>; 262 #address-cells = <3>; 263 #size-cells = <2>; 264 #interrupt-cells = <1>; 265 ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0 266 0x81000000 0 0 0x81000000 0x8 0 1 0>; 267 bus-range = <0x00 0xff>; 268 interrupt-map-mask = <0 0 0 0>; 269 interrupt-map = <0 0 0 0 &mpic 65>; 270 marvell,pcie-port = <1>; 271 marvell,pcie-lane = <3>; 272 clocks = <&gateclk 12>; 273 status = "disabled"; 274 }; 275 276 pcie9: pcie@9,0 { 277 device_type = "pci"; 278 assigned-addresses = <0x82000800 0 0x42000 0 0x2000>; 279 reg = <0x4800 0 0 0 0>; 280 #address-cells = <3>; 281 #size-cells = <2>; 282 #interrupt-cells = <1>; 283 ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0 284 0x81000000 0 0 0x81000000 0x9 0 1 0>; 285 bus-range = <0x00 0xff>; 286 interrupt-map-mask = <0 0 0 0>; 287 interrupt-map = <0 0 0 0 &mpic 99>; 288 marvell,pcie-port = <2>; 289 marvell,pcie-lane = <0>; 290 clocks = <&gateclk 26>; 291 status = "disabled"; 292 }; 293 }; 294 295 internal-regs { 296 gpio0: gpio@18100 { 297 compatible = "marvell,orion-gpio"; 298 reg = <0x18100 0x40>; 299 ngpios = <32>; 300 gpio-controller; 301 #gpio-cells = <2>; 302 interrupt-controller; 303 #interrupt-cells = <2>; 304 interrupts = <82>, <83>, <84>, <85>; 305 }; 306 307 gpio1: gpio@18140 { 308 compatible = "marvell,orion-gpio"; 309 reg = <0x18140 0x40>; 310 ngpios = <32>; 311 gpio-controller; 312 #gpio-cells = <2>; 313 interrupt-controller; 314 #interrupt-cells = <2>; 315 interrupts = <87>, <88>, <89>, <90>; 316 }; 317 318 gpio2: gpio@18180 { 319 compatible = "marvell,orion-gpio"; 320 reg = <0x18180 0x40>; 321 ngpios = <3>; 322 gpio-controller; 323 #gpio-cells = <2>; 324 interrupt-controller; 325 #interrupt-cells = <2>; 326 interrupts = <91>; 327 }; 328 329 eth3: ethernet@34000 { 330 compatible = "marvell,armada-xp-neta"; 331 reg = <0x34000 0x4000>; 332 interrupts = <14>; 333 clocks = <&gateclk 1>; 334 status = "disabled"; 335 }; 336 }; 337 }; 338}; 339 340&pinctrl { 341 compatible = "marvell,mv78260-pinctrl"; 342}; 343